clk: Add brcm,bcm63xx-gate-clk device tree binding
Subsystems (3)
PATCH 1/2 clk: Add brcm,bcm63xx-gate-clk device tree binding
Add device tree binding for the BCM63xx's gated clocks.
The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register.
--- .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +58 -0
@@ -0,0 +1,58 @@ +Broadcom BCM63xx clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The BCM63xx contains clocks gated with a register. Clocks are indexed +by bits in the register and are active high. Clock gate bits are +interleaved with other status bits and configurable clocks in the same +register. + +Required properties: +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk" +- #clock-cells: Should be <1>. +- regmap: The register map phandle +- offset: Offset in the register map for the reboot register (in bytes) +- clocks: The external oscillator clock phandle + +Example: + +periph_clk: periph_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&periph_cntl>; + offset = <0x4>; + + #clock-cells = <1>; + clock-indices = + <1>, <2>, <3>, <4>, <5>, + <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, + <16>, <17>, <18>, <19>, <20>, + <27>, <31>; + clock-output-names = + "vdsl_qproc", "vdsl_afe", "vdsl", "mips", "wlan_ocp", + "dect", "fap0", "fap1", "sar", "robosw", + "pcm", "usbd", "usbh", "ipsec", "spi", + "hsspi", "pcie", "phymips", "gmac", "nand", + "tbus", "robosw250"; +}; + +timer_clk: timer_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&timer_cntl>; + offset = <0x4>; + + #clock-cells = <1>; + clock-indices = <17>, <18>; + clock-output-names = "uto_extin", "usb_ref"; +}; + +ehci0: usb@10002500 { + compatible = "brcm,bcm63168-ehci", "brcm,bcm63xx-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + big-endian; + interrupt-parent = <&periph_intc>; + interrupts = <10>; + clocks = <&periph_clk 13>, <&timer_clk 18>; + phys = <&usbh>; +};
Signature · 4 lines
2.1.4 -- Simon Arlott
PATCH 2/2 clk: bcm63xx: Add BCM63xx gated clock support
The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register.
Enabled by default for BMIPS_GENERIC.
--- MAINTAINERS | 1 + drivers/clk/bcm/Kconfig | 8 ++ drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-bcm63xx.c | 187 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+) create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
MAINTAINERS +1 -0
@@ -2373,6 +2373,7 @@ F: arch/mips/bmips/* F: arch/mips/include/asm/mach-bmips/* F: arch/mips/kernel/*bmips* F: arch/mips/boot/dts/brcm/bcm*.dts* +F: drivers/clk/bcm/clk-bcm63* F: drivers/irqchip/irq-bcm63* F: drivers/irqchip/irq-bcm7* F: drivers/irqchip/irq-brcmstb*
drivers/clk/bcm/Kconfig +8 -0
@@ -14,3 +14,11 @@ config COMMON_CLK_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture + +config CLK_BCM63XX + bool "Broadcom BCM63xx clock support" + depends on BMIPS_GENERIC + depends on COMMON_CLK + default y + help + Enable clock framework support for Broadcom 63xx SoCs
drivers/clk/bcm/Makefile +1 -0
@@ -8,3 +8,4 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o +obj-$(CONFIG_CLK_BCM63XX) += clk-bcm63xx.o
drivers/clk/bcm/clk-bcm63xx.c new file +187 -0
187 lines not on this page · raw message
Signature · 4 lines
2.1.4 -- Simon Arlott
Re: [PATCH 2/2] clk: bcm63xx: Add BCM63xx gated clock support
2015-11-30 12:54 GMT-08:00 Simon Arlott <[email protected]>:
Quoted 9 lines
The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register.
Enabled by default for
BMIPS_GENERIC.Signed-off-by Simon Arlott <[email protected]>---
[snip]
drivers/clk/bcm/Kconfig config COMMON_CLK_IPROC · line 22
Quoted 6 lines
drivers/clk/bcm/Kconfig +6
-0+ +config CLK_BCM63XX + bool "Broadcom BCM63xx clock support" + depends on BMIPS_GENERIC + depends on COMMON_CLK + default y
default BMIPS_GENERIC?
drivers/clk/bcm/clk-bcm63xx.c
Quoted 16 lines
drivers/clk/bcm/Kconfig +2
-0+ help + Enable clock framework support for Broadcom 63xx SoCsdrivers/clk/bcm/Makefile +1
-0@@ -8,3 +8,4 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o +obj-$(CONFIG_CLK_BCM63XX) += clk-bcm63xx.odrivers/clk/bcm/clk-bcm63xx.c new file +0
-0
There is a pending clk-bcm63xx.c implementation, covering BCM63138 in Stephen Boyd's clk/next tree, which you would want to base your patches on, it is not a huge deal to resolve the conflict, and there will be separate entry points and functions based on the compatible string anyway...
drivers/clk/bcm/clk-bcm63xx.c line 11
Quoted 12 lines
drivers/clk/bcm/clk-bcm63xx.c new file +11
-0@@ -0,0 +1,187 @@ +/* +* Copyright 2015 Simon Arlott +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* Based on clk-gate.c: +* Copyright (C) 2010-2011 Canonical Ltd <[email protected]> +* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]> +*/
I am not really anything very specific to 63xx chips in there, in fact, this looks like a fairly generic clk-gate driver using regmap to get its masks and offsets, would it make sense to create clk-gate-regmap.c which exposes the bulk of what you are doing and you could match using a specific compatible string?
--
Florian
2015-11-30 12:52 GMT-08:00 Simon Arlott <[email protected]>:
Quoted 19 lines
Add device tree binding for the BCM63xx's gated clocks.
The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register.
Signed-off-by Simon Arlott <[email protected]>--- .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txtDocumentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +0
-0
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt line 9
Quoted 9 lines
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +9
-0@@ -0,0 +1,58 @@ +Broadcom BCM63xx clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The BCM63xx contains clocks gated with a register. Clocks are indexed +by bits in the register and are active high. Clock gate bits are +interleaved with other status bits and configurable clocks in the same +register.
Most MIPS-based BCM63xx SoCs have clock gating set of registers, these SoCs are pretty much all of them except 63381 (maybe newer ones too), this one uses the PMB interface, like 63138 to control resets and clocks fed to peripherals.
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt line 12
Quoted 3 lines
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +3
-0+ +Required properties: +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk"
I think we would want to start with the lowest common denominator here, which is either 6345 or 6348.
--
Florian
Rob Herring
maintainerQuoted 31 lines · Simon Arlott
Add device tree binding for the BCM63xx's gated clocks.
The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register.
Signed-off-by Simon Arlott <[email protected]>--- .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txtDocumentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +12
-0@@ -0,0 +1,58 @@ +Broadcom BCM63xx clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The BCM63xx contains clocks gated with a register. Clocks are indexed +by bits in the register and are active high. Clock gate bits are +interleaved with other status bits and configurable clocks in the same +register. + +Required properties: +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk"
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt line 22
Quoted 10 lines
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +10
-0+- #clock-cells: Should be <1>. +- regmap: The register map phandle +- offset: Offset in the register map for the reboot register (in bytes) +- clocks: The external oscillator clock phandle + +Example: + +periph_clk: periph_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&periph_cntl>;
What else is in periph_cntrl? Could this all just be part of that node?
Rob
Quoted 6 lines · Rob Herring
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt line 22
Quoted 3 lines · Simon Arlott
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +3
-0+periph_clk: periph_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&periph_cntl>;What else is in
periph_cntrl? Could this all just be part of that node?
uint32 RevID; /* (00) word 0 */
uint32 blkEnables; /* (04) word 1 */ <-- gated clocks
uint32 pll_control; /* (08) word 2 */ <-- system reset controller bit
uint32 deviceTimeoutEn; /* (0c) word 3 */ <-- unknown
uint32 softResetB; /* (10) word 4 */ <-- device reset controller bits
uint32 diagControl; /* (14) word 5 */ <-- unknown
uint32 ExtIrqCfg; /* (18) word 6*/ <-- external interrupt controller
uint32 unused1; /* (1c) word 7 */ <-- (external interrupt controller?)
IrqControl_t IrqControl[3]; /* (20) (40) (60) */ <-- normal interrupt controllerSo it has these clocks, two types of reset controller, and the interrupt controllers, but I've left the interrupt controllers registers out of the syscon device.
For the registers in the "timer" peripheral at the end of the timer/watchdog registers:
uint32 EnSwPLL; <-- unknown
uint32 ClkRstCtl;
#define POR_RESET_STATUS (1 << 31) <-- unknown #define HW_RESET_STATUS (1 << 30) <-- unknown #define SW_RESET_STATUS (1 << 29) <-- unknown #define USB_REF_CLKEN (1 << 18) <-- gated clock #define UTO_EXTIN_CLKEN (1 << 17) <-- gated clock #define UTO_CLK50_SEL (1 << 16) <-- looks like a clock frequency selection bit #define FAP2_PLL_CLKEN (1 << 15) <-- gated clock #define FAP2_PLL_FREQ_SHIFT 12 <-- bits for controlling the frequency #define FAP1_PLL_CLKEN (1 << 11) <-- gated clock #define FAP1_PLL_FREQ_SHIFT 8 <-- bits for controlling the frequency #define WAKEON_DSL (1 << 7) <-- wake on network bit #define WAKEON_EPHY (1 << 6) <-- wake on network bit #define DSL_ENERGY_DETECT_ENABLE (1 << 4) <-- energy saving control for network #define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3) <-- energy saving control for network #define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2) <-- energy saving control for network #define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1) <-- energy saving control for network #define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0) <-- energy saving control for network
I need the usb_ref clock for USB, and I want to be able to disable uto_extin, fap1 and fap2 as they're unused by anything in the device tree.
The full list of registers is here:
https://github.com/lp0/bcm963xx_4.12L.06B_consumer/blob/master/shared/opensource/include/bcm963xx/63268_map_part.h
Signature · 1 line
Simon Arlott
Quoted 8 lines · Simon Arlott
Quoted 6 lines · Rob Herring
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt line 22
Quoted 3 lines · Simon Arlott
Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt new file +3
-0+periph_clk: periph_clk { + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk"; + regmap = <&periph_cntl>;What else is in
periph_cntrl? Could this all just be part of that node?
Quoted 9 lines
uint32 RevID; /* (00) word 0 */
uint32 blkEnables; /* (04) word 1 */ <-- gated clocks
uint32 pll_control; /* (08) word 2 */ <-- system reset controller bit
uint32 deviceTimeoutEn; /* (0c) word 3 */ <-- unknown
uint32 softResetB; /* (10) word 4 */ <-- device reset controller bits
uint32 diagControl; /* (14) word 5 */ <-- unknown
uint32 ExtIrqCfg; /* (18) word 6*/ <-- external interrupt controller
uint32 unused1; /* (1c) word 7 */ <-- (external interrupt controller?)
IrqControl_t IrqControl[3]; /* (20) (40) (60) */ <-- normal interrupt controllerOn the BCM6368 [1], blkEnables also conatains a power domain bit:
uint32 blkEnables; /* (04) word 1 */
#define USBH_IDDQ_EN (1 << 19) #define IPSEC_CLK_EN (1 << 18) #define NAND_CLK_EN (1 << 17) #define DISABLE_GLESS (1 << 16) #define USBH_CLK_EN (1 << 15) #define PCM_CLK_EN (1 << 14) #define UTOPIA_CLK_EN (1 << 13) #define ROBOSW_CLK_EN (1 << 12) #define SAR_CLK_EN (1 << 11) #define USBD_CLK_EN (1 << 10) #define SPI_CLK_EN (1 << 9) #define SWPKT_SAR_CLK_EN (1 << 8) #define SWPKT_USB_CLK_EN (1 << 7) #define PHYMIPS_CLK_EN (1 << 6) #define VDSL_CLK_EN (1 << 5) #define VDSL_BONDING_EN (1 << 4) #define VDSL_AFE_EN (1 << 3) #define VDSL_QPROC_EN (1 << 2)
In order to be able to map these to devices for the BCM63xx SoCs I'm going to define the power controller binding with "power-domain-indices" and "power-domain-names" to mirror the clock binding. The separate clk and generic_pm_domain devices will then handle set/clear of the relevant bits using the regmap.
Signature · 1 line
Simon Arlott