ARM: mxs: fix VDDD brownout setting
Subsystems (2)
PATCH 1/1 ARM: mxs: fix VDDD brownout setting
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value.
Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14
Register takes only 3 bits, that is 0x4.
But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V.
Minimum possible BO level is
1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].
So lets use this value as desired BO value (which is also the same as FSL bootlets use).
--- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +2 -2
@@ -1221,8 +1221,8 @@ void mxs_power_init(void)debug ("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n" );mxs_power_set_vddx (&mxs_vddio_cfg,3300 ,3150 ); -debug ("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n" ); -mxs_power_set_vddx (&mxs_vddd_cfg,1500 ,1000 ); +debug ("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n" ); +mxs_power_set_vddx (&mxs_vddd_cfg,1500 ,1315 );#ifdef CONFIG_MX23 debug ("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n" );mxs_power_set_vddx (&mxs_vddmem_cfg,2500 ,1700 );
Signature · 1 line
2.5.0
PATCH 1/1 ARM: mxs: fix VDDD brownout setting
Quoted 19 lines · Michael Heimpold
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value.
Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) =0x14Register takes only 3 bits, that is
0x4.But
0x4* 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V.Minimum possible BO level is
1500 [mV] -0x7* 25 [mV] = 1315 [mV].
Quoted 7 lines
So lets use this value as desired BO value (which is also the same as FSL bootlets use).
Signed-off-by Michael Heimpold <[email protected]>Cc Marek Vasut <[email protected]>Cc Otavio Salvador <[email protected]>Cc Fabio Estevam <[email protected]>
Uh, nice find. How did you find it?
Best regards,
Marek Vasut
PATCH 1/1 ARM: mxs: fix VDDD brownout setting
Hi Marek,
Am Monday 16 November 2015, 12:01:36 schrieben Sie:
Quoted 24 lines · Michael Heimpold
Quoted 23 lines
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value.
Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) =0x14Register takes only 3 bits, that is
0x4.But
0x4* 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V.Minimum possible BO level is
1500 [mV] -
0x7* 25 [mV] = 1315 [mV].So lets use this value as desired BO value (which is also the same as FSL bootlets use).
Quoted 6 lines
Quoted 4 lines
Signed-off-by Michael Heimpold <[email protected]>Cc Marek Vasut <[email protected]>Cc Otavio Salvador <[email protected]>Cc Fabio Estevam <[email protected]>Uh, nice find. How did you find it?
I was investigating a boot stall with I2SE's Duckbill devices and since we're about to switch from FSL bootlets to U-Boot, I compared the register settings. Then I stumbled about the comment and wondered whether 1.0V BO level makes sense for 1.5V target voltage...
Best regards,
Michael Heimpold
Quoted 5 lines
Acked-by Marek Vasut <[email protected]>Best regards,
Marek Vasut
PATCH 1/1 ARM: mxs: fix VDDD brownout setting
Quoted 1 line · Michael Heimpold
Hi Marek,
Hi!
Quoted 30 lines
Am Monday 16 November 2015, 12:01:36 schrieben Sie:
Quoted 29 lines · Michael Heimpold
Quoted 27 lines
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value.
Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) =0x14Register takes only 3 bits, that is
0x4.But
0x4* 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V.Minimum possible BO level is
1500 [mV] -
0x7* 25 [mV] = 1315 [mV].So lets use this value as desired BO value (which is also the same as FSL bootlets use).
Signed-off-by Michael Heimpold <[email protected]>Cc Marek Vasut <[email protected]>Cc Otavio Salvador <[email protected]>Cc Fabio Estevam <[email protected]>
Quoted 6 lines
Quoted 1 line
Uh, nice find. How did you find it?
I was investigating a boot stall with I2SE's Duckbill devices and since we're about to switch from FSL bootlets to U-Boot, I compared the register settings. Then I stumbled about the comment and wondered whether 1.0V BO level makes sense for 1.5V target voltage...
Heh, nice. Thanks!
Best regards,
Marek Vasut
PATCH 1/1 ARM: mxs: fix VDDD brownout setting
In reply to Michael HeimpoldQuoted 19 lines · Michael Heimpold
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value.
Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) =0x14Register takes only 3 bits, that is
0x4.But
0x4* 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V.Minimum possible BO level is
1500 [mV] -0x7* 25 [mV] = 1315 [mV].
Quoted 8 lines
So lets use this value as desired BO value (which is also the same as FSL bootlets use).
Signed-off-by Michael Heimpold <[email protected]>Cc Marek Vasut <[email protected]>Cc Otavio Salvador <[email protected]>Cc Fabio Estevam <[email protected]>---
Applied to u-boot-imx, thanks!
Best regards,
Stefano Babic
Signature · 5 lines
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