spi: ti_qspi: Use 4-byte opcode for mmap read
PATCH 1/1 spi: ti_qspi: Use 4-byte opcode for mmap read
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.
---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix flash.
drivers/spi/ti_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/spi/ti_qspi.c +3 -3
@@ -48,14 +48,14 @@#define CORE_CTRL_IO 0x4a002558#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0)#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)#define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16)#define QSPI_NUM_DUMMY_BITS (0x0 << 24)/* ti qspi register set */
Signature · 1 line
2.6.3
PATCH 1/1 spi: ti_qspi: Use 4-byte opcode for mmap read
Quoted 5 lines · Vignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.
What about sf side, since we don't have 4-byte opcode support yet?
Quoted 36 lines
Signed-off-by Ravi Babu <[email protected]>[vigneshr at ti.com: Re-word commit description]Signed-off-by Vignesh R <[email protected]>---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix flash.
drivers/spi/ti_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)drivers/spi/ti_qspi.c +3
-4@@ -48,14 +48,14 @@#define CORE_CTRL_IO 0x4a002558#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0)#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)#define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16)#define QSPI_NUM_DUMMY_BITS (0x0 << 24)/* ti qspi register set */ --
Quoted 2 lines
2.6.3
thanks!
Signature · 1 line
Jagan | openedev.
PATCH 1/1 spi: ti_qspi: Use 4-byte opcode for mmap read
Quoted 9 lines · Jagan Teki
Quoted 5 lines · Vignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.What about sf side, since we don't have 4-byte opcode support yet?
Well, the sf is accessing >16MB address space using EXT_ADDR registers via BAR support (for regular spi read/write). But, memory-mapped read doesn't support using EXT_ADDR, hence 4-byte opcode needs to be used for during mmap transfers to access >16MB.
Quoted 41 lines
Quoted 36 lines
Signed-off-by Ravi Babu <[email protected]>[vigneshr at ti.com: Re-word commit description]Signed-off-by Vignesh R <[email protected]>---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix flash.
drivers/spi/ti_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)drivers/spi/ti_qspi.c +3
-4@@ -48,14 +48,14 @@#define CORE_CTRL_IO 0x4a002558#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0)#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)#define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16)#define QSPI_NUM_DUMMY_BITS (0x0 << 24)/* ti qspi register set */ --Quoted 2 lines
2.6.3
thanks!
Signature · 2 lines
Regards Vignesh
PATCH 1/1 spi: ti_qspi: Use 4-byte opcode for mmap read
Quoted 10 lines · Vignesh R
Quoted 7 lines · Jagan Teki
Quoted 5 lines · Vignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.
Quoted 7 lines
Quoted 2 lines
What about sf side, since we don't have 4-byte opcode support yet?
Well, the sf is accessing >16MB address space using
EXT_ADDRregisters via BAR support (for regular spi read/write). But, memory-mapped read doesn't support usingEXT_ADDR, hence 4-byte opcode needs to be used for during mmap transfers to access >16MB.
So, there is no need to have 4-byte opcode support from sf side for memory-mapped reads - true?
Quoted 35 lines
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Quoted 35 lines
Signed-off-by Ravi Babu <[email protected]>[vigneshr at ti.com: Re-word commit description]Signed-off-by Vignesh R <[email protected]>---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix flash.
drivers/spi/ti_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)drivers/spi/ti_qspi.c +3
-3@@ -48,14 +48,14 @@#define CORE_CTRL_IO 0x4a002558#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0)#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)#define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16)#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
Quoted 3 lines
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drivers/spi/ti_qspi.c +0
-1/* ti qspi register set */ --2.6.3
thanks!
--
Jagan.
PATCH 1/1 spi: ti_qspi: Use 4-byte opcode for mmap read
Quoted 14 lines · Jagan Teki
Quoted 13 lines · Vignesh R
Quoted 9 lines · Jagan Teki
Quoted 5 lines · Vignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.What about sf side, since we don't have 4-byte opcode support yet?
Quoted 8 lines
Quoted 4 lines
Well, the sf is accessing >16MB address space using
EXT_ADDRregisters via BAR support (for regular spi read/write). But, memory-mapped read doesn't support usingEXT_ADDR, hence 4-byte opcode needs to be used for during mmap transfers to access >16MB.So, there is no need to have 4-byte opcode support from sf side for memory-mapped reads - true?
Yes, AFAIU, there is no programming required on the sf side to use 4-byte addressing opcode (I have tested this on Macronix MX66L51235F and Spansion S25FL256S)
Quoted 43 lines
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Signed-off-by Ravi Babu <[email protected]>[vigneshr at ti.com: Re-word commit description]Signed-off-by Vignesh R <[email protected]>---
Tested on DRA74 EVM with Spansion flash and AM437X IDK EVM with Macronix
flash.drivers/spi/ti_qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)drivers/spi/ti_qspi.c +3
-3@@ -48,14 +48,14 @@#define CORE_CTRL_IO 0x4a002558#define QSPI_CMD_READ (0x3 << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0)#define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)#define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16)#define QSPI_NUM_DUMMY_BITS (0x0 << 24)Quoted 3 lines
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drivers/spi/ti_qspi.c +0
-0/* ti qspi register set */ Signature · 1 line
2.6.3thanks!
Signature · 1 line
Jagan.
Signature · 2 lines
Regards Vignesh
Quoted 9 lines · Vignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB.Signed-off-by Ravi Babu <[email protected]>[vigneshr at ti.com: Re-word commit description]Signed-off-by Vignesh R <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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