armv8: define usec2ticks function

PATCH New Aneesh Bansal 3 participants 14 messages Dec 8, 2015 – Dec 16, 2015

Subsystems (2)

Arm (32-bit) Crypto API

lore

Share & tools

lore

Aneesh Bansal

author

2015-12-08 08:24 UTC #0 lore raw

PATCH v5 1/5 armv8: define usec2ticks function

usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver.

Signed-off-by Aneesh Bansal <[email protected]>

---
Changes in v5:
- Commit Subject modified

Changes in v4: None

Changes in v3: None

Changes in v2: None (New Patch set created with an additional patch)

 arch/arm/cpu/armv8/generic_timer.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

arch/arm/cpu/armv8/generic_timer.c +11 -0

index 8e60bae..8f47a82 100644
@@ -40,3 +40,14 @@ unsigned long timer_read_counter(void)
 #endif
 	return cntpct;
 }
+
+unsigned long usec2ticks(unsigned long usec)
+{
+	ulong ticks;
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}

Signature · 1 line

1.8.1.4

Aneesh Bansal

author

2015-12-08 08:24 UTC #1 lore raw

PATCH v5 2/5 armv8: Make SEC read/write as snoopable for LS1043

For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues.

Signed-off-by Aneesh Bansal <[email protected]>

---
Changes in v5: None

Changes in v4: None

Changes in v3: None

Changes in v2:
New Patch set created with an additional patch
Commit Subject modified

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm/cpu/armv8/fsl-layerscape/soc.c +5 -0

index 8896b70..85d8df8 100644
@@ -124,11 +124,16 @@ void fsl_lsch3_early_init_f(void)
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_FSL_IFC
 	init_early_memctl_regs();	/* tighten IFC timing */
 #endif
 
+	/* Make SEC reads and writes snoopable */
+	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+		     SCFG_SNPCNFGCR_SECWRSNP);
+
 	/*
 	 * Enable snoop requests and DVM message requests for
 	 * Slave insterface S4 (A53 core cluster)

Signature · 1 line

1.8.1.4

York Sun

Applied

2015-12-15 01:07 UTC #2 lore raw

PATCH v5 2/5 armv8: Make SEC read/write as snoopable for LS1043

Quoted 7 lines · Aneesh Bansal

For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5: None

Quoted 7 lines

Changes in v4: None
Changes in v3: None
Changes in v2:
New Patch set created with an additional patch
Commit Subject modified

Applied to fsl-qoriq master. Awaiting upstream.

York

Aneesh Bansal

author

2015-12-08 08:24 UTC #3 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

In reply to Aneesh Bansal

uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.

The typdef has been moved from include/compiler.h to include/linux/types.h

Signed-off-by Aneesh Bansal <[email protected]>

---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/

Changes in v4: None

Changes in v3: None

Changes in v2: None

 include/compiler.h    | 3 ---
 include/linux/types.h | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)

include/compiler.h +0 -3

index 47c296e..f853ed4 100644
@@ -115,9 +115,6 @@ typedef unsigned int uint;
 #ifdef CONFIG_USE_STDINT
 /* Provided by gcc. */
 #include <stdint.h>
-#else
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
 #endif
 
 #include <linux/string.h>

include/linux/types.h +1 -0

index 6f75be4..c7e8fdb 100644
@@ -124,6 +124,7 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+typedef unsigned long uintptr_t;
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.

Signature · 1 line

1.8.1.4

York Sun

2015-12-08 16:45 UTC #4 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

Quoted 43 lines · Aneesh Bansal

uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
 include/compiler.h    | 3 ---
 include/linux/types.h | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)
include/compiler.h +0 -3
index 47c296e..f853ed4 100644
@@ -115,9 +115,6 @@ typedef unsigned int uint;
 #ifdef CONFIG_USE_STDINT
 /* Provided by gcc. */
 #include <stdint.h>
-#else
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
 #endif
 
 #include <linux/string.h>
include/linux/types.h +0 -0
index 6f75be4..c7e8fdb 100644

include/linux/types.h typedef __UINT64_TYPE__ u_int64_t; · line 130

Quoted 7 lines

include/linux/types.h +1 -0

@@ -124,6 +124,7 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+typedef unsigned long uintptr_t;
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.

Tom,

Please help review this change. I can compile test for power and arm but I don't have the setup for other platforms.

York

York Sun

2015-12-14 02:08 UTC #5 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

I would like to merge this one if no objection.

York

Quoted 61 lines · York Sun

Quoted 43 lines · Aneesh Bansal
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
 include/compiler.h    | 3 ---
 include/linux/types.h | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)
include/compiler.h +0 -3
index 47c296e..f853ed4 100644
@@ -115,9 +115,6 @@ typedef unsigned int uint;
 #ifdef CONFIG_USE_STDINT
 /* Provided by gcc. */
 #include <stdint.h>
-#else
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
 #endif
 
 #include <linux/string.h>
include/linux/types.h +0 -0
index 6f75be4..c7e8fdb 100644
include/linux/types.h typedef __UINT64_TYPE__ u_int64_t; · line 130
Quoted 7 lines
include/linux/types.h +1 -0
@@ -124,6 +124,7 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+typedef unsigned long uintptr_t;
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
Tom,
Please help review this change. I can compile test for power and arm but I don't have the setup for other platforms.
York

York Sun

2015-12-14 02:10 UTC #6 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

In reply to York Sun

Resend with my freescale id.

I would like to merge this patch if no objection.

York

Quoted 61 lines · York Sun

Quoted 43 lines · Aneesh Bansal
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
 include/compiler.h    | 3 ---
 include/linux/types.h | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)
include/compiler.h +0 -3
index 47c296e..f853ed4 100644
@@ -115,9 +115,6 @@ typedef unsigned int uint;
 #ifdef CONFIG_USE_STDINT
 /* Provided by gcc. */
 #include <stdint.h>
-#else
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
 #endif
 
 #include <linux/string.h>
include/linux/types.h +0 -0
index 6f75be4..c7e8fdb 100644
include/linux/types.h typedef __UINT64_TYPE__ u_int64_t; · line 130
Quoted 7 lines
include/linux/types.h +1 -0
@@ -124,6 +124,7 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+typedef unsigned long uintptr_t;
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
Tom,
Please help review this change. I can compile test for power and arm but I don't have the setup for other platforms.
York

York Sun

Applied

2015-12-15 01:07 UTC #7 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

In reply to Aneesh Bansal

Quoted 13 lines · Aneesh Bansal

uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/

Quoted 6 lines

Changes in v4: None
Changes in v3: None
Changes in v2: None

Applied to fsl-qoriq master. Awaiting upstream.

York

York Sun

2015-12-16 03:48 UTC #8 lore raw

PATCH v5 3/5 include/linux: move typdef for uintptr_t

In reply to Aneesh Bansal

Quoted 43 lines · Aneesh Bansal

uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
 include/compiler.h    | 3 ---
 include/linux/types.h | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)
include/compiler.h +0 -3
index 47c296e..f853ed4 100644
@@ -115,9 +115,6 @@ typedef unsigned int uint;
 #ifdef CONFIG_USE_STDINT
 /* Provided by gcc. */
 #include <stdint.h>
-#else
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
 #endif
 
 #include <linux/string.h>
include/linux/types.h +0 -0
index 6f75be4..c7e8fdb 100644

include/linux/types.h typedef __UINT64_TYPE__ u_int64_t; · line 130

Quoted 7 lines

include/linux/types.h +1 -0

@@ -124,6 +124,7 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+typedef unsigned long uintptr_t;
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.

Aneesh,

This change is tested OK on 64-bit hosts, but failed on 32-bit hosts. A second thought, is this change needed? I reverted this one and still passed tests for all aarch64 targets, including ls1043ardb_SECURE_BOOT. I didn't boot it though.

York

Aneesh Bansal

author

2015-12-08 08:24 UTC #9 lore raw

PATCH v5 4/5 armv8/ls1043ardb: add SECURE BOOT target for NOR

In reply to Aneesh Bansal

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by Aneesh Bansal <[email protected]>

---
Changes in v5:
- Commit Subject modified
- Call to sec_init() placed under CONFIG_FSL_CAAM

Changes in v4:
- Fixed compilation break for LS1021AQDS

Changes in v3:
- Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options similar to ls1043ardb_defconfig.
- fsl_secure_boot.h is included outside of ifdef in file include/configs/ls1043ardb.h

Changes in v2:
- New Patch set created with an additional patch
- Pointers typecasted to uintptr_t to remove compiler warnings

 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  4 +--
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  2 +-
 arch/arm/include/asm/fsl_secure_boot.h             |  6 +++-
 board/freescale/common/fsl_validate.c              | 34 ++++++++++++++--------
 board/freescale/ls1043ardb/MAINTAINERS             |  5 ++++
 board/freescale/ls1043ardb/ls1043ardb.c            | 18 +++++++++++-
 common/cmd_blob.c                                  |  6 ++--
 configs/ls1043ardb_SECURE_BOOT_defconfig           |  9 ++++++
 include/configs/ls1043ardb.h                       | 10 +++++++
 include/fsl_validate.h                             |  9 +++++-
 10 files changed, 82 insertions(+), 21 deletions(-)
 create mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig

arch/arm/include/asm/arch-fsl-layerscape/config.h +2 -2

index b5a2d28..6f4773a 100644
@@ -147,8 +147,8 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
 
 #define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +1 -1

index 83caa91..e7def3a 100644
@@ -38,7 +38,7 @@
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
 #define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SNVS_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000

arch/arm/include/asm/fsl_secure_boot.h +5 -1

index f2d4c3c..806302b 100644
@@ -11,13 +11,17 @@
 #define CONFIG_CMD_ESBC_VALIDATE
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_DM
 #define CONFIG_RSA
 #define CONFIG_RSA_FREESCALE_EXP
+
 #ifndef CONFIG_FSL_CAAM
 #define CONFIG_FSL_CAAM
 #endif
 
+#ifndef CONFIG_DM
+#define CONFIG_DM
+#endif
+
 #define CONFIG_KEY_REVOCATION
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images

board/freescale/common/fsl_validate.c +22 ~~-12~~

index 73b6718..b510c71 100644
@@ -15,7 +15,7 @@
 #include <u-boot/rsa-mod-exp.h>
 #include <hash.h>
 #include <fsl_secboot_err.h>
-#ifndef CONFIG_MPC85xx
+#ifdef CONFIG_LS102XA
 #include <asm/arch/immap_ls102xa.h>
 #endif

@@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
 
-	if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+	if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+		   barker_code, ESBC_BARKER_LEN))
 		return -1;
 
 	*csf_addr = csf_hdr_addr;

@@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr)
 	if (get_csf_base_addr(&csf_addr, &flash_base_addr))
 		return -1;
 
-	hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+	hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
 
 	/* For SoC's with Trust Architecture v1 with corenet bus
 	 * the sg table field in CSF header has absolute address

@@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr)
 		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
 		  flash_base_addr);
 #else
-	sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+	sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
 						 (u32)hdr->psgtable);
 #endif

@@ -379,8 +380,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
 #ifdef CONFIG_KEY_REVOCATION
 	if (check_srk(img)) {
 		ret = algo->hash_update(algo, ctx,
-			(u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
-			img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
 		srk = 1;
 	}
 #endif

@@ -438,8 +439,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
 #ifdef CONFIG_KEY_REVOCATION
 	if (check_srk(img)) {
 		ret = algo->hash_update(algo, ctx,
-			(u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
-			img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+		      (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+		      img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
 		key_hash = 1;
 	}
 #endif

@@ -454,8 +455,13 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
 		return ret;
 
 	/* Update hash for actual Image */
+#ifdef CONFIG_ESBC_ADDR_64BIT
 	ret = algo->hash_update(algo, ctx,
-			(u8 *)img->hdr.pimg, img->hdr.img_size, 1);
+		(u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1);
+#else
+	ret = algo->hash_update(algo, ctx,
+		(u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1);
+#endif
 	if (ret)
 		return ret;

@@ -533,7 +539,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
 {
 	char buf[20];
 	struct fsl_secboot_img_hdr *hdr = &img->hdr;
-	void *esbc = (u8 *)img->ehdrloc;
+	void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
 	u8 *k, *s;
 #ifdef CONFIG_KEY_REVOCATION
 	u32 ret;

@@ -549,7 +555,11 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
 	if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
 		return ERROR_ESBC_CLIENT_HEADER_BARKER;
 
+#ifdef CONFIG_ESBC_ADDR_64BIT
+	sprintf(buf, "%llx", hdr->pimg64);
+#else
 	sprintf(buf, "%x", hdr->pimg);
+#endif
 	setenv("img_addr", buf);
 
 	if (!hdr->img_size)

@@ -594,7 +604,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
 	if (!key_found && check_ie(img)) {
 		if (get_ie_info_addr(&img->ie_addr))
 			return ERROR_IE_TABLE_NOT_FOUND;
-		ie_info = (struct ie_key_info *)img->ie_addr;
+		ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
 		if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
 			return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;

@@ -748,7 +758,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
 
 	hdr = &img->hdr;
 	img->ehdrloc = addr;
-	esbc = (u8 *)img->ehdrloc;
+	esbc = (u8 *)(uintptr_t)img->ehdrloc;
 
 	memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));

board/freescale/ls1043ardb/MAINTAINERS +5 -0

index efca5bf..84ffb63 100644
@@ -7,3 +7,8 @@ F:	include/configs/ls1043ardb.h
 F:	configs/ls1043ardb_defconfig
 F:	configs/ls1043ardb_nand_defconfig
 F:	configs/ls1043ardb_sdcard_defconfig
+
+LS1043A_SECURE_BOOT BOARD
+M:	Aneesh Bansal <[email protected]>
+S:	Maintained
+F:	configs/ls1043ardb_SECURE_BOOT_defconfig

board/freescale/ls1043ardb/ls1043ardb.c +17 -1

index cdd50d6..4b4a08d 100644
@@ -18,6 +18,8 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <environment.h>
+#include <fsl_sec.h>
 #include "cpld.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -123,7 +125,21 @@ int config_board_mux(void)
 int misc_init_r(void)
 {
 	config_board_mux();
-
+#ifdef CONFIG_SECURE_BOOT
+	/* In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
 	return 0;
 }
 #endif

common/cmd_blob.c +3 -3

index d3f22a1..ac8b268 100644
@@ -73,9 +73,9 @@ static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	len = simple_strtoul(argv[4], NULL, 16);
 	key_addr = simple_strtoul(argv[5], NULL, 16);
 
-	km_ptr = (uint8_t *)key_addr;
-	src_ptr = (uint8_t *)src_addr;
-	dst_ptr = (uint8_t *)dst_addr;
+	km_ptr = (uint8_t *)(uintptr_t)key_addr;
+	src_ptr = (uint8_t *)(uintptr_t)src_addr;
+	dst_ptr = (uint8_t *)(uintptr_t)dst_addr;
 
 	if (enc)
 		ret = blob_encap(km_ptr, src_ptr, dst_ptr, len);

configs/ls1043ardb_SECURE_BOOT_defconfig new file +9 -0

new file mode 100644
index 0000000..d9d6c97
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
\ No newline at end of file

include/configs/ls1043ardb.h +10 -0

index 7d113a0..5d82cf3 100644
@@ -291,4 +291,14 @@
 #define CONFIG_CMD_EXT2
 #endif
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#define CONFIG_CMD_BLOB
+/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
 #endif /* __LS1043ARDB_H__ */

include/fsl_validate.h +8 -1

index 92dd98b..a62dc74 100644
@@ -83,7 +83,9 @@ struct fsl_secboot_img_hdr {
 	u32 sign_len;		/* length of the signature in bytes */
 	union {
 		u32 psgtable;	/* ptr to SG table */
+#ifndef CONFIG_ESBC_ADDR_64BIT
 		u32 pimg;	/* ptr to ESBC client image */
+#endif
 	};
 	union {
 		u32 sg_entries;	/* no of entries in SG table */

@@ -97,7 +99,12 @@ struct fsl_secboot_img_hdr {
 	u32 reserved1[2];
 	u32 fsl_uid_1;
 	u32 oem_uid_1;
-	u32 reserved2[2];
+	union {
+		u32 reserved2[2];
+#ifdef CONFIG_ESBC_ADDR_64BIT
+		u64 pimg64;	/* 64 bit pointer to ESBC Image */
+#endif
+	};
 	u32 ie_flag;
 	u32 ie_key_sel;
 };

Signature · 1 line

1.8.1.4

York Sun

Applied

2015-12-15 01:10 UTC #10 lore raw

PATCH v5 4/5 armv8/ls1043ardb: add SECURE BOOT target for NOR

Quoted 20 lines · Aneesh Bansal

LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
- Commit Subject modified
- Call to sec_init() placed under CONFIG_FSL_CAAM
Changes in v4:
- Fixed compilation break for LS1021AQDS
Changes in v3:
- Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options similar to ls1043ardb_defconfig.
- fsl_secure_boot.h is included outside of ifdef in file include/configs/ls1043ardb.h

Quoted 4 lines

Changes in v2:
- New Patch set created with an additional patch
- Pointers typecasted to uintptr_t to remove compiler warnings

Applied to fsl-qoriq master. Awaiting upstream.

York

Aneesh Bansal

author

2015-12-08 08:24 UTC #11 lore raw

PATCH v5 5/5 drivers/crypto/fsl: fix endianness issue in RNG

In reply to Aneesh Bansal

For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block.
So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different.

Signed-off-by Aneesh Bansal <[email protected]>

CC Alex Porosanu <[email protected]>

---
Changes in v5: None

Changes in v4: None

Changes in v3: None

Changes in v2: None (New Patch set created with an additional patch)

 drivers/crypto/fsl/jr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

drivers/crypto/fsl/jr.c +2 -6

index f63eacb..b553e3c 100644
@@ -470,17 +470,13 @@ static void kick_trng(int ent_delay)
 	sec_out32(&rng->rtfreqmin, ent_delay >> 2);
 	/* disable maximum frequency count */
 	sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
-	/* read the control register */
-	val = sec_in32(&rng->rtmctl);
 	/*
 	 * select raw sampling in both entropy shifter
 	 * and statistical checker
 	 */
-	sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
+	sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
 	/* put RNG4 into run mode */
-	sec_clrbits32(&val, RTMCTL_PRGM);
-	/* write back the control register */
-	sec_out32(&rng->rtmctl, val);
+	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 }
 
 static int rng_init(void)

Signature · 1 line

1.8.1.4

York Sun

Applied

2015-12-15 01:12 UTC #12 lore raw

PATCH v5 5/5 drivers/crypto/fsl: fix endianness issue in RNG

Quoted 10 lines · Aneesh Bansal

For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block.
So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different.
Signed-off-by Aneesh Bansal <[email protected]>
CC Alex Porosanu <[email protected]>

Quoted 8 lines

---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional patch)

Applied to fsl-qoriq master. Awaiting upstream.

York

York Sun

Applied

2015-12-15 01:06 UTC #13 lore raw

PATCH v5 1/5 armv8: define usec2ticks function

In reply to Aneesh Bansal

Quoted 8 lines · Aneesh Bansal

usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver.
Signed-off-by Aneesh Bansal <[email protected]>
---
Changes in v5:
- Commit Subject modified

Quoted 6 lines

Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional patch)

Applied to fsl-qoriq master. Awaiting upstream.

York