spi: zynq_qspi: Add configuration to disable LQSPI feature

The Device Model sequence alias feature is required by some Uclasses.

Specifically SPI which picks the bus to use based on the sequence. Without this the SPI Uclass will not probe any bus and will fail which prevents SPL from using SPI flash as a boot location.

Signed-off-by Nathan Rossi <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc Linus Walleij <[email protected]>

---
 include/config_uncmd_spl.h | 1 -
 1 file changed, 1 deletion(-)

include/config_uncmd_spl.h +0 -2

index 6e299f6..3b198ae 100644
@@ -29,7 +29,6 @@
 #endif
 
 #undef CONFIG_DM_WARN
-#undef CONFIG_DM_SEQ_ALIAS
 #undef CONFIG_DM_STDIO
 
 #endif /* CONFIG_SPL_BUILD */
--

2.6.2

Update the ZYBO device tree and enable config options that relate to the added devices in the device tree.

Signed-off-by Nathan Rossi <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

---
 arch/arm/dts/zynq-zybo.dts  | 18 ++++++++++++++++++
 configs/zynq_zybo_defconfig |  3 +++
 include/configs/zynq_zybo.h |  1 +
 3 files changed, 22 insertions(+)

arch/arm/dts/zynq-zybo.dts +18 -0

index dcfc00e..fbbb891 100644
@@ -16,6 +16,8 @@
 	aliases {
 		ethernet0 = &gem0;
 		serial0 = &uart1;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {

@@ -28,6 +30,10 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
 };
 
 &clkc {

@@ -45,6 +51,7 @@
 };
 
 &sdhci0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 

@@ -52,3 +59,14 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

configs/zynq_zybo_defconfig +3 -0

index 6f0bd0b..d443e92 100644
@@ -17,3 +17,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_ZYNQ_QSPI=y

include/configs/zynq_zybo.h +0 -0

index 5d1a9d5..c53ba79 100644

Clean up the param checking, removing some code paths that will never happen.

Signed-off-by Nathan Rossi <[email protected]>

Cc Michal Simek <[email protected]>

Cc Tom Rini <[email protected]>

Quoted 3 lines · Nathan Rossi

Clean up the param checking, removing some code paths that will never happen.

Quoted 3 lines

Signed-off-by Nathan Rossi <[email protected]>

Cc Michal Simek <[email protected]>

Cc Tom Rini <[email protected]>

Reported-by Coverity (CID 133251)

Reviewed-by Tom Rini <[email protected]>

When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the device.

Signed-off-by Nathan Rossi <[email protected]>

Cc Jagan Teki <[email protected]>

Cc Siva Durga Prasad Paladugu <[email protected]>

Cc Simon Glass <[email protected]>

---
 drivers/spi/zynq_qspi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

drivers/spi/zynq_qspi.c +4 -0

index 5825c6d..b98663c 100644
@@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK	BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */

@@ -68,6 +69,9 @@ struct zynq_qspi_regs {
 	u32 txd1r;	/* 0x80 */
 	u32 txd2r;	/* 0x84 */
 	u32 txd3r;	/* 0x88 */
+	u32 reserved1[5];
+	u32 lqspicfg;	/* 0xA0 */
+	u32 lqspists;	/* 0xA4 */
 };
 
 /* zynq qspi platform data */

@@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
 		ZYNQ_QSPI_CR_MSTREN_MASK;