Add support for 96boards Dragonboard410C board

This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/serial/Kconfig      |   5 ++
 drivers/serial/Makefile     |   1 +
 drivers/serial/serial_msm.c | 204 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 210 insertions(+)
 create mode 100644 drivers/serial/serial_msm.c

drivers/serial/Kconfig +0 -0

index 1fc287e..f28c093 100644

drivers/serial/Kconfig +0 -0

 endmenu

drivers/serial/Makefile +1 -0

index dd87147..d052175 100644
@@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o

drivers/serial/serial_msm.c new file +9 -0

new file mode 100644
index 0000000..13dad33
@@ -0,0 +1,204 @@
+/*
+ * Qualcomm UART driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * UART will work in Data Mover mode.
+ * Based on Linux driver.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+

drivers/serial/serial_msm.c new file +76 -0

+
+/* Serial registers - this driver works in uartdm mode*/
+
+#define UARTDM_DMRX             0x34 /* Max RX transfer length */
+#define UARTDM_NCF_TX           0x40 /* Number of chars to TX */
+
+#define UARTDM_RXFS             0x50 /* RX channel status register */
+#define UARTDM_RXFS_BUF_SHIFT   0x7  /* Number of bytes in the packing buffer */
+#define UARTDM_RXFS_BUF_MASK    0x7
+
+#define UARTDM_SR                0xA4 /* Status register */
+#define UARTDM_SR_RX_READY       (1 << 0) /* Word is the receiver FIFO */
+#define UARTDM_SR_TX_EMPTY       (1 << 3) /* Transmitter underrun */
+#define UARTDM_SR_UART_OVERRUN   (1 << 4) /* Receive overrun */
+
+#define UARTDM_CR                         0xA8 /* Command register */
+#define UARTDM_CR_CMD_RESET_ERR           (3 << 4) /* Clear overrun error */
+#define UARTDM_CR_CMD_RESET_STALE_INT     (8 << 4) /* Clears stale irq */
+#define UARTDM_CR_CMD_RESET_TX_READY      (3 << 8) /* Clears TX Ready irq*/
+#define UARTDM_CR_CMD_FORCE_STALE         (4 << 8) /* Causes stale event */
+#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
+
+#define UARTDM_IMR                0xB0 /* Interrupt mask register */
+#define UARTDM_ISR                0xB4 /* Interrupt status register */
+#define UARTDM_ISR_TX_READY       0x80 /* TX FIFO empty */
+
+#define UARTDM_TF               0x100 /* UART Transmit FIFO register */
+#define UARTDM_RF               0x140 /* UART Receive FIFO register */
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct msm_serial_data {
+       phys_addr_t base;
+       unsigned chars_cnt; /* number of buffered chars */
+       uint32_t chars_buf; /* buffered chars */
+};
+
+static int msm_serial_getc(struct udevice *dev)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+       unsigned sr;
+       char c;
+
+       /* There was something buffered */
+       if (p->chars_cnt) {
+               c = p->chars_buf & 0xFF;
+               p->chars_buf >>= 8;
+               p->chars_cnt--;
+               return c;
+       }
+
+       /* Clear error in case of buffer overrun */
+       if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
+               writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR);
+
+       /* We need to fetch new character */
+       sr = readl(p->base + UARTDM_SR);
+
+       /* There are at least 4 bytes in fifo */
+       if (sr & UARTDM_SR_RX_READY) {
+               p->chars_buf = readl(p->base + UARTDM_RF);
+               c = p->chars_buf & 0xFF;
+               p->chars_cnt = 3; /* 4 - one read */
+               p->chars_buf >>= 8;
+               return c;
+       }
+
+       /* Check if there is anything in fifo */
+       p->chars_cnt = readl(p->base + UARTDM_RXFS);
+       /* Extract number of characters in UART packing buffer */
+       p->chars_cnt = (p->chars_cnt >> UARTDM_RXFS_BUF_SHIFT) &
+                      UARTDM_RXFS_BUF_MASK;
+       if (!p->chars_cnt)
+               return -EAGAIN;
+

drivers/serial/serial_msm.c new file +35 -0

+
+       return c;
+}
+
+static int msm_serial_putc(struct udevice *dev, const char ch)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+
+       if (!(readl(p->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
+           !(readl(p->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
+               return -EAGAIN;
+
+       writel(UARTDM_CR_CMD_RESET_TX_READY, p->base + UARTDM_CR);
+
+       writel(1, p->base + UARTDM_NCF_TX);
+       writel(ch, p->base + UARTDM_TF);
+       return 0;
+}
+
+static int msm_serial_pending(struct udevice *dev, bool input)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+
+       if (input) {
+               if (p->chars_cnt)
+                       return 1;
+               if (readl(p->base + UARTDM_SR) & UARTDM_SR_RX_READY)
+                       return 1;
+               if (readl(p->base + UARTDM_RXFS))
+                       return 1;
+       }
+       return 0;
+}
+
+static const struct dm_serial_ops msm_serial_ops = {

drivers/serial/serial_msm.c new file +9 -0

+
+       return 0;
+}
+
+static int msm_serial_probe(struct udevice *dev)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+
+       msm_uart_clk_init(dev);

drivers/serial/serial_msm.c new file +17 -0

+       return 0;
+}
+
+static int msm_serial_ofdata_to_platdata(struct udevice *dev)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+
+       p->base = dev_get_addr(dev);
+       if (p->base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+       return 0;
+}
+
+static const struct udevice_id msm_serial_ids[] = {
+       { .compatible = "qcom,msm-uartdm-v1.4" },
+       { }
+};

drivers/serial/serial_msm.c new file +1 -1

+};
--

2.5.0

Hi Mateusz,

On 10 December 2015 at 14:41, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 38 lines

drivers/serial/serial_msm.c new file +38 -0

+static int msm_serial_getc(struct udevice *dev)
+{
+       struct msm_serial_data *p = dev_get_priv(dev);
+       unsigned sr;
+       char c;
+
+       /* There was something buffered */
+       if (p->chars_cnt) {
+               c = p->chars_buf & 0xFF;
+               p->chars_buf >>= 8;
+               p->chars_cnt--;
+               return c;
+       }
+
+       /* Clear error in case of buffer overrun */
+       if (readl(p->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
+               writel(UARTDM_CR_CMD_RESET_ERR, p->base + UARTDM_CR);
+
+       /* We need to fetch new character */
+       sr = readl(p->base + UARTDM_SR);
+
+       /* There are at least 4 bytes in fifo */
+       if (sr & UARTDM_SR_RX_READY) {
+               p->chars_buf = readl(p->base + UARTDM_RF);
+               c = p->chars_buf & 0xFF;
+               p->chars_cnt = 3; /* 4 - one read */
+               p->chars_buf >>= 8;
+               return c;
+       }
+
+       /* Check if there is anything in fifo */
+       p->chars_cnt = readl(p->base + UARTDM_RXFS);
+       /* Extract number of characters in UART packing buffer */
+       p->chars_cnt = (p->chars_cnt >> UARTDM_RXFS_BUF_SHIFT) &
+                      UARTDM_RXFS_BUF_MASK;
+       if (!p->chars_cnt)
+               return -EAGAIN;
+

drivers/serial/serial_msm.c line 105

Quoted 10 lines

drivers/serial/serial_msm.c new file +10 -0

+       /* There is at least one charcter, move it to fifo */
+       writel(UARTDM_CR_CMD_FORCE_STALE, p->base + UARTDM_CR);
+
+       p->chars_buf = readl(p->base + UARTDM_RF);
+       writel(UARTDM_CR_CMD_RESET_STALE_INT, p->base + UARTDM_CR);
+       writel(0xFFFFFF, p->base + UARTDM_DMRX);
+
+       c = p->chars_buf & 0xFF;
+       p->chars_buf >>= 8;
+       p->chars_cnt--;

Can you not rationalise this code a bit? E.g.

if (no chars in fifo) {
try to get some
}
if (no chars in fifo)
return -EAGAIN
extract char from fifo
return ch;

You seem to have three copies of the same code.

Quoted 2 lines

+ uclass_get_device_by_of_offset(UCLASS_CLK, clkd[0], &clk);

Check return value. -ENODEV means there is no clk. Is it OK to have no clock?

drivers/serial/serial_msm.c line 157

Quoted 2 lines

drivers/serial/serial_msm.c new file +2 -0

+       if (clk)
+               clk_set_periph_rate(clk, clkd[1], clk_rate);

If is OK to

drivers/serial/serial_msm.c line 203

Quoted 5 lines

drivers/serial/serial_msm.c new file +5 -0

+       .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
+       .priv_auto_alloc_size = sizeof(struct msm_serial_data),
+       .probe = msm_serial_probe,
+       .ops    = &msm_serial_ops,
+       .flags = DM_FLAG_PRE_RELOC,

Do you need this? You can specify this with u-boot,dm-pre-reloc in the device tree.

Quoted 11 lines

+++ b/drivers/serial/serial_msm.c

drivers/serial/serial_msm.c new file +9 -0

@@ -0,0 +1,204 @@
+/*
+ * Qualcomm UART driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * UART will work in Data Mover mode.
+ * Based on Linux driver.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+

drivers/serial/serial_msm.c line 19

Quoted 10 lines

drivers/serial/serial_msm.c new file +10 -0

+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <serial.h>
+#include <watchdog.h>

Ordering:

common.h
clk.h
dm.h
errno.h
serial.h
watchdog.h
asm/
linux/

2015-12-16 3:58 GMT+09:00 Simon Glass <[email protected]>:

Quoted 24 lines

Quoted 11 lines

+++ b/drivers/serial/serial_msm.c

drivers/serial/serial_msm.c new file +9 -0

@@ -0,0 +1,204 @@
+/*
+ * Qualcomm UART driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * UART will work in Data Mover mode.
+ * Based on Linux driver.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+

drivers/serial/serial_msm.c line 19

Quoted 10 lines

drivers/serial/serial_msm.c new file +10 -0

+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <serial.h>
+#include <watchdog.h>

Ordering:

Quoted 10 lines

common.h
clk.h
dm.h
errno.h
serial.h
watchdog.h
asm/
linux/

No.

Put <linux/*.h> above <asm/*.h>, at least.
(the same order in Linux)

BTW, the "Include file order" in
http://www.denx.de/wiki/U-Boot/CodingStyle

Is this your opinion? Or community's opinion.

Did anybody review it?

Quoted 5 lines

BTW, the "Include file order" in
http://www.denx.de/wiki/U-Boot/CodingStyle

Is this your opinion? Or community's opinion.

Quoted 1 line

Did anybody review it?

This came from Mike Frysinger some years ago on the mailing list and I have followed it since. I took it to be a U-Boot standard and added it to the Wiki at some point. Linux perhaps has linux/ above asm/ for its own reasons (e.g. because it is Linux and needs its headers first) but I don't think that is a good idea for U-Boot. It is unnecessary and makes the sort order more confusing.

I guess Linux sorts headers from global to local.

#include <linux/*.h>    global in the project
#include <asm/*.h>      arch-specific
#include "foo.h"        local in the directory

Likewise, the following makes sense for U-Boot

#include <common.h>

#include <*.h>              global in the project (U-boot orignal)
#include <linux/*.h>        global in the project (come from Linux)
#include <asm/*.h>          arch-specific
#include <asm/arch/*.h>     SoC-specific
#include "foo.h"            local in the directory

if I am not missing something...

Hi Masahiro,

On 23.12.2015 04:52, Masahiro Yamada wrote:
[..]

Quoted 16 lines

I guess Linux sorts headers from global to local.

#include <linux/*.h>    global in the project
#include <asm/*.h>      arch-specific
#include "foo.h"        local in the directory

Likewise, the following makes sense for U-Boot

#include <common.h>

#include <*.h>              global in the project (U-boot orignal)
#include <linux/*.h>        global in the project (come from Linux)
#include <asm/*.h>          arch-specific
#include <asm/arch/*.h>     SoC-specific
#include "foo.h"            local in the directory

Quoted 3 lines

if I am not missing something...

Is it OK with you if for V1 (I'd like to post it soon) I'll use order proposed by Simon (and U-Boot page in general), and then depending on your discussion will swap (or not).

Hi Simon,

Quoted 5 lines

Quoted 5 lines

BTW, the "Include file order" in
http://www.denx.de/wiki/U-Boot/CodingStyle

Is this your opinion? Or community's opinion.

Quoted 9 lines

Quoted 1 line

Did anybody review it?

This came from Mike Frysinger some years ago on the mailing list and I have followed it since. I took it to be a U-Boot standard and added it to the Wiki at some point. Linux perhaps has linux/ above asm/ for its own reasons (e.g. because it is Linux and needs its headers first) but I don't think that is a good idea for U-Boot. It is unnecessary and makes the sort order more confusing.

OK, but I want to know the reason.
Do you remember why Mike Frysinger suggested so?

I guess Linux sorts headers from global to local.

#include <linux/*.h>    global in the project
#include <asm/*.h>      arch-specific
#include "foo.h"        local in the directory

Likewise, the following makes sense for U-Boot

#include <common.h>

#include <*.h>              global in the project (U-boot orignal)
#include <linux/*.h>        global in the project (come from Linux)
#include <asm/*.h>          arch-specific
#include <asm/arch/*.h>     SoC-specific
#include "foo.h"            local in the directory

if I am not missing something...

--
Best Regards
Masahiro Yamada

Hi Masahiro,

Quoted 31 lines · Masahiro Yamada

Hi Simon,

Quoted 5 lines

Quoted 5 lines

BTW, the "Include file order" in
http://www.denx.de/wiki/U-Boot/CodingStyle

Is this your opinion? Or community's opinion.

Quoted 9 lines

Quoted 1 line

Did anybody review it?

This came from Mike Frysinger some years ago on the mailing list and I have followed it since. I took it to be a U-Boot standard and added it to the Wiki at some point. Linux perhaps has linux/ above asm/ for its own reasons (e.g. because it is Linux and needs its headers first) but I don't think that is a good idea for U-Boot. It is unnecessary and makes the sort order more confusing.

OK, but I want to know the reason.
Do you remember why Mike Frysinger suggested so?

I guess Linux sorts headers from global to local.

#include <linux/*.h>    global in the project
#include <asm/*.h>      arch-specific
#include "foo.h"        local in the directory

Likewise, the following makes sense for U-Boot

Quoted 8 lines

#include <common.h>

#include <*.h>              global in the project (U-boot orignal)
#include <linux/*.h>        global in the project (come from Linux)
#include <asm/*.h>          arch-specific
#include <asm/arch/*.h>     SoC-specific
#include "foo.h"            local in the directory

if I am not missing something...

The only difference here seems to be the position of the linux headers. I don't think it is a big deal to change it if you like. The only think I don't like so much is that it seems easier to put 'linux' after 'asm', since it matches the alphabetical order and may avoid confusion. But it's not important to me - mostly we just need to be consistent. If you want to do this, perhaps get an ack from Tom and then update the wiki?

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/gpio/Kconfig    |   7 +++
 drivers/gpio/Makefile   |   2 +-
 drivers/gpio/msm_gpio.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpio/msm_gpio.c

drivers/gpio/Kconfig +0 -0

index e60e9fd..1d9443b 100644

drivers/gpio/Kconfig +1 -0

+
 config ROCKCHIP_GPIO
        bool "Rockchip GPIO driver"
        depends on DM_GPIO

drivers/gpio/Makefile +1 -1

index fb4fd25..9520b1e 100644
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)      += stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)                += zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)      += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)       += hi6220_gpio.o
-
+obj-$(CONFIG_MSM_GPIO)         += msm_gpio.o

drivers/gpio/msm_gpio.c new file +3 -0

new file mode 100644
index 0000000..9bb9e89
@@ -0,0 +1,115 @@
+/*
+ * Qualcomm GPIO driver
+ *

drivers/gpio/msm_gpio.c new file +4 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct msm_gpio_bank {

drivers/gpio/msm_gpio.c new file +64 -0

+       return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       value = !!value;
+       /* set value */
+       writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+       return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+                                    int value)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+       phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+       value = !!value;
+       /* set value */
+       writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+       /* switch direction */
+       writel((readl(reg) & ~GPIO_OE_MASK) | GPIO_OE_ENABLE , reg);
+       return 0;
+}
+
+static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
+}
+
+static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
+               return GPIOF_OUTPUT;
+       return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_msm_ops = {
+       .direction_input        = msm_gpio_direction_input,
+       .direction_output       = msm_gpio_direction_output,
+       .get_value              = msm_gpio_get_value,
+       .set_value              = msm_gpio_set_value,
+       .get_function           = msm_gpio_get_function,
+};
+
+static int msm_gpio_probe(struct udevice *dev)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       priv->base = dev_get_addr(dev);
+       return priv->base == FDT_ADDR_T_NONE;
+}
+
+static int msm_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

drivers/gpio/msm_gpio.c new file +14 -1

+       { }
+};
+
+U_BOOT_DRIVER(gpio_msm) = {
+       .name   = "gpio_msm",
+       .id     = UCLASS_GPIO,
+       .of_match = msm_gpio_ids,
+       .ofdata_to_platdata = msm_gpio_ofdata_to_platdata,
+       .probe  = msm_gpio_probe,
+       .ops    = &gpio_msm_ops,
+       .priv_auto_alloc_size = sizeof(struct msm_gpio_bank),
+};
+
+
--

2.5.0

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/mmc/Kconfig     |   6 ++
 drivers/mmc/Makefile    |   1 +
 drivers/mmc/msm_sdhci.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 156 insertions(+)
 create mode 100644 drivers/mmc/msm_sdhci.c

drivers/mmc/Kconfig +0 -0

index ceae7bc..3f75fa7 100644

drivers/mmc/Kconfig +1 -0

+
 config ROCKCHIP_DWMMC
        bool "Rockchip SD/MMC controller support"
        depends on DM_MMC && OF_CONTROL

drivers/mmc/Makefile +1 -0

index 5d35705..f4fdfca 100644
@@ -49,3 +49,4 @@ else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
 
+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o

drivers/mmc/msm_sdhci.c new file +6 -0

new file mode 100644
index 0000000..96119f0
@@ -0,0 +1,149 @@
+/*
+ * Qualcomm SDHCI driver - SD/eMMC controller
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Based on Linux driver

drivers/mmc/msm_sdhci.c new file +13 -0

+
+/* Non-standard registers needed for SDHCI startup */
+#define SDCC_MCI_POWER   0x0
+#define SDCC_MCI_POWER_SW_RST BIT(7)
+
+/* This is undocumented register */
+#define SDCC_MCI_VERSION             0x50
+#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
+#define SDCC_MCI_VERSION_MAJOR_MASK  (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
+#define SDCC_MCI_VERSION_MINOR_MASK  0xff
+
+#define SDCC_MCI_HC_MODE 0x78
+

drivers/mmc/msm_sdhci.c new file +7 -0

+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

drivers/mmc/msm_sdhci.c new file +11 -0

+       return 0;
+}
+
+static int msm_sdc_probe(struct udevice *dev)
+{
+       struct msm_sdhc *prv = dev_get_priv(dev);
+       struct sdhci_host *host = &prv->host;
+       u32 core_version, core_minor, core_major;
+
+       host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+

drivers/mmc/msm_sdhci.c new file +22 -0

+       }
+
+       /* Enable host-controller mode */
+       writel(1, prv->base + SDCC_MCI_HC_MODE);
+
+       core_version = readl(prv->base + SDCC_MCI_VERSION);
+
+       core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
+       core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+
+       core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+
+       /*
+        * Support for some capabilities is not advertised by newer
+        * controller versions and must be explicitly enabled.
+        */
+       if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
+               u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+               caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
+               writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
+       }
+

drivers/mmc/msm_sdhci.c new file +7 -0

+       return 0;
+}
+
+static int msm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct msm_sdhc *priv = dev_get_priv(dev);
+       struct sdhci_host *host = &priv->host;

drivers/mmc/msm_sdhci.c new file +17 -1

+       return 0;
+}
+
+static const struct udevice_id msm_mmc_ids[] = {
+       { .compatible = "qcom,sdhci-msm-v4" },
+       { }
+};
+
+U_BOOT_DRIVER(msm_sdc_drv) = {
+       .name           = "msm_sdc",
+       .id             = UCLASS_MMC,
+       .of_match       = msm_mmc_ids,
+       .ofdata_to_platdata = msm_ofdata_to_platdata,
+       .probe          = msm_sdc_probe,
+       .remove         = msm_sdc_remove,
+       .priv_auto_alloc_size = sizeof(struct msm_sdhc),
+};
--

2.5.0

Hi Mateusz,

On 10 December 2015 at 14:41, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+                                       "clock-frequency", 400000);
+       uint clkd[2]; /* clk_id and clk_no */
+       fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, 2);
+       clkd[0] = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
+

drivers/mmc/msm_sdhci.c line 56

Quoted 5 lines

drivers/mmc/msm_sdhci.c new file +5 -0

+       struct udevice *clk = NULL;
+       uclass_get_device_by_of_offset(UCLASS_CLK, clkd[0], &clk);
+       if (clk)
+               clk_set_periph_rate(clk, clkd[1], clk_rate);
+

See comments on the previous patch. Also you could move the DT decode code all into your ofdata_to_platdata function (if you like).

Quoted 12 lines

drivers/mmc/msm_sdhci.c new file +11 -0

+       return 0;
+}
+
+static int msm_sdc_probe(struct udevice *dev)
+{
+       struct msm_sdhc *prv = dev_get_priv(dev);
+       struct sdhci_host *host = &prv->host;
+       u32 core_version, core_minor, core_major;
+
+       host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+

drivers/mmc/msm_sdhci.c line 77

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+       /* Init clocks */
+       if (msm_sdc_clk_init(dev))
+               return -EIO;
+
+       /* Reset the core and Enable SDHC mode */
+       writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
+              prv->base + SDCC_MCI_POWER);
+
+       /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
+       mdelay(2);

So why such a long delay? Perhaps you should put the code immediately below int a timeout loop?

start = get_timer(0);

while (readl...) {
   if (get_timer(start) > 2)
      return -ETIMEDOUT;
}

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+}
+
+static int msm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct msm_sdhc *priv = dev_get_priv(dev);
+       struct sdhci_host *host = &priv->host;
+
+       host->name = strdup(dev->name);
+       host->ioaddr = (void *)dev_get_addr(dev);
+       host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

drivers/mmc/msm_sdhci.c line 132

Quoted 6 lines

drivers/mmc/msm_sdhci.c new file +6 -0

+                                        "bus-width", 4);
+       host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+       priv->base = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+                                                     dev->parent->of_offset,
+                                                     dev->of_offset, "reg",
+                                                     1, NULL);

Odd that you are reading the second cell. How come?

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

Hi Simon,

Quoted 4 lines · Simon Glass

Hi Mateusz,

On 10 December 2015 at 14:41, Mateusz Kulikowski
<[email protected]> wrote:

[...]

Quoted 10 lines

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+                                       "clock-frequency", 400000);
+       uint clkd[2]; /* clk_id and clk_no */
+       fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd, 2);
+       clkd[0] = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
+

Quoted 8 lines

drivers/mmc/msm_sdhci.c line 56

Quoted 5 lines

drivers/mmc/msm_sdhci.c new file +5 -0

+       struct udevice *clk = NULL;
+       uclass_get_device_by_of_offset(UCLASS_CLK, clkd[0], &clk);
+       if (clk)
+               clk_set_periph_rate(clk, clkd[1], clk_rate);
+

See comments on the previous patch. Also you could move the DT decode code all into your ofdata_to_platdata function (if you like).

But requesting clock must be handled in probe (i.e. when clock is already bound) right?

Quoted 27 lines

Quoted 13 lines

drivers/mmc/msm_sdhci.c new file +11 -0

+       return 0;
+}
+
+static int msm_sdc_probe(struct udevice *dev)
+{
+       struct msm_sdhc *prv = dev_get_priv(dev);
+       struct sdhci_host *host = &prv->host;
+       u32 core_version, core_minor, core_major;
+
+       host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+

drivers/mmc/msm_sdhci.c line 77

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+       /* Init clocks */
+       if (msm_sdc_clk_init(dev))
+               return -EIO;
+
+       /* Reset the core and Enable SDHC mode */
+       writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
+              prv->base + SDCC_MCI_POWER);
+
+       /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
+       mdelay(2);

So why such a long delay? Perhaps you should put the code immediately below int a timeout loop?

Quoted 6 lines

start = get_timer(0);

while (readl...) {
   if (get_timer(start) > 2)
      return -ETIMEDOUT;
}

I'm not sure if I can do that - I can test it, perhaps it will even work on my board, but it was put explicitly in Linux driver (1-5ms delay).

Documentation says:
"SW should wait until bit 0 (MCLK_REG_WR_ACTIVE) of MCI_STATUS2 register is 0, after writing to MCI_POWER register and before accessing this register again."

But this applies to all writes, not to reset request - I'm not sure how MCI_STATUS2 will behave during reset (it may get zeroed earlier).

Do you really think I should try to decrease this delay?

[...]

Quoted 10 lines

Quoted 10 lines

drivers/mmc/msm_sdhci.c new file +10 -0

+}
+
+static int msm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct msm_sdhc *priv = dev_get_priv(dev);
+       struct sdhci_host *host = &priv->host;
+
+       host->name = strdup(dev->name);
+       host->ioaddr = (void *)dev_get_addr(dev);
+       host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

Quoted 8 lines

drivers/mmc/msm_sdhci.c line 132

Quoted 6 lines

drivers/mmc/msm_sdhci.c new file +6 -0

+                                        "bus-width", 4);
+       host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+       priv->base = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+                                                     dev->parent->of_offset,
+                                                     dev->of_offset, "reg",
+                                                     1, NULL);

Odd that you are reading the second cell. How come?

I tried to use as much parts of original qcom Linux dts as possible. For mmc controller, there are 2 addresses needed:
- - SDCC base (i.e. base of IP block with vendor-specific regs etc.)
- - SDHCI base (i.e. place where SDHCI "standard" registers start)

My assumption is that SDHCI offset may be different on different SoCs, and wanted to have generic driver.

Hi Mateusz,

On 16 December 2015 at 15:46, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 8 lines

I'm not sure if I can do that - I can test it, perhaps it will even work on my board, but it was put explicitly in Linux driver (1-5ms delay).

Documentation says:
"SW should wait until bit 0 (MCLK_REG_WR_ACTIVE) of MCI_STATUS2 register is 0, after writing to MCI_POWER register and before accessing this register again."

Quoted 4 lines

But this applies to all writes, not to reset request - I'm not sure how MCI_STATUS2 will behave during reset (it may get zeroed earlier).

Do you really think I should try to decrease this delay?

Can you change the code to wait until bit 0 is 0, instead of having a delay?

Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm.

Signed-off-by Mateusz Kulikowski <[email protected]>

Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm.

Signed-off-by Mateusz Kulikowski <[email protected]>

This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by Mateusz Kulikowski <[email protected]>

drivers/usb/host/ehci-msm.c new file +15 -0

new file mode 100644
index 0000000..d17a29a
@@ -0,0 +1,198 @@
+/*
+ * Qualcomm EHCI driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
+#include <linux/compat.h>
+#include <dm.h>

drivers/usb/host/ehci-msm.c new file +5 -0

+#define MSM_USB_ULPI_OFFSET 0x170 /* ULPI viewport (PHY) */
+#define MSM_USB_EHCI_OFFSET 0x100 /* Start of EHCI registers */
+
+/* PHY viewport regs */
+#define ULPI_MISC_A_READ         0x96

drivers/usb/host/ehci-msm.c new file +33 -0

+#define SESS_VLD_CTRL         (1 << 25)
+#define USBCMD_RESET   2
+#define USBCMD_ATTACH  1
+
+/* USB2_HSIC_USB_OTG_HS_BASE_USB_OTG_HS_PORTSC */
+#define USB_PORTSC           0x0184
+#define USB_SBUSCFG          0x0090
+#define USB_AHB_MODE         0x0098
+
+#define USB_USBMODE          0x01A8
+#define USBMODE_DEVICE 2
+#define USBMODE_HOST   3
+
+struct msm_ehci_priv {
+	struct ehci_ctrl ctrl; /* Needed by EHCI */
+	phys_addr_t base;
+	phys_addr_t ehci_base;
+	u32 ulpi_base;
+	u32 ulpi_port;
+};
+
+int __weak board_prepare_usb(enum usb_init_type type)
+{
+	return 0;
+}
+
+static void setup_usb_phy(struct msm_ehci_priv *priv)
+{
+	struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port,
+					.viewport_addr = priv->ulpi_base};
+
+	/* Select and enable external configuration with USB PHY */
+	ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_SET,

drivers/usb/host/ehci-msm.c new file +2 -0

+		   ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+}

drivers/usb/host/ehci-msm.c new file +30 -0

+	return 0;
+}
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+	struct msm_ehci_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_get_addr(dev);
+	priv->ehci_base = priv->base + MSM_USB_EHCI_OFFSET;
+	priv->ulpi_base = priv->base + MSM_USB_ULPI_OFFSET;
+	priv->ulpi_port = 0;
+	return 0;
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+	{ .compatible = "qcom,ehci-host", },
+	{ }
+};
+
+U_BOOT_DRIVER(usb_ehci) = {
+	.name	= "ehci_msm",
+	.id	= UCLASS_USB,
+	.of_match = ehci_usb_ids,
+	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+	.probe = ehci_usb_probe,
+	.remove = ehci_usb_remove,
+	.ops	= &ehci_usb_ops,
+	.priv_auto_alloc_size = sizeof(struct msm_ehci_priv),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};

On Thursday, December 10, 2015 at 10:41:41 PM, Mateusz Kulikowski wrote:

drivers/usb/host/ehci-msm.c line 25

Quoted 4 lines

drivers/usb/host/ehci-msm.c new file +4 -0

+
+#ifndef CONFIG_USB_ULPI_VIEWPORT
+#error Please enable CONFIG_USB_ULPI_VIEWPORT
+#endif

The driver should select this in Kconfig instead of this check, right ?

Quoted 1 line

+#define USB_USBCMD (0x0140)

Please drop the parenthesis.

btw. this register layout looks very similar to struct usb_ehci in include/usb/ehci-fsl.h , can the header be made more universal to cover your driver as well ? Then these macros here won't be needed.

drivers/usb/host/ehci-msm.c line 84

Quoted 5 lines

drivers/usb/host/ehci-msm.c new file +5 -0

+	struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port,
+					.viewport_addr = priv->ulpi_base};
+
+	/* Disable VBUS mimicing in the controller. */
+	ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,

This should be a pointer to a field in struct ulpi_regs, so the (u8 *) cast does not seem right. See for example ehci-zynq.c

drivers/usb/host/ehci-msm.c line 154

Quoted 3 lines

drivers/usb/host/ehci-msm.c new file +3 -0

+
+	/* Stop controller. */
+	writel(readl(reg) & ~USBCMD_ATTACH, reg);

This should use clrbits_le32() instead.

drivers/usb/host/ehci-msm.c line 167

Quoted 3 lines

drivers/usb/host/ehci-msm.c new file +3 -0

+	/* Wait for completion */
+	while (readl(reg) & 2)
+		;

Look at wait_for_bit() implementations in the U-Boot tree and avoid the unbounded waiting here please.

Hi,

Thanks for quick review;

Quoted 1 line · Marek Vasut

On Thursday, December 10, 2015 at 10:41:41 PM, Mateusz Kulikowski wrote:

[...]

Quoted 6 lines

drivers/usb/host/ehci-msm.c line 25

Quoted 4 lines

drivers/usb/host/ehci-msm.c new file +4 -0

+
+#ifndef CONFIG_USB_ULPI_VIEWPORT
+#error Please enable CONFIG_USB_ULPI_VIEWPORT
+#endif

The driver should select this in Kconfig instead of this check, right ?

That was my first attempt, but ULPI_VIEWPORT is not Kconfig option, and it seems it just doesn't work :(

It doesn't matter if I add it as
select USB_ULPI_VIEWPORT
in usb KConfig, or forcibly add CONFIG_USB_ULPI_VIEWPORT to .config

[...]

Quoted 3 lines

Quoted 1 line

+#define USB_USBCMD (0x0140)

Please drop the parenthesis.

Doh, missed this one - surely will do it.

Quoted 3 lines

btw. this register layout looks very similar to struct usb_ehci in include/usb/ehci-fsl.h , can the header be made more universal to cover your driver as well ? Then these macros here won't be needed.

You're right.. in fact contrary to what I expected, Qualcomm didn't implemented their own USB controller.

It is designed by Chipidea, and PHY as far as I see is made by Synapsys.

I can use fsl headers with little exception that two registers are marked as reserved: USB_AHB_MODE (0x98) and USB_GENCONFIG_2 (0xA0)

My guess is that it's just different revision/config of IP core.

Do you think it wouldn't look awkward if I use fsl headers?

I think once this series gets to mainline we can create shared driver that will support both vendors.

I also noticed that U-Boot have ci_udc already so there is a chance I make device controller working pretty fast (but I prefer not to include it in this series yet).

[...]

Quoted 8 lines

drivers/usb/host/ehci-msm.c line 84

Quoted 5 lines

drivers/usb/host/ehci-msm.c new file +5 -0

+	struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port,
+					.viewport_addr = priv->ulpi_base};
+
+	/* Disable VBUS mimicing in the controller. */
+	ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,

This should be a pointer to a field in struct ulpi_regs, so the (u8 *) cast does not seem right. See for example ehci-zynq.c

Perhaps I misussed ulpi_viewport code in that case;

The reason is I need to access MISC_A register (0x96+) that is not in ulpi_regs structure - afaik it's vendor-specific.

Any hints how to tackle that properly?

I can of course duplicate ulpi code, but it probably doesn't make much sense.

[...]

Quoted 5 lines

drivers/usb/host/ehci-msm.c line 154

Quoted 3 lines

drivers/usb/host/ehci-msm.c new file +3 -0

+
+	/* Stop controller. */
+	writel(readl(reg) & ~USBCMD_ATTACH, reg);

This should use clrbits_le32() instead.

Ok

[...]

Quoted 6 lines

drivers/usb/host/ehci-msm.c line 167

Quoted 3 lines

drivers/usb/host/ehci-msm.c new file +3 -0

+	/* Wait for completion */
+	while (readl(reg) & 2)
+		;

Look at wait_for_bit() implementations in the U-Boot tree and avoid the unbounded waiting here please.

Ok, btw I noticed there are 3 copies of almost the same code that does that :)

Perhaps I can add a patch to add this function to /lib as it seems it's common use case?

The following drivers would benefit: ehci-msm, zynq_gem, dwc2, ehci-mx6, ohci-lpc32xx

On Sunday, December 13, 2015 at 01:38:41 PM, Mateusz Kulikowski wrote:

Quoted 3 lines

It doesn't matter if I add it as
select USB_ULPI_VIEWPORT
in usb KConfig, or forcibly add CONFIG_USB_ULPI_VIEWPORT to .config

I think it should be quite easily possible to add this to USB Kconfig.

Quoted 6 lines

I can use fsl headers with little exception that two registers are marked as reserved: USB_AHB_MODE (0x98) and USB_GENCONFIG_2 (0xA0)

My guess is that it's just different revision/config of IP core.

Do you think it wouldn't look awkward if I use fsl headers?

Just rename them to ehci-ci.h, that should be the quickest.

Quoted 14 lines

Quoted 8 lines

drivers/usb/host/ehci-msm.c line 84

Quoted 5 lines

drivers/usb/host/ehci-msm.c new file +5 -0

+	struct ulpi_viewport ulpi_vp = {.port_num = priv->ulpi_port,
+					.viewport_addr = priv->ulpi_base};
+
+	/* Disable VBUS mimicing in the controller. */
+	ulpi_write(&ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,

This should be a pointer to a field in struct ulpi_regs, so the (u8 *) cast does not seem right. See for example ehci-zynq.c

Perhaps I misussed ulpi_viewport code in that case;

The reason is I need to access MISC_A register (0x96+) that is not in ulpi_regs structure - afaik it's vendor-specific.

Quoted 4 lines

Any hints how to tackle that properly?

I can of course duplicate ulpi code, but it probably doesn't make much sense.

I don't have a better suggestion, sorry. Let's keep this as-is unless someone can come up with something better. Code duplication is not a good idea, so we won't do that.

Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/Kconfig            |  2 ++
 drivers/Makefile           |  1 +
 drivers/spmi/Kconfig       | 10 +++++++++
 drivers/spmi/Makefile      |  7 ++++++
 drivers/spmi/spmi-uclass.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++
 include/dm/uclass-id.h     |  1 +
 include/spmi/spmi.h        | 44 ++++++++++++++++++++++++++++++++++++++
 7 files changed, 118 insertions(+)
 create mode 100644 drivers/spmi/Kconfig
 create mode 100644 drivers/spmi/Makefile
 create mode 100644 drivers/spmi/spmi-uclass.c
 create mode 100644 include/spmi/spmi.h

drivers/Kconfig +2 -0

index c481e93..4cbe976 100644
@@ -52,6 +52,8 @@ source "drivers/remoteproc/Kconfig"
 
 source "drivers/rtc/Kconfig"
 
+source "drivers/spmi/Kconfig"
+
 source "drivers/serial/Kconfig"
 
 source "drivers/sound/Kconfig"

drivers/Makefile +1 -0

index c9031f2..7ae72c0 100644
@@ -53,6 +53,7 @@ obj-y += pcmcia/
 obj-y += dfu/
 obj-y += rtc/
 obj-y += sound/
+obj-y += spmi/
 obj-y += timer/
 obj-y += tpm/
 obj-y += twserial/

drivers/spmi/Kconfig new file +10 -0

new file mode 100644
index 0000000..2d8d78b
@@ -0,0 +1,10 @@
+menu "SPMI support"
+
+config DM_SPMI
+       bool "Enable SPMI bus support"
+       depends on DM
+       ---help---
+       Select this to enable to support SPMI bus.
+       SPMI (System Power Management Interface) bus is used
+       to connect PMIC devices on various SoCs.
+endmenu

drivers/spmi/Makefile new file +7 -0

new file mode 100644
index 0000000..2015b1a
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-$(CONFIG_DM_SPMI)  += spmi-uclass.o

drivers/spmi/spmi-uclass.c new file +9 -0

new file mode 100644
index 0000000..981da68
@@ -0,0 +1,53 @@
+/*
+ * SPMI bus uclass driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>

drivers/spmi/spmi-uclass.c new file +34 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg)
+{
+       const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+       if (!ops || !ops->read)
+               return -ENOSYS;
+
+       return ops->read(dev, usid, pid, reg);
+}
+
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+                  uint8_t value)
+{
+       const struct dm_spmi_ops *ops = dev_get_driver_ops(dev);
+
+       if (!ops || !ops->write)
+               return -ENOSYS;
+
+       return ops->write(dev, usid, pid, reg, value);
+}
+
+static int msm_spmi_post_bind(struct udevice *dev)
+{
+       return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(spmi) = {
+       .id             = UCLASS_SPMI,
+       .name           = "spmi",
+       .post_bind      = msm_spmi_post_bind,
+};

include/dm/uclass-id.h +1 -0

index 27fa0b6..772e780 100644
@@ -57,6 +57,7 @@ enum uclass_id {
        UCLASS_RTC,             /* Real time clock device */
        UCLASS_SERIAL,          /* Serial UART */
        UCLASS_SPI,             /* SPI bus */
+       UCLASS_SPMI,            /* System Power Management Interface bus */
        UCLASS_SPI_FLASH,       /* SPI flash */
        UCLASS_SPI_GENERIC,     /* Generic SPI flash target */
        UCLASS_SYSCON,          /* System configuration device */

include/spmi/spmi.h new file +1 -0

new file mode 100644
index 0000000..e06a79e
@@ -0,0 +1,44 @@
+#ifndef _SPMI_SPMI_H

include/spmi/spmi.h new file +33 -1

+ */
+struct dm_spmi_ops {
+       int (*read)(struct udevice *dev, int usid, int pid, int reg);
+       int (*write)(struct udevice *dev, int usid, int pid, int reg,
+                    uint8_t value);
+};
+
+/**
+ * spmi_reg_read() - read a register from specific slave/peripheral
+ *
+ * @dev:       SPMI bus to read
+ * @usid       SlaveID
+ * @pid                Peripheral ID
+ * @reg:       Register to read
+ * @return value read on success or negative value of errno.
+ */
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg);
+
+/**
+ * spmi_reg_write() - write a register of specific slave/peripheral
+ *
+ * @dev:       SPMI bus to write
+ * @usid       SlaveID
+ * @pid                Peripheral ID
+ * @reg:       Register to write
+ * @value:     Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+                  uint8_t value);
+
+#endif
+
--

2.5.0

Hi Matheusz,

On 10 December 2015 at 14:41, Mateusz Kulikowski
<[email protected]> wrote:

include/spmi/spmi.h line 11

Quoted 9 lines

include/spmi/spmi.h new file +9 -0

+
+/**
+ * struct dm_spmi_ops - SPMI device I/O interface
+ *
+ * Should be implemented by UCLASS_SPMI device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @read:      read register
+ * @write:     write register

You should describe the args also.

What is different between this and I2C? Could you use that uclass? It seems to have an additional address value (pid)- is that right?

If you do end up with a new uclass, please add a sandbox driver for it and a test.

This PMIC is connected on SPMI bus so needs SPMI support enabled.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/power/pmic/Kconfig  | 14 +++++++
 drivers/power/pmic/Makefile |  1 +
 drivers/power/pmic/pm8916.c | 92 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 107 insertions(+)
 create mode 100644 drivers/power/pmic/pm8916.c

drivers/power/pmic/Kconfig +4 -0

index fb29843..eb1dde0 100644
@@ -89,3 +89,17 @@ config PMIC_TPS65090
        FETs and a battery charger. This driver provides register access
        only, and you can enable the regulator/charger drivers separately if
        required.
+
+config PMIC_PM8916
+       bool "Enable Driver Model for Qualcomm PM8916 PMIC"
+       depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index 91e78f8..ac653c7 100644
@@ -13,6 +13,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_PMIC_PM8916) += pm8916.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o

drivers/power/pmic/pm8916.c new file +5 -0

new file mode 100644
index 0000000..5fe50ef
@@ -0,0 +1,92 @@
+/*
+ * Qualcomm pm8916 pmic driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *

drivers/power/pmic/pm8916.c new file +37 -0

+
+struct pm8916_priv {
+       uint16_t usid; /* Slave ID on SPMI bus */
+};
+
+static int pm8916_reg_count(struct udevice *dev)
+{
+       return 0xFFFF;
+}
+
+static int pm8916_write(struct udevice *dev, uint reg, const uint8_t *buff,
+                       int len)
+{
+       struct pm8916_priv *priv = dev_get_priv(dev);
+
+       if (len != 1)
+               return -EINVAL;
+
+       return spmi_reg_write(dev->parent, priv->usid, EXTRACT_PID(reg),
+                             EXTRACT_REG(reg), *buff);
+}
+
+static int pm8916_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+       struct pm8916_priv *priv = dev_get_priv(dev);
+       int val;
+
+       if (len != 1)
+               return -EINVAL;
+
+       val = spmi_reg_read(dev->parent, priv->usid, EXTRACT_PID(reg),
+                           EXTRACT_REG(reg));
+
+       if (val < 0)
+               return val;
+       *buff = val;
+       return 0;

drivers/power/pmic/pm8916.c new file +19 -1

+       priv->usid = dev_get_addr(dev);
+       return 0;
+}
+
+
+static int pm8916_bind(struct udevice *dev)
+{
+       return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+U_BOOT_DRIVER(pmic_pm8916) = {
+       .name = "pmic_pm8916",
+       .id = UCLASS_PMIC,
+       .of_match = pm8916_ids,
+       .bind = pm8916_bind,
+       .probe = pm8916_probe,
+       .ops = &pm8916_ops,
+       .priv_auto_alloc_size = sizeof(struct pm8916_priv),
+};
--

2.5.0

This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)

Signed-off-by Mateusz Kulikowski <[email protected]>

---

 drivers/gpio/Kconfig       |   7 ++
 drivers/gpio/Makefile      |   1 +
 drivers/gpio/pm8916_gpio.c | 306 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 314 insertions(+)
 create mode 100644 drivers/gpio/pm8916_gpio.c

drivers/gpio/Kconfig +7 -0

index 1d9443b..1fbdfeb 100644
@@ -53,6 +53,13 @@ config MSM_GPIO
        help
          Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
 
+config PM8916_GPIO
+       bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
+       depends on DM_GPIO && PMIC_PM8916
+       help
+         Support for GPIO1-GPIO4 pins and power/reset buttons found on
+         Qualcomm PM8916 PMIC.
+
 config ROCKCHIP_GPIO
        bool "Rockchip GPIO driver"
        depends on DM_GPIO

drivers/gpio/Makefile +1 -0

index 9520b1e..aaa9f8d 100644
@@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO)               += zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)      += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)       += hi6220_gpio.o
 obj-$(CONFIG_MSM_GPIO)         += msm_gpio.o
+obj-$(CONFIG_PM8916_GPIO)      += pm8916_gpio.o

drivers/gpio/pm8916_gpio.c new file +5 -0

new file mode 100644
index 0000000..9214984
@@ -0,0 +1,306 @@
+/*
+ * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *

drivers/gpio/pm8916_gpio.c new file +40 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offset for each gpio */
+#define REG_OFFSET(x)          ((x) * 0x100)
+
+/* Register maps */
+#define REG_STATUS             0x08
+#define REG_STATUS_VAL_MASK    0x1
+
+/* MODE_CTL */
+#define REG_CTL           0x40
+#define REG_CTL_MODE_MASK       0x70
+#define REG_CTL_MODE_INPUT      0x00
+#define REG_CTL_MODE_INOUT      0x20
+#define REG_CTL_MODE_OUTPUT     0x10
+#define REG_CTL_OUTPUT_MASK     0x0F
+
+#define REG_DIG_VIN_CTL        0x41
+#define REG_DIG_VIN_VIN0       0
+
+#define REG_DIG_PULL_CTL       0x42
+#define REG_DIG_PULL_NO_PU     0x5
+
+#define REG_DIG_OUT_CTL        0x45
+#define REG_DIG_OUT_CTL_CMOS   (0x0 << 4)
+#define REG_DIG_OUT_CTL_DRIVE_L 0x1
+
+#define REG_EN_CTL             0x46
+#define REG_EN_CTL_ENABLE      (1 << 7)
+
+struct pm8916_gpio_bank {
+       uint16_t pid; /* Peripheral ID on SPMI bus */
+};
+
+static int pm8916_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+       int val, ret;

drivers/gpio/pm8916_gpio.c new file +71 -0

+
+       /* Select the mode */
+       val = REG_CTL_MODE_INPUT;
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, val);
+       if (ret < 0)
+               return ret;
+
+       /* Set the right pull (no pull) */
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+                            REG_DIG_PULL_NO_PU);
+       if (ret < 0)
+               return ret;
+
+       /* Select the VIN - VIN0, pin is input so it doesn't matter */
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+                            REG_DIG_VIN_VIN0);
+       if (ret < 0)
+               return ret;
+
+       /* Enable the GPIO */
+       val = pmic_reg_read(dev->parent, gpio_base + REG_EN_CTL);
+       if (val < 0)
+               return val;
+
+       val |= REG_EN_CTL_ENABLE;
+
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_EN_CTL, val);
+       return ret;
+}
+
+static int pm8916_gpio_direction_output(struct udevice *dev, unsigned offset,
+                                       int value)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+       int val, ret;
+
+       /* Disable the GPIO */
+       val = pmic_reg_read(dev->parent, gpio_base + REG_EN_CTL);
+       if (val < 0)
+               return val;
+
+       val &= REG_EN_CTL_ENABLE;
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_EN_CTL, val);
+       if (ret < 0)
+               return ret;
+
+       /* Select the mode and output value*/
+       val = REG_CTL_MODE_INOUT | (value ? 1 : 0);
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, val);
+       if (ret < 0)
+               return ret;
+
+       /* Set the right pull */
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+                            REG_DIG_PULL_NO_PU);
+       if (ret < 0)
+               return ret;
+
+       /* Select the VIN - VIN0*/
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+                            REG_DIG_VIN_VIN0);
+       if (ret < 0)
+               return ret;
+
+       /* Set the right dig out control */
+       val = REG_DIG_OUT_CTL_CMOS | REG_DIG_OUT_CTL_DRIVE_L;
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL, val);
+       if (ret < 0)
+               return ret;
+

drivers/gpio/pm8916_gpio.c new file +13 -0

+
+       reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
+       if (reg < 0)
+               return reg;
+
+       return !!(reg & REG_STATUS_VAL_MASK);
+}
+
+static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset,
+                                int value)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);

drivers/gpio/pm8916_gpio.c new file +22 -0

+}
+
+static const struct dm_gpio_ops pm8916_gpio_ops = {
+       .direction_input        = pm8916_gpio_direction_input,
+       .direction_output       = pm8916_gpio_direction_output,
+       .get_value              = pm8916_gpio_get_value,
+       .set_value              = pm8916_gpio_set_value,
+       .get_function           = pm8916_gpio_get_function,
+};
+
+static int pm8916_gpio_probe(struct udevice *dev)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       priv->pid = dev_get_addr(dev);
+       return 0;
+}
+
+static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,

drivers/gpio/pm8916_gpio.c new file +79 -1

+       { }
+};
+
+U_BOOT_DRIVER(gpio_pm8916) = {
+       .name   = "gpio_pm8916",
+       .id     = UCLASS_GPIO,
+       .of_match = pm8916_gpio_ids,
+       .ofdata_to_platdata = pm8916_gpio_ofdata_to_platdata,
+       .probe  = pm8916_gpio_probe,
+       .ops    = &pm8916_gpio_ops,
+       .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
+
+
+/* Add pmic buttons as GPIO as well - there is no generic way for now */
+#define PON_INT_RT_STS                        0x10
+#define KPDPWR_ON_INT_BIT                     0
+#define RESIN_ON_INT_BIT                      1
+
+static int pm8941_pwrkey_get_function(struct udevice *dev, unsigned offset)
+{
+       return GPIOF_INPUT;
+}
+
+static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+
+       int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
+
+       if (reg < 0)
+               return 0;
+
+       switch (offset) {
+       case 0: /* Power button */
+               return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
+               break;
+       case 1: /* Reset button */
+       default:
+               return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
+               break;
+       }
+}
+
+static const struct dm_gpio_ops pm8941_pwrkey_ops = {
+       .get_value              = pm8941_pwrkey_get_value,
+       .get_function           = pm8941_pwrkey_get_function,
+};
+
+static int pm8941_pwrkey_probe(struct udevice *dev)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+
+       priv->pid = dev_get_addr(dev);
+       return 0;
+}
+
+static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       uc_priv->gpio_count = 2;
+       uc_priv->bank_name = "pm8916_key";
+       return 0;
+}
+
+static const struct udevice_id pm8941_pwrkey_ids[] = {
+       { .compatible = "qcom,pm8916-pwrkey" },
+       { }
+};
+
+U_BOOT_DRIVER(pwrkey_pm8941) = {
+       .name   = "pwrkey_pm8916",
+       .id     = UCLASS_GPIO,
+       .of_match = pm8941_pwrkey_ids,
+       .ofdata_to_platdata = pm8941_pwrkey_ofdata_to_platdata,
+       .probe  = pm8941_pwrkey_probe,
+       .ops    = &pm8941_pwrkey_ops,
+       .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
--

2.5.0

arch/arm/mach-snapdragon/clock-apq8016.c new file +6 -0

@@ -0,0 +1,262 @@
+/*
+ * Clock drivers for Qualcomm APQ8016
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Based on Little Kernel driver, simplified

arch/arm/mach-snapdragon/clock-apq8016.c new file +5 -0

+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS        0x2101C
+#define GPLL0_STATUS_ACTIVE BIT(17)
+

arch/arm/mach-snapdragon/clock-apq8016.c new file +22 -0

+/* cmd */
+#define SDCC_CMD_RCGR(n)            (((n*0x1000)) + 0x41004)
+/* cfg */
+#define SDCC_CFG_RCGR(n)            (((n*0x1000)) + 0x41008)
+/* m */
+#define SDCC_M(n)                   (((n*0x1000)) + 0x4100C)
+/* n */
+#define SDCC_N(n)                   (((n*0x1000)) + 0x41010)
+/* d */
+#define SDCC_D(n)                   (((n*0x1000)) + 0x41014)
+/* branch control */
+#define SDCC_APPS_CBCR(n)           (((n*0x1000)) + 0x41018)
+#define SDCC_AHB_CBCR(n)            (((n*0x1000)) + 0x4101C)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR              0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR             0x3028
+#define BLSP1_UART2_APPS_CBCR       0x302C
+#define BLSP1_UART2_APPS_CMD_RCGR   0x3034
+#define BLSP1_UART2_APPS_CFG_RCGR   0x3038