arm: ls1021a: merge SoC specific code in a separate file

PATCH New Yuan Yao 2 participants 15 messages Dec 5, 2015 – Dec 15, 2015 Arm (32-bit)

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Yuan Yao

author

2015-12-05 06:59 UTC #0 lore raw

v3 cover arm: ls1021a: merge SoC specific code in a separate file

arm: ls1021a: merge SoC specific code in a separate file
arm: ls102xa: enable all the snoop signal for masters.
ls102xa: Enable snoop and DVM message requests. armv7/fsl-ls102xa: Workaround for DDR erratum A008514 Changed in v2:

        Update the write value to 63b2_0042h;

move erratum a008336 and a008514 to soc specific file Changed in v3:
Fix a typo issue.
In function "erratum_a008514"
"#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be "#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR"
Changed in v2:
Update the patch commit message.

Yuan Yao

author

2015-12-05 06:59 UTC #1 lore raw

PATCH v3 1/5 arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by Yuan Yao <[email protected]>

---

 arch/arm/cpu/armv7/ls102xa/Makefile             |  1 +
 arch/arm/cpu/armv7/ls102xa/soc.c                | 66 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++
 board/freescale/ls1021aqds/ls1021aqds.c         | 49 +-----------------
 board/freescale/ls1021atwr/ls1021atwr.c         | 42 +---------------
 5 files changed, 83 insertions(+), 87 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h

arch/arm/cpu/armv7/ls102xa/Makefile +1 -0

index 2311468..0228300 100644
@@ -8,6 +8,7 @@ obj-y	+= cpu.o
 obj-y	+= clock.o
 obj-y	+= timer.o
 obj-y	+= fsl_epu.o
+obj-y	+= soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o

arch/arm/cpu/armv7/ls102xa/soc.c new file +66 -0

66 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file +12 -0

new file mode 100644
index 0000000..f10cb91
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */

board/freescale/ls1021aqds/ls1021aqds.c +2 ~~-47~~

73 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c +2 ~~-40~~

66 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 00:55 UTC #2 lore raw

PATCH 1/5 arm: ls1021a: merge SoC specific code in a separate file

Quoted 4 lines · Yuan Yao

Create a soc.c file to put the code for soc special settings.
Signed-off-by Yuan Yao <[email protected]>
---

Applied to fsl-qoriq master. Awaiting upstream.

York

Yuan Yao

author

2015-12-05 06:59 UTC #3 lore raw

PATCH v3 2/5 arm: ls102xa: enable all the snoop signal for masters.

In reply to Yuan Yao

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by Yuan Yao <[email protected]>

---

 arch/arm/cpu/armv7/ls102xa/soc.c                  | 8 ++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++
 2 files changed, 14 insertions(+)

arch/arm/cpu/armv7/ls102xa/soc.c +8 -0

index 0fdd6d4..6036473 100644
@@ -62,5 +62,13 @@ int arch_soc_init(void)
 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 	}
 
+	/* Enable all the snoop signal for various masters */
+	out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+				SCFG_SNPCNFGCR_DCU_RD_WR |
+				SCFG_SNPCNFGCR_SATA_RD_WR |
+				SCFG_SNPCNFGCR_USB3_RD_WR |
+				SCFG_SNPCNFGCR_DBG_RD_WR |
+				SCFG_SNPCNFGCR_EDMA_SNP);
+
 	return 0;
 }

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +6 -0

index 1bcdf04..0527576 100644
@@ -150,6 +150,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
 #define SCFG_QSPI_CLKSEL		0xc0100000
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
+#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
+#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
+#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
+#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
+#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
 #define SCFG_ENDIANCR_LE		0x80000000
 
 /* Supplemental Configuration Unit */

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 00:58 UTC #4 lore raw

PATCH 2/5 arm: ls102xa: enable all the snoop signal for masters.

Quoted 8 lines · Yuan Yao

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by Yuan Yao <[email protected]>
---

Applied to fsl-qoriq master. Awaiting upstream.

York

Yuan Yao

author

2015-12-05 06:59 UTC #5 lore raw

PATCH v3 3/5 ls102xa: Enable snoop and DVM message requests.

In reply to Yuan Yao

Signed-off-by Yuan Yao <[email protected]>

---

 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +7 -1

index 6036473..97ba6d5 100644
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
 	/*
 	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
+	 * All the slave insterfaces.
 	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-12-07 16:58 UTC #6 lore raw

PATCH 3/5 ls102xa: Enable snoop and DVM message requests.

Quoted 17 lines · Yuan Yao

Signed-off-by Yuan Yao <[email protected]>

---

 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +1 -1

index 6036473..97ba6d5 100644
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
 	/*
 	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
+	 * All the slave insterfaces.

arch/arm/cpu/armv7/ls102xa/soc.c int arch_soc_init(void) · line 53

Quoted 10 lines

arch/arm/cpu/armv7/ls102xa/soc.c +6 -0

 	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);

Yuan,

I'm not sure both snoop request and DVM are supported on every port. Do you need to check them before setting?

York

Yao Yuan

author

2015-12-14 10:35 UTC #7 lore raw

PATCH v3 3/5 ls102xa: Enable snoop and DVM message requests.

Hi York,

I'm sorry I'm late replies.

Thanks for reminding me.
We have some investigates and then depend on the document we think both snoop request and DVM are supported on those port. So we think the setting should be ok in here.

Best Regards,
Yuan Yao

Quoted 45 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Tuesday, December 08, 2015 12:58 AM
To: Yuan Yao-B46683 <[email protected]>
Cc: Wang Huan-B18965 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.
Quoted 18 lines · Yuan Yao
Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/ls102xa/soc.c +1 -1
index 6036473..97ba6d5 100644
@@ -40,8 +40,14 @@ int arch_soc_init(void)
 
 	/*
 	 * Enable snoop requests and DVM message requests for
-	 * Slave insterface S4 (A7 core cluster)
+	 * All the slave insterfaces.
arch/arm/cpu/armv7/ls102xa/soc.c int arch_soc_init(void) · line 53
Quoted 10 lines
arch/arm/cpu/armv7/ls102xa/soc.c +6 -0
 	 */
+	out_le32(&cci->slave[0].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[1].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+	out_le32(&cci->slave[2].snoop_ctrl,
+		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
Yuan,
I'm not sure both snoop request and DVM are supported on every port. Do you need to check them before setting?
York

York Sun

2015-12-14 10:43 UTC #8 lore raw

PATCH 3/5 ls102xa: Enable snoop and DVM message requests.

Quoted 8 lines · On 12/14/2015 06:35 PM, Yuan Yao-B46683 wrote:

Hi York,
I'm sorry I'm late replies.
Thanks for reminding me.
We have some investigates and then depend on the document we think both snoop request and DVM are supported on those port. So we think the setting should be ok in here.

I think your conclusion is correct but not your reasoning. I did some digging myself. These registers (snoop control) have top two bits indicating if a slave interface supports snoop and/or DVM messages. If the feature is disabled, writing the enabling bit is ignored.

No more action for you.

York

York Sun

2015-12-15 00:59 UTC #9 lore raw

PATCH 3/5 ls102xa: Enable snoop and DVM message requests.

In reply to Yuan Yao

Quoted 6 lines · Yuan Yao

Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Modified subject, added commit message.
Applied to fsl-qoriq master. Awaiting upstream.

York

Yao Yuan

author

2015-12-15 02:14 UTC #10 lore raw

PATCH v3 3/5 ls102xa: Enable snoop and DVM message requests.

Hi York,

Thanks for your review and modified.

Best Regards,
Yuan Yao

Quoted 21 lines

-----Original Message-----
From: Sun York-R58495
Sent: Tuesday, December 15, 2015 9:00 AM
To: Yuan Yao-B46683 <[email protected]>
Cc: Wang Huan-B18965 <[email protected]>; u-boot at lists.denx.de
Subject: Re: [PATCH 3/5] ls102xa: Enable snoop and DVM message requests.
Quoted 6 lines · Yuan Yao
Signed-off-by Yuan Yao <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
Modified subject, added commit message.
Applied to fsl-qoriq master. Awaiting upstream.
York

Yuan Yao

author

2015-12-05 06:59 UTC #11 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

In reply to Yuan Yao

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by Yuan Yao <[email protected]>

---
Changed in v2:

	Update the write value to 63b2_0042h;

---

 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/ls102xa/soc.c +10 -0

index 97ba6d5..79ae883 100644
@@ -76,5 +76,15 @@ int arch_soc_init(void)
 				SCFG_SNPCNFGCR_DBG_RD_WR |
 				SCFG_SNPCNFGCR_EDMA_SNP);
 
+	/*
+	 * Memory controller require a register write before being enabled.
+	 * Affects: DDR
+	 * Register: EDDRTQCFG
+	 * Description: Memory controller performance is not optimal with
+	 *		default internal target queue register values.
+	 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+	 */
+	out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
 	return 0;
 }

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -1

index 0527576..c584c9f 100644
@@ -228,7 +228,7 @@ struct ccsr_scfg {
 	u32 scfgrevcr;
 	u32 coresrencr;
 	u32 pex2pmrdsr;
-	u32 ddrc1cr;
+	u32 eddrtqcfg;
 	u32 ddrc2cr;
 	u32 ddrc3cr;
 	u32 ddrc4cr;

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 01:00 UTC #12 lore raw

PATCH v2 4/5 armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Quoted 11 lines · Yuan Yao

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by Yuan Yao <[email protected]>
---
Changed in v2:
	Update the write value to 63b2_0042h;
---

Applied to fsl-qoriq master. Awaiting upstream.

York

Yuan Yao

author

2015-12-05 06:59 UTC #13 lore raw

PATCH v3 5/5 move erratum a008336 and a008514 to soc specific file

In reply to Yuan Yao

As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by Yuan Yao <[email protected]>

---
Changed in v3:
Fix a typo issue.
In function "erratum_a008514"
"#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be "#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR"
Changed in v2:
Update the patch commit message.
---

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++
 drivers/ddr/fsl/fsl_ddr_gen4.c          | 34 ------------------------------
 2 files changed, 37 insertions(+), 34 deletions(-)

arch/arm/cpu/armv8/fsl-layerscape/soc.c +37 -0

index 8896b70..738b113 100644
@@ -14,6 +14,41 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a008336(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b30002);
+#endif
+#endif
+}
+
+/*
+ * This erratum requires a register write before being Memory
+ * controller 3 being enabled.
+ */
+static void erratum_a008514(void)
+{
+	u32 *eddrtqcr1;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+	out_le32(eddrtqcr1, 0x63b20002);
+#endif
+#endif
+}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 #define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"

@@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void)
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
 	erratum_a009203();
+	erratum_a008514();
+	erratum_a008336();
 }
 
 #elif defined(CONFIG_LS1043A)

drivers/ddr/fsl/fsl_ddr_gen4.c +0 ~~-34~~

index 1de7b72..2e5fe62 100644
@@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 temp_sdram_cfg;
 	u32 total_gb_size_per_controller;
 	int timeout;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-	u32 *eddrtqcr1;
-#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 	u32 temp32, mr6;
 #endif

@@ -66,36 +62,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	switch (ctrl_num) {
 	case 0:
 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-#endif
 		break;
 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	case 1:
 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 	case 2:
 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
-#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 	case 3:
 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
-	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
-		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
-#endif
 		break;
 #endif
 	default:

@@ -106,20 +86,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	if (step == 2)
 		goto step2;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008336 only applies to general DDR controllers */
-	if ((ctrl_num == 0) || (ctrl_num == 1))
-#endif
-		ddr_out32(eddrtqcr1, 0x63b30002);
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
-	/* A008514 only applies to DP-DDR controler */
-	if (ctrl_num == 2)
-#endif
-		ddr_out32(eddrtqcr1, 0x63b20002);
-#endif
 	if (regs->ddr_eor)
 		ddr_out32(&ddr->eor, regs->ddr_eor);

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 01:00 UTC #14 lore raw

PATCH v3 5/5 move erratum a008336 and a008514 to soc specific file

Quoted 4 lines · Yuan Yao

As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by Yuan Yao <[email protected]>

Quoted 9 lines

---
Changed in v3:
Fix a typo issue.
In function "erratum_a008514"
"#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR" should be "#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR"
Changed in v2:
Update the patch commit message.
---

Applied to fsl-qoriq master. Awaiting upstream.

York