arm: ls102x: add get_svr and IS_SVR_REV helper

PATCH New Shengzhou Liu 2 participants 6 messages Nov 20, 2015 – Dec 15, 2015

Subsystems (2)

Arm (32-bit) PowerPC

lore

Share & tools

lore

Shengzhou Liu

author

2015-11-20 07:52 UTC #0 lore raw

PATCH 1/3 arm: ls102x: add get_svr and IS_SVR_REV helper

Signed-off-by Shengzhou Liu <[email protected]>

---
 arch/arm/cpu/armv7/ls102xa/cpu.c                  | 8 ++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++
 2 files changed, 13 insertions(+)

arch/arm/cpu/armv7/ls102xa/cpu.c +8 -0

index 14ae2a3..74cd2cb 100644
@@ -209,6 +209,14 @@ void enable_caches(void)
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
+
+uint get_svr(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	return in_be32(&gur->svr);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +5 -0

index c59c93a..2d0832a 100644
@@ -11,6 +11,8 @@
 #define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
+#define IS_SVR_REV(svr, maj, min) \
+		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
 
 #define SOC_VER_SLS1020		0x00
 #define SOC_VER_LS1020		0x10

@@ -427,4 +429,7 @@ struct ccsr_ahci {
 	u32 pberr;	/* port 0/1 BIST error */
 	u32 cmds;	/* port 0/1 CMD status error */
 };
+
+uint get_svr(void);
+
 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */

Signature · 1 line

2.1.0.27.g96db324

Shengzhou Liu

author

2015-11-20 07:52 UTC #1 lore raw

PATCH 2/3 fsl/errata: move fsl_errata.h to common directory

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs.

Signed-off-by Shengzhou Liu <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c          |  2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c            |  2 +-
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |  2 +-
 arch/powerpc/include/asm/fsl_errata.h          | 53 ----------------------
 include/fsl_errata.h                           | 61 ++++++++++++++++++++++++++
 5 files changed, 64 insertions(+), 56 deletions(-)
 delete mode 100644 arch/powerpc/include/asm/fsl_errata.h
 create mode 100644 include/fsl_errata.h

arch/powerpc/cpu/mpc85xx/cmd_errata.c +1 -1

index b368562..a493556 100644
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/compiler.h>
-#include <asm/fsl_errata.h>
+#include <fsl_errata.h>
 #include <asm/processor.h>
 #include <fsl_usb.h>
 #include "fsl_corenet_serdes.h"

arch/powerpc/cpu/mpc85xx/cpu_init.c +1 -1

index eb0534b..51b5f5e 100644
@@ -19,7 +19,7 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
-#include <asm/fsl_errata.h>
+#include <fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +1 -1

index acb1353..f89c94e 100644
@@ -11,7 +11,7 @@
 #include <asm/processor.h>
 #include <asm/fsl_law.h>
 #include <asm/errno.h>
-#include <asm/fsl_errata.h>
+#include <fsl_errata.h>
 #include "fsl_corenet2_serdes.h"
 
 #ifdef CONFIG_SYS_FSL_SRDS_1

arch/powerpc/include/asm/fsl_errata.h deleted +0 ~~-53~~

53 lines not on this page · raw message

include/fsl_errata.h new file +61 -0

61 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 00:43 UTC #2 lore raw

PATCH 2/3 fsl/errata: move fsl_errata.h to common directory

Quoted 5 lines · Shengzhou Liu

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs.
Signed-off-by Shengzhou Liu <[email protected]>
---

Applied to fsl-qoriq master. Awaiting upstream.

York

Shengzhou Liu

author

2015-11-20 07:52 UTC #3 lore raw

PATCH 3/3 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

In reply to Shengzhou Liu

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2.

Signed-off-by Shengzhou Liu <[email protected]>

---
 arch/powerpc/include/asm/config_mpc85xx.h |  2 ++
 drivers/ddr/fsl/fsl_ddr_gen4.c            |  9 ++++++---
 include/fsl_errata.h                      | 31 +++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 3 deletions(-)

arch/powerpc/include/asm/config_mpc85xx.h +2 -0

index aabe253..6308c6e 100644
@@ -797,6 +797,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 
 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)

@@ -844,6 +845,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500

drivers/ddr/fsl/fsl_ddr_gen4.c +6 -3

index 4eef047..1ef220b 100644
@@ -10,6 +10,7 @@
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#include <fsl_errata.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL

@@ -175,9 +176,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	/* Erratum applies when accumulated ECC is used, or DBI is enabled */
 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
-	if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
-	    IS_DBI(regs->ddr_sdram_cfg_3))
-		ddr_setbits32(ddr->debug[28], 0x9 << 20);
+	if (has_erratum_a008378()) {
+		if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+		    IS_DBI(regs->ddr_sdram_cfg_3))
+			ddr_setbits32(&ddr->debug[28], 0x9 << 20);
+	}
 #endif
 
 	/*

include/fsl_errata.h +31 -0

index 8f81e4c..283cfcf 100644
@@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+static inline bool has_erratum_a008378(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+
+	switch (soc) {
+#ifdef CONFIG_LS102XA
+	case SOC_VER_LS1020:
+	case SOC_VER_LS1021:
+	case SOC_VER_LS1022:
+	case SOC_VER_SLS1020:
+		return IS_SVR_REV(svr, 1, 0);
+#endif
+#ifdef CONFIG_PPC
+	case SVR_T1023:
+	case SVR_T1024:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T1020:
+	case SVR_T1022:
+	case SVR_T1040:
+	case SVR_T1042:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+	default:
+		return false;
+	}
+}
+#endif
+
 #endif /*  _FSL_ERRATA_H */

Signature · 1 line

2.1.0.27.g96db324

York Sun

Applied

2015-12-15 00:44 UTC #4 lore raw

PATCH 3/3 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

Quoted 6 lines · Shengzhou Liu

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2.
Signed-off-by Shengzhou Liu <[email protected]>
---

Applied to fsl-qoriq master. Awaiting upstream.

York

York Sun

Applied

2015-12-15 00:43 UTC #5 lore raw

PATCH 1/3 arm: ls102x: add get_svr and IS_SVR_REV helper

In reply to Shengzhou Liu

Quoted 2 lines · Shengzhou Liu

Signed-off-by Shengzhou Liu <[email protected]>
---

Applied to fsl-qoriq master. Awaiting upstream.

York