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armv8/ls1043ardb: Add support for >2GB memory

PATCH New Mingkai Hu 2 participants 2 messages Nov 23, 2015 – Dec 15, 2015 Arm (32-bit)

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Mingkai Hu

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PATCH 1/1 armv8/ls1043ardb: Add support for >2GB memory

From: Shaohui Xie <[email protected]>

This patch also expose the complete DDR region(s) to Linux.

Signed-off-by Shaohui Xie <[email protected]>
Signed-off-by Mingkai Hu <[email protected]>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++--
 board/freescale/ls1043ardb/ddr.c                  |  9 ++++++++-
 board/freescale/ls1043ardb/ls1043ardb.c           | 10 ++++++++++
 include/configs/ls1043a_common.h                  |  1 +
 include/configs/ls1043ardb.h                      |  2 +-
 5 files changed, 22 insertions(+), 4 deletions(-)
arch/arm/include/asm/arch-fsl-layerscape/config.h +2 -2
index 87bb937..aba360e 100644
@@ -103,8 +103,8 @@
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
 #define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
board/freescale/ls1043ardb/ddr.c +8 -1
index b181579..249d056 100644
@@ -187,5 +187,12 @@ phys_size_t initdram(int board_type)
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+					  CONFIG_SYS_DDR_BLOCK1_SIZE;
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+	}
 }
board/freescale/ls1043ardb/ls1043ardb.c +10 -0
index 9032ed3..c4f2603 100644
@@ -114,6 +114,16 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
include/configs/ls1043a_common.h +1 -0
index 6b9856a..677d281 100644
@@ -44,6 +44,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
 #define CPU_RELEASE_ADDR               secondary_boot_func
include/configs/ls1043ardb.h +1 -1
index 307d947..acffe6e 100644
@@ -27,7 +27,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		2
 
 #define CONFIG_SYS_SPD_BUS_NUM		0
Signature · 1 line
2.1.0.27.g96db324