armv8/ls1043a: remove print info

PATCH New Mingkai Hu 2 participants 10 messages Dec 7, 2015 – Dec 16, 2015

Subsystems (2)

Network drivers Arm (32-bit)

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Mingkai Hu

author

2015-12-07 08:58 UTC #0 lore raw

PATCH 1/5 armv8/ls1043a: remove print info

Signed-off-by Mingkai Hu <[email protected]>

---
 drivers/net/fm/ls1043.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

drivers/net/fm/ls1043.c +1 -8

index cf2cc95..93ba318 100644
@@ -54,11 +54,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
-	if (is_device_disabled(port)) {
-		printf("%s:%d: port(%d) is disabled\n", __func__,
-		       __LINE__, port);
+	if (is_device_disabled(port))
 		return PHY_INTERFACE_MODE_NONE;
-	}
 
 	if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
 		return PHY_INTERFACE_MODE_XGMII;

@@ -69,15 +66,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	if (port == FM1_DTSEC3)
 		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
 				FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
-			printf("%s:%d: port(FM1_DTSEC3) is OK\n",
-			       __func__, __LINE__);
 			return PHY_INTERFACE_MODE_RGMII;
 		}
 	if (port == FM1_DTSEC4)
 		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
 				FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
-			printf("%s:%d: port(FM1_DTSEC4) is OK\n",
-			       __func__, __LINE__);
 			return PHY_INTERFACE_MODE_RGMII;
 		}

Signature · 1 line

2.1.0.27.g96db324

Mingkai Hu

author

2015-12-07 08:58 UTC #1 lore raw

PATCH 2/5 armv8/fsl_lsch2: fix DCSR_DCFG address

Signed-off-by Mingkai Hu <[email protected]>

---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +1 -1

index 83caa91..3869177 100644
@@ -11,7 +11,7 @@
 
 #define CONFIG_SYS_IMMR				0x01000000
 #define CONFIG_SYS_DCSRBAR			0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
 
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-12-16 09:02 UTC #2 lore raw

PATCH 2/5 armv8/fsl_lsch2: fix DCSR_DCFG address

Quoted 2 lines · Mingkai Hu

Signed-off-by Mingkai Hu <[email protected]>
---

Applied to u-boot-fsl-qoriq master. Awaiting upstream.

York

Mingkai Hu

author

2015-12-07 08:58 UTC #3 lore raw

PATCH 3/5 armv8/ls1043a: Implement workaround for PEX erratum A009929

In reply to Mingkai Hu

Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting.

Signed-off-by Mingkai Hu <[email protected]>

---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c                | 16 ++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h      |  1 +
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  1 +
 3 files changed, 18 insertions(+)

arch/arm/cpu/armv8/fsl-layerscape/soc.c +16 -0

index 8896b70..b76e5ad 100644
@@ -121,6 +121,19 @@ void fsl_lsch3_early_init_f(void)
 }
 
 #elif defined(CONFIG_LS1043A)
+static void erratum_a009929(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
+	struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
+	u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
+
+	rstrqmr1 |= 0x00000400;
+	gur_out32(&gur->rstrqmr1, rstrqmr1);
+	writel(0x01000000, dcsr_cop_ccp);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

@@ -135,6 +148,9 @@ void fsl_lsch2_early_init_f(void)
 	 */
 	out_le32(&cci->slave[4].snoop_ctrl,
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+	/* Erratum */
+	erratum_a009929();
 }
 #endif

arch/arm/include/asm/arch-fsl-layerscape/config.h +1 -0

index b5a2d28..f744303 100644
@@ -160,6 +160,7 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 
+#define CONFIG_SYS_FSL_ERRATUM_A009929
 #else
 #error SoC not defined
 #endif

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +1 -0

index 3869177..364485e 100644
@@ -12,6 +12,7 @@
 #define CONFIG_SYS_IMMR				0x01000000
 #define CONFIG_SYS_DCSRBAR			0x20000000
 #define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CONFIG_SYS_DCSR_COP_CCP_ADDR	(CONFIG_SYS_DCSRBAR + 0x02008040)
 
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-12-16 09:03 UTC #4 lore raw

PATCH 3/5 armv8/ls1043a: Implement workaround for PEX erratum A009929

Quoted 6 lines · Mingkai Hu

Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting.
Signed-off-by Mingkai Hu <[email protected]>
---

Applied to u-boot-fsl-qoriq master. Awaiting upstream.

York

Mingkai Hu

author

2015-12-07 08:58 UTC #5 lore raw

PATCH 4/5 armv8/ls1043ardb: change core frequency to 1600MHz

In reply to Mingkai Hu

For SD boot and NAND boot.

Signed-off-by Mingkai Hu <[email protected]>

---
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 4 ++--
 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +2 -2

index 935ffc0..d87058b 100644
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0810000f 0c000000 00000000 00000000
-14550002 80004012 e0106000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
 00000000 00000000 00000000 00038800
 00000000 00001100 00000096 00000001

board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +2 -2

index 28cd958..e2ee34b 100644
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0810000f 0c000000 00000000 00000000
-14550002 80004012 60040000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
 00000000 00000000 00000000 00038800
 00000000 00001100 00000096 00000001

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-12-16 09:03 UTC #6 lore raw

PATCH 4/5 armv8/ls1043ardb: change core frequency to 1600MHz

Quoted 4 lines · Mingkai Hu

For SD boot and NAND boot.
Signed-off-by Mingkai Hu <[email protected]>
---

Slightly revised subject and commit message. Applied to u-boot-fsl-qoriq master. Awaiting upstream.

York

Mingkai Hu

author

2015-12-07 08:58 UTC #7 lore raw

PATCH 5/5 armv8/ls1043aqds: change core frequency to 1600MHz

In reply to Mingkai Hu

For SD boot and NAND boot.

Signed-off-by Mingkai Hu <[email protected]>

---
 board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg   | 4 ++--
 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +2 -2

index 935ffc0..d87058b 100644
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0810000f 0c000000 00000000 00000000
-14550002 80004012 e0106000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
 00000000 00000000 00000000 00038800
 00000000 00001100 00000096 00000001

board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +2 -2

index 17a5dd0..b6b5e0b 100644
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 # RCW
 # Enable IFC; disable QSPI
-0810000f 0c000000 00000000 00000000
-14550002 80004012 60040000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
 00000000 00000000 00000000 00038800
 00000000 00001100 00000096 00000001

Signature · 1 line

2.1.0.27.g96db324

York Sun

2015-12-16 09:04 UTC #8 lore raw

PATCH 5/5 armv8/ls1043aqds: change core frequency to 1600MHz

Quoted 4 lines · Mingkai Hu

For SD boot and NAND boot.
Signed-off-by Mingkai Hu <[email protected]>
---

Slightly revised subject and commit message. Applied to u-boot-fsl-qoriq master. Awaiting upstream.

York

York Sun

2015-12-16 09:02 UTC #9 lore raw

PATCH 1/5 armv8/ls1043a: remove print info

In reply to Mingkai Hu

Quoted 4 lines · Mingkai Hu

Signed-off-by Mingkai Hu <[email protected]>
---
 drivers/net/fm/ls1043.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

Added commit message.
Applied to u-boot-fsl-qoriq master. Awaiting upstream.

York