irqchip:support mbigen interrupt controller
Subsystems (2)
v10 cover irqchip:support mbigen interrupt controller
From: Ma Jun <[email protected]>
This patch set adds the driver of mbigen and binding document for Hisilicon Mbigen chips.
Compared with previous version, this version changed much.
Because during the time between V3 and V4 of my patch, there are two related patches were committed by Mr.Marc Zyngier and Mr. Mark Rutland.
First, Mr. Marc Zyngier changed MSI frame and added supporting for platform MSI.
https://lkml.org/lkml/2015/7/28/552
Second, Mr.Mark Rutland changed Generic PCI MSI + IOMMU topology bindings
https://lkml.org/lkml/2015/7/23/558
After V5 patch posted, Mr.Marc Zyngier posted a new patch set "Adding core support for wire-MSI bridges"
https://lkml.org/lkml/2015/10/15/545
So, mbigen patch since v6 is based on this new patch.
Changes in v10:
--- Changed some dts file accroidng to Mark's comment.
--- Fixed some wrong variable type problem.
--- Validate the input value in translate function.
Changes in v9:
--- Fixed typo problem (dts)
--- Removed superfluous data structures
--- Changed clear register offset
Changes in v8:
--- Fixed some tiny bugs.
Changes in v7:
--- Fixed the build test error when applied patch v6 3/4
Changes in v6:
--- Re-based mbigen driver on kernel 4.3.0-rc5 and Marc's new patch --- Change the mbigen chip node definition(dts).
--- Change the interrupt cells definition(dts).
Changes in v5:
--- Split mbigen driver patch into 2 smaller patches.
--- Change mbigen chip and mbigen device initialzing sequence. --- Initializing mbigen device instead of mbigen chip as interrupt controller --- Remove mbigen node from driver to make this driver more easily read. --- Change the mbigen chip node definition(dts).
--- Change the interrupt cells definition(dts).
Changes in v4:
--- Re-based mbigen driver on kernel 4.2.0-rc2 and Marc's patch --- Changed the binding document based on Mark's patch.
Ma Jun (4):
dt-binding:Documents of the mbigen bindings
irqchip: add platform device driver for mbigen device irqchip:create irq domain for each mbigen device irqchip:implement the mbigen irq chip operation functions
Documentation/devicetree/bindings/arm/mbigen.txt | 74 ++++++ drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mbigen.c | 297 ++++++++++++++++++++++ 4 files changed, 380 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt create mode 100644 drivers/irqchip/irq-mbigen.c
PATCH v10 1/4 dt-binding:Documents of the mbigen bindings
From: Ma Jun <[email protected]>
Add the mbigen msi interrupt controller bindings document.
This patch based on Mark Rutland's patch
https://lkml.org/lkml/2015/7/23/558
--- Documentation/devicetree/bindings/arm/mbigen.txt | 74 ++++++++++++++++++++++ 1 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt
Documentation/devicetree/bindings/arm/mbigen.txt new file +74 -0
@@ -0,0 +1,74 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" + +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has. + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen. + + The 2nd cell is the interrupt trigger type. + The value of this cell should be: + 1: rising edge triggered + or + 4: high level triggered + +Examples: + + mbigen_device_gmac:intc { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-msis = <9>; + #interrupt-cells = <2>; + }; + +Devices connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. + +-interrupts:Specifies the interrupt source. + For the specific information of each cell in this property,please refer to + the "interrupt-cells" description mentioned above. + +Examples: + gmac0: ethernet at c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac>; + interrupts = <656 1>, + <657 1>; + }; +
Signature · 1 line
1.7.1
Re: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
Quoted 39 lines · MaJun
From: Ma Jun <[email protected]>
Add the mbigen msi interrupt controller bindings document.
This patch based on Mark Rutland's patch
https://lkml.org/lkml/2015/7/23/558Signed-off-by Ma Jun <[email protected]>--- Documentation/devicetree/bindings/arm/mbigen.txt | 74 ++++++++++++++++++++++ 1 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txtDocumentation/devicetree/bindings/arm/mbigen.txt new file +20
-0@@ -0,0 +1,74 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and generate the +interrupt by writing ITS register. + +The mbigen chip and devices connect to mbigen have the following properties: + +Mbigen main node required properties: +------------------------------------------- +- compatible: Should be "hisilicon,mbigen-v2" +
Documentation/devicetree/bindings/arm/mbigen.txt line 30
Quoted 10 lines
Documentation/devicetree/bindings/arm/mbigen.txt new file +10
-0+- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has.
Is this the number of pins implemented? Or the number of pins that are in use?
The latter feels like something we can derive.
Documentation/devicetree/bindings/arm/mbigen.txt line 37
Quoted 6 lines
Documentation/devicetree/bindings/arm/mbigen.txt new file +6
-0+- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen.
Just to check: 0 - 63 represent the "reserved" pins, yes?
Other than those questions, this looks good to me.
Thanks,
Mark.
Quoted 41 lines
Documentation/devicetree/bindings/arm/mbigen.txt new file +37
-0+ + The 2nd cell is the interrupt trigger type. + The value of this cell should be: + 1: rising edge triggered + or + 4: high level triggered + +Examples: + + mbigen_device_gmac:intc { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-msis = <9>; + #interrupt-cells = <2>; + }; + +Devices connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. + +-interrupts:Specifies the interrupt source. + For the specific information of each cell in this property,please refer to + the "interrupt-cells" description mentioned above. + +Examples: + gmac0: ethernet at c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac>; + interrupts = <656 1>, + <657 1>; + }; +Signature · 1 line
1.7.1
Re: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
Hi Mark:
? 2015/12/17 21:52, Mark Rutland ??:
Quoted 2 lines · MaJun
Quoted 1 line
From: Ma Jun <[email protected]>
[...]
Quoted 16 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 30
Quoted 12 lines
+- compatible: Should be "hisilicon,mbigen-v2"
Documentation/devicetree/bindings/arm/mbigen.txt new file +11
-0+ +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has.Is this the number of pins implemented? Or the number of pins that are in use?
Quoted 1 line
The latter feels like something we can derive.
num-msis means the total number of pins implemented.
Quoted 9 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 37
Quoted 7 lines
+- #interrupt-cells : Specifies the number of cells needed to encode an
Documentation/devicetree/bindings/arm/mbigen.txt new file +5
-0+ interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen.Just to check: 0 - 63 represent the "reserved" pins, yes?
Yes, you are right.
Quoted 2 lines
Other than those questions, this looks good to me.
Do i need to post a new patch to update these two questions?
Thanks!
MaJun
Quoted 48 lines
Thanks,
Mark.Quoted 41 lines
Documentation/devicetree/bindings/arm/mbigen.txt new file +37
-0+ + The 2nd cell is the interrupt trigger type. + The value of this cell should be: + 1: rising edge triggered + or + 4: high level triggered + +Examples: + + mbigen_device_gmac:intc { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-msis = <9>; + #interrupt-cells = <2>; + }; + +Devices connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen device node which device connected. + +-interrupts:Specifies the interrupt source. + For the specific information of each cell in this property,please refer to + the "interrupt-cells" description mentioned above. + +Examples: + gmac0: ethernet at c2080000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xc2080000 0 0x20000>, + <0 0xc0000000 0 0x1000>; + interrupt-parent = <&mbigen_device_gmac>; + interrupts = <656 1>, + <657 1>; + }; +Signature · 1 line
1.7.1.
Mark Rutland
Acked-byRe: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
Quoted 22 lines · majun (F)
Hi Mark:
? 2015/12/17 21:52, Mark Rutland ??:
Quoted 2 lines · MaJun
Quoted 1 line
From: Ma Jun <[email protected]>
[...]
Quoted 16 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 30
Quoted 12 lines
+- compatible: Should be "hisilicon,mbigen-v2"
Documentation/devicetree/bindings/arm/mbigen.txt new file +11
-0+ +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has.Is this the number of pins implemented? Or the number of pins that are in use?
Quoted 3 lines
Quoted 1 line
The latter feels like something we can derive.
num-msis means the total number of pins implemented.
Ok. In that case I think it should be:
- num-pins: the total number of pins implemented in this Mbigen instance.
(with the appropriate fixups in the driver).
With that:
Quoted 7 lines
Quoted 7 lines
Quoted 6 lines
+- #interrupt-cells : Specifies the number of cells needed to encode an
Documentation/devicetree/bindings/arm/mbigen.txt new file +5
-0+ interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen.
Quoted 8 lines
Quoted 1 line
Just to check: 0 - 63 represent the "reserved" pins, yes?
Yes, you are right.
Quoted 2 lines
Other than those questions, this looks good to me.
Do i need to post a new patch to update these two questions?
Hopefully not.
Marc, are you happy to fold in the s/num-msis/num-pins/ change?
Thanks,
Mark.
Re: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
Quoted 50 lines · Mark Rutland
Quoted 22 lines · majun (F)
Hi Mark:
? 2015/12/17 21:52, Mark Rutland ??:
Quoted 2 lines · MaJun
Quoted 1 line
From: Ma Jun <[email protected]>
[...]
Quoted 16 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 30
Quoted 12 lines
+- compatible: Should be "hisilicon,mbigen-v2"
Documentation/devicetree/bindings/arm/mbigen.txt new file +11
-0+ +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has.Is this the number of pins implemented? Or the number of pins that are in use?
Quoted 3 lines
Quoted 1 line
The latter feels like something we can derive.
num-msis means the total number of pins implemented.
Ok. In that case I think it should be:
- num-pins: the total number of pins implemented in this Mbigen instance.
(with the appropriate fixups in the driver).
With that:
Acked-by Mark Rutland <[email protected]>Quoted 12 lines
Quoted 8 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 37
Quoted 6 lines
+- #interrupt-cells : Specifies the number of cells needed to encode an
Documentation/devicetree/bindings/arm/mbigen.txt new file +5
-0+ interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen.Just to check: 0 - 63 represent the "reserved" pins, yes?
Yes, you are right.
Quoted 1 line
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Other than those questions, this looks good to me.
Do i need to post a new patch to update these two questions?
Hopefully not.
Marc, are you happy to fold in the s/num-msis/num-pins/ change?
Sure, I'll update the whole thing while merging it.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Re: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
In reply to Mark RutlandQuoted 50 lines · Mark Rutland
Quoted 22 lines · majun (F)
Hi Mark:
? 2015/12/17 21:52, Mark Rutland ??:
Quoted 2 lines · MaJun
Quoted 1 line
From: Ma Jun <[email protected]>
[...]
Quoted 16 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 30
Quoted 12 lines
+- compatible: Should be "hisilicon,mbigen-v2"
Documentation/devicetree/bindings/arm/mbigen.txt new file +11
-0+ +- reg: Specifies the base physical address and size of the Mbigen + registers. + +- interrupt controller: Identifies the node as an interrupt controller + +- msi-parent: Specifies the MSI controller this mbigen use. + For more detail information,please refer to the generic msi-parent binding in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +- num-msis:Specifies the total number of interrupt this device has.Is this the number of pins implemented? Or the number of pins that are in use?
Quoted 3 lines
Quoted 1 line
The latter feels like something we can derive.
num-msis means the total number of pins implemented.
Ok. In that case I think it should be:
- num-pins: the total number of pins implemented in this Mbigen instance.
(with the appropriate fixups in the driver).
With that:
Acked-by Mark Rutland <[email protected]>Quoted 12 lines
Quoted 8 lines
Documentation/devicetree/bindings/arm/mbigen.txt line 37
Quoted 6 lines
+- #interrupt-cells : Specifies the number of cells needed to encode an
Documentation/devicetree/bindings/arm/mbigen.txt new file +5
-0+ interrupt source. The value must be 2. + + The 1st cell is hardware pin number of the interrupt.This number is local to + each mbigen chip and in the range from 0 to the maximum interrupts number + of the mbigen.Just to check: 0 - 63 represent the "reserved" pins, yes?
Yes, you are right.
Quoted 1 line
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Other than those questions, this looks good to me.
Do i need to post a new patch to update these two questions?
Hopefully not.
Marc, are you happy to fold in the s/num-msis/num-pins/ change?
FWIW, I'm also moving this to:
Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
in order to match the new documentation conventions.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Re: [PATCH v10 1/4] dt-binding:Documents of the mbigen bindings
Quoted 8 lines · Marc Zyngier
Quoted 1 line · Mark Rutland
Marc, are you happy to fold in the s/num-msis/num-pins/ change?
FWIW, I'm also moving this to:
Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txtin order to match the new documentation conventions.
Even better! My ack stil stands.
Mark.
PATCH v10 2/4 irqchip: add platform device driver for mbigen device
In reply to MaJunFrom: Ma Jun <[email protected]>
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt. Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------| mgn_node0 mgn_node1 mgn_node2 | |-------| |-------|------| dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends on the interrupt lines number of devices, a device can connects to one more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects the interrupts and generates the MBI interrupts by writing the ITS Translator register.
To simplify mbigen driver,I used a new conception--mbigen device. Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3--- drivers/irqchip/Kconfig | 8 ++++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mbigen.c | 78 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 drivers/irqchip/irq-mbigen.c
drivers/irqchip/Kconfig +8 -0
@@ -27,6 +27,14 @@ config ARM_GIC_V3_ITS bool select PCI_MSI_IRQ_DOMAIN +config HISILICON_IRQ_MBIGEN + bool "Support mbigen interrupt controller" + default n + depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN + help + Enable the mbigen interrupt controller used on + Hisilicon platform. + config ARM_NVIC bool select IRQ_DOMAIN
drivers/irqchip/Makefile +1 -0
@@ -24,6 +24,7 @@ obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o +obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
drivers/irqchip/irq-mbigen.c new file +78 -0
78 lines not on this page · raw message
Signature · 1 line
1.7.1
PATCH v10 3/4 irqchip:create irq domain for each mbigen device
In reply to MaJunFrom: Ma Jun <[email protected]>
For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure.
--- drivers/irqchip/irq-mbigen.c | 138 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 138 insertions(+), 0 deletions(-)
drivers/irqchip/irq-mbigen.c +138 -0
@@ -16,13 +16,39 @@* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#include <linux/interrupt.h> +#include <linux/irqchip.h> #include <linux/module.h> +#include <linux/msi.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/slab.h> +/* Interrupt numbers per mbigen node supported */ +#define IRQS_PER_MBIGEN_NODE 128 + +/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ +#define RESERVED_IRQ_PER_MBIGEN_CHIP 64 + +/* The maximum IRQ pin number of mbigen chip(start from 0) */ +#define MAXIMUM_IRQ_PIN_NUM 1407 + +/** +* In mbigen vector register +* bit[21:12]: event id value +* bit[11:0]: device id +*/ +#define IRQ_EVENT_ID_SHIFT 12 +#define IRQ_EVENT_ID_MASK 0x3ff + +/* register range of each mbigen node */ +#define MBIGEN_NODE_OFFSET 0x1000 + +/* offset of vector register in mbigen node */ +#define REG_MBIGEN_VEC_OFFSET 0x200 +/** * struct mbigen_device - holds the information of mbigen device. *
@@ -34,10 +60,107 @@ struct mbigen_device {void __iomem *base; }; +static inline unsigned int get_mbigen_vec_reg (irq_hw_number_t hwirq) +{ +unsigned int nid, pin; + + hwirq -=RESERVED_IRQ_PER_MBIGEN_CHIP ; + nid = hwirq /IRQS_PER_MBIGEN_NODE +1 ; + pin = hwirq %IRQS_PER_MBIGEN_NODE ; + +return pin *4 + nid *MBIGEN_NODE_OFFSET + +REG_MBIGEN_VEC_OFFSET ; +} + +static struct irq_chip mbigen_irq_chip = { + .name ="mbigen-v2" , +}; + +static void mbigen_write_msg (struct msi_desc *desc,struct msi_msg *msg) +{ +struct irq_data *d =irq_get_irq_data (desc->irq); +void __iomem *base = d->chip_data; +u32 val; + + base +=get_mbigen_vec_reg (d->hwirq); + val =readl_relaxed (base); + + val &= ~(IRQ_EVENT_ID_MASK <<IRQ_EVENT_ID_SHIFT ); + val |= (msg->data <<IRQ_EVENT_ID_SHIFT ); + +/* The address of doorbell is encoded in mbigen register by default +* So,we don't need to program the doorbell address@here +*/ +writel_relaxed (val, base); +} + +static int mbigen_domain_translate (struct irq_domain *d, +struct irq_fwspec *fwspec, +unsigned long *hwirq, +unsigned int *type) +{ +if (is_of_node (fwspec->fwnode)) { +if (fwspec->param_count !=2 ) +return -EINVAL ; + +if ((fwspec->param[0 ] >MAXIMUM_IRQ_PIN_NUM ) || + (fwspec->param[0 ] <RESERVED_IRQ_PER_MBIGEN_CHIP )) +return -EINVAL ; +else + *hwirq = fwspec->param[0 ]; + +/* If there is no valid irq type, just use the default type */ +if ((fwspec->param[1 ] ==IRQ_TYPE_EDGE_RISING ) || + (fwspec->param[1 ] ==IRQ_TYPE_LEVEL_HIGH )) + *type = fwspec->param[1 ]; +else + *type =IRQ_TYPE_NONE ; + +return 0 ; + } +return -EINVAL ; +} + +static int mbigen_irq_domain_alloc (struct irq_domain *domain, +unsigned int virq, +unsigned int nr_irqs, +void *args) +{ +struct irq_fwspec *fwspec = args; +irq_hw_number_t hwirq; +unsigned int type; +struct mbigen_device *mgn_chip; +int i, err; + + err =mbigen_domain_translate (domain, fwspec, &hwirq, &type); +if (err) +return err; + + err =platform_msi_domain_alloc (domain, virq, nr_irqs); +if (err) +return err; + + mgn_chip =platform_msi_get_host_data (domain); + +for (i =0 ; i < nr_irqs; i++) +irq_domain_set_hwirq_and_chip (domain, virq + i, hwirq + i, + &mbigen_irq_chip, mgn_chip->base); + +return 0 ; +} + +static struct irq_domain_ops mbigen_domain_ops = { + .translate = mbigen_domain_translate, + .alloc = mbigen_irq_domain_alloc, + .free = irq_domain_free_irqs_common, +}; +static int mbigen_device_probe (struct platform_device *pdev) {struct mbigen_device *mgn_chip;struct resource *res; +struct irq_domain *domain; +u32 num_msis; mgn_chip =devm_kzalloc (&pdev->dev,sizeof (*mgn_chip),GFP_KERNEL );if (!mgn_chip)
@@ -50,8 +173,23 @@ static int mbigen_device_probe(struct platform_device *pdev)if (IS_ERR (mgn_chip->base))return PTR_ERR (mgn_chip->base); +if (of_property_read_u32 (pdev->dev.of_node,"num-msis" , &num_msis) <0 ) { +dev_err (&pdev->dev,"No num-msis property\n" ); +return -EINVAL ; + } + + domain =platform_msi_create_device_domain (&pdev->dev, num_msis, + mbigen_write_msg, + &mbigen_domain_ops, + mgn_chip); + +if (!domain) +return -ENOMEM ; +platform_set_drvdata (pdev, mgn_chip); +dev_info (&pdev->dev,"Probing ok, allocated %d MSIs\n" , num_msis); +return 0 ; }
Signature · 1 line
1.7.1
Re: [PATCH v10 3/4] irqchip:create irq domain for each mbigen device
Quoted 7 lines · MaJun
From: Ma Jun <[email protected]>
For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure.
Signed-off-by Ma Jun <[email protected]>
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Re: [PATCH v10 3/4] irqchip:create irq domain for each mbigen device
In reply to MaJunQuoted 10 lines · MaJun
From: Ma Jun <[email protected]>
For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure.
Signed-off-by Ma Jun <[email protected]>--- drivers/irqchip/irq-mbigen.c | 138 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 138 insertions(+), 0 deletions(-)
[...]
Quoted 11 lines
drivers/irqchip/irq-mbigen.c +11
-0+static int mbigen_domain_translate (struct irq_domain *d, +struct irq_fwspec *fwspec, +unsigned long *hwirq, +unsigned int *type) +{ +if (is_of_node (fwspec->fwnode)) { +if (fwspec->param_count !=2 ) +return -EINVAL ; + +if ((fwspec->param[0 ] >MAXIMUM_IRQ_PIN_NUM ) || + (fwspec->param[0 ] <RESERVED_IRQ_PER_MBIGEN_CHIP ))
drivers/irqchip/irq-mbigen.c struct mbigen_device { · line 117
Quoted 10 lines
drivers/irqchip/irq-mbigen.c +10
-0+return -EINVAL ; + else + *hwirq = fwspec->param[0 ]; + +/* If there is no valid irq type, just use the default type */ +if ((fwspec->param[1 ] ==IRQ_TYPE_EDGE_RISING ) || + (fwspec->param[1 ] ==IRQ_TYPE_LEVEL_HIGH )) + *type = fwspec->param[1 ]; +else + *type =IRQ_TYPE_NONE ;
That does not seem like a good idea. The binding requires one of two types, and the DT is clearly wrong in the else case.
I think for the else case we should return -EINVAL.
Thanks,
Mark.
Re: [PATCH v10 3/4] irqchip:create irq domain for each mbigen device
Quoted 39 lines · Mark Rutland
Quoted 10 lines · MaJun
From: Ma Jun <[email protected]>
For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure.
Signed-off-by Ma Jun <[email protected]>--- drivers/irqchip/irq-mbigen.c | 138 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 138 insertions(+), 0 deletions(-)[...]
Quoted 11 lines
drivers/irqchip/irq-mbigen.c +11
-0+static int mbigen_domain_translate (struct irq_domain *d, +struct irq_fwspec *fwspec, +unsigned long *hwirq, +unsigned int *type) +{ +if (is_of_node (fwspec->fwnode)) { +if (fwspec->param_count !=2 ) +return -EINVAL ; + +if ((fwspec->param[0 ] >MAXIMUM_IRQ_PIN_NUM ) || + (fwspec->param[0 ] <RESERVED_IRQ_PER_MBIGEN_CHIP ))drivers/irqchip/irq-mbigen.c struct mbigen_device { · line 117
Quoted 10 lines
drivers/irqchip/irq-mbigen.c +10
-0+return -EINVAL ; + else + *hwirq = fwspec->param[0 ]; + +/* If there is no valid irq type, just use the default type */ +if ((fwspec->param[1 ] ==IRQ_TYPE_EDGE_RISING ) || + (fwspec->param[1 ] ==IRQ_TYPE_LEVEL_HIGH )) + *type = fwspec->param[1 ]; +else + *type =IRQ_TYPE_NONE ;That does not seem like a good idea. The binding requires one of two types, and the DT is clearly wrong in the else case.
Quoted 1 line
I think for the else case we should return
-EINVAL.
Ah, nicely spotted. I'll fix that in my tree too.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v10 4/4 irqchip:implement the mbigen irq chip operation functions
In reply to MaJunFrom: Ma Jun <[email protected]>
Add the interrupt controller chip operation functions of mbigen chip.
--- drivers/irqchip/irq-mbigen.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 81 insertions(+), 0 deletions(-)
drivers/irqchip/irq-mbigen.c +81 -0
@@ -50,6 +50,20 @@#define REG_MBIGEN_VEC_OFFSET 0x200/** +* offset of clear register in mbigen node +* This register is used to clear the status +* of interrupt +*/ +#define REG_MBIGEN_CLEAR_OFFSET 0xa000 + +/** +* offset of interrupt type register +* This register is used to configure interrupt +* trigger type +*/ +#define REG_MBIGEN_TYPE_OFFSET 0x0 + +/** * struct mbigen_device - holds the information of mbigen device. * * @pdev: pointer to the platform device structure of mbigen chip.
@@ -72,8 +86,75 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) +REG_MBIGEN_VEC_OFFSET ; } +static inline void get_mbigen_type_reg (irq_hw_number_t hwirq, +u32 *mask,u32 *addr) +{ +unsigned int nid, irq_ofst, ofst; + + hwirq -=RESERVED_IRQ_PER_MBIGEN_CHIP ; + nid = hwirq /IRQS_PER_MBIGEN_NODE +1 ; + irq_ofst = hwirq %IRQS_PER_MBIGEN_NODE ; + + *mask =1 << (irq_ofst %32 ); + ofst = irq_ofst /32 *4 ; + + *addr = ofst + nid *MBIGEN_NODE_OFFSET + +REG_MBIGEN_TYPE_OFFSET ; +} + +static inline void get_mbigen_clear_reg (irq_hw_number_t hwirq, +u32 *mask,u32 *addr) +{ +unsigned int ofst; + + hwirq -=RESERVED_IRQ_PER_MBIGEN_CHIP ; + ofst = hwirq /32 *4 ; + + *mask =1 << (hwirq %32 ); + *addr = ofst +REG_MBIGEN_CLEAR_OFFSET ; +} + +static void mbigen_eoi_irq (struct irq_data *data) +{ +void __iomem *base = data->chip_data; +u32 mask, addr; + +get_mbigen_clear_reg (data->hwirq, &mask, &addr); + +writel_relaxed (mask, base + addr); + +irq_chip_eoi_parent (data); +} + +static int mbigen_set_type (struct irq_data *data,unsigned int type) +{ +void __iomem *base = data->chip_data; +u32 mask, addr, val; + +if (type !=IRQ_TYPE_LEVEL_HIGH && type !=IRQ_TYPE_EDGE_RISING ) +return -EINVAL ; + +get_mbigen_type_reg (data->hwirq, &mask, &addr); + + val =readl_relaxed (base + addr); + +if (type ==IRQ_TYPE_LEVEL_HIGH ) + val |= mask; +else + val &= ~mask; + +writel_relaxed (val, base + addr); + +return 0 ; +} +static struct irq_chip mbigen_irq_chip = { .name ="mbigen-v2" , + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = mbigen_eoi_irq, + .irq_set_type = mbigen_set_type, + .irq_set_affinity = irq_chip_set_affinity_parent, };static void mbigen_write_msg (struct msi_desc *desc,struct msi_msg *msg)
Signature · 1 line
1.7.1
Re: [PATCH v10 4/4] irqchip:implement the mbigen irq chip operation functions
Quoted 5 lines · MaJun
From: Ma Jun <[email protected]>
Add the interrupt controller chip operation functions of mbigen chip.
Signed-off-by Ma Jun <[email protected]>
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Quoted 4 lines · MaJun
From: Ma Jun <[email protected]>
This patch set adds the driver of mbigen and binding document for Hisilicon Mbigen chips.
[...[
Right, we're almost there. Assuming you quickly deal with the couple of remarks Mark had, I'll apply this on top of my irq/wire-msi-bridge branch for Thomas to merge it into 4.5.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Quoted 4 lines · MaJun
From: Ma Jun <[email protected]>
This patch set adds the driver of mbigen and binding document for Hisilicon Mbigen chips.
[...]
I've reworked the nits noticed by Mark and stashed this in my irq/wire-msi-bridge branch.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Hi Marc, Mark,
Quoted 9 lines · Marc Zyngier
Quoted 4 lines · MaJun
From: Ma Jun <[email protected]>
This patch set adds the driver of mbigen and binding document for Hisilicon Mbigen chips.
[...]
I've reworked the nits noticed by Mark and stashed this in my irq/wire-msi-bridge branch.
I'm also following this patch set and I checked your tree in irq/wire-msi-bridge branch, especially with the "num-pins" property/driver update, I think the code in your tree is in good shape, thanks a lot for the review!
Thanks
Hanjun
Hi Marc and Mark:
Quoted 11 lines · Marc Zyngier
Quoted 4 lines · MaJun
From: Ma Jun <[email protected]>
This patch set adds the driver of mbigen and binding document for Hisilicon Mbigen chips.
[...]
I've reworked the nits noticed by Mark and stashed this in my irq/wire-msi-bridge branch.
Thanks for your reviewing and great help.
Thanks again!
MaJun