board: Add Microchip PIC32MZ[DA] Starter Kit board.
PATCH 7/18 board: Add Microchip PIC32MZ[DA] Starter Kit board.
This adds support for Microchip PIC32MZ[DA] Starter Kit board based on a PIC32MZ[DA] family of microcontrollers.
Signed-off-by Purna Chandra Mandal <[email protected]>
---
arch/mips/dts/Makefile | 2 +- arch/mips/dts/pic32mzda_sk.dts | 38 ++++ arch/mips/mach-pic32/Kconfig | 7 + board/microchip/pic32mzda/Kconfig | 13 ++ board/microchip/pic32mzda/MAINTAINERS | 6 + board/microchip/pic32mzda/Makefile | 7 + board/microchip/pic32mzda/README | 22 ++ board/microchip/pic32mzda/config.mk | 4 + board/microchip/pic32mzda/ddr.c | 389 ++++++++++++++++++++++++++++++++++ board/microchip/pic32mzda/ddr.h | 46 ++++ board/microchip/pic32mzda/pic32mzda.c | 41 ++++ configs/pic32mzdask_defconfig | 22 ++ include/configs/pic32mzdask.h | 110 ++++++++++ 13 files changed, 706 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/pic32mzda_sk.dts create mode 100644 board/microchip/pic32mzda/Kconfig create mode 100644 board/microchip/pic32mzda/MAINTAINERS create mode 100644 board/microchip/pic32mzda/Makefile create mode 100644 board/microchip/pic32mzda/README create mode 100644 board/microchip/pic32mzda/config.mk create mode 100644 board/microchip/pic32mzda/ddr.c create mode 100644 board/microchip/pic32mzda/ddr.h create mode 100644 board/microchip/pic32mzda/pic32mzda.c create mode 100644 configs/pic32mzdask_defconfig create mode 100644 include/configs/pic32mzdask.h
arch/mips/dts/Makefile +1 -1
@@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#dtb-$(CONFIG_XXX) += xxx.dtb +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y)
arch/mips/dts/pic32mzda_sk.dts new file +38 -0
@@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal at microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "pic32mzda.dtsi" + +/ { + model = "Microchip PIC32MZDASK"; + compatible = "microchip,pic32mzdask", "microchip,pic32mzda"; + + aliases { + console = &uart2; + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clock { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +};
arch/mips/mach-pic32/Kconfig +7 -0
@@ -24,6 +24,12 @@ endchoice choice prompt "Board select" +config TARGET_PIC32MZDASK + bool "Microchip PIC32MZ[DA] Starter Kit" + depends on SOC_PIC32MZDA + help + This supports Microchip PIC32MZ[DA] Starter Kit. + endchoice config PIC32_SUPPORTS_FDT_BOOT
@@ -31,4 +37,5 @@ config PIC32_SUPPORTS_FDT_BOOT select MIPS_BOOT_FDT select MIPS_BOOT_CMDLINE_LEGACY +source "board/microchip/pic32mzda/Kconfig" endmenu
board/microchip/pic32mzda/Kconfig new file +13 -0
@@ -0,0 +1,13 @@ + +if TARGET_PIC32MZDASK + +config SYS_BOARD + default "pic32mzda" + +config SYS_VENDOR + default "microchip" + +config SYS_CONFIG_NAME + default "pic32mzdask" + +endif
board/microchip/pic32mzda/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +PIC32MZDASK BOARD +M: Purna Chandra Mandal <[email protected]> +S: Maintained +F: board/microchip/pic32mzda/ +F: include/configs/pic32mzdask.h +F: configs/pic32mzdask_defconfig
board/microchip/pic32mzda/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal at microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := pic32mzda.o ddr.o
board/microchip/pic32mzda/README new file +22 -0
@@ -0,0 +1,22 @@ +/* + * (c) 2015 Purna Chandra Mandal <[email protected]> + */ + +PIC32MZ[DA] Starter-Kit +---------------------------------------- +PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller. +This family is powered by MIPS M14KEC 32bit general purpose core with advanced +microcontroller features and peripherals. + +This processor boots with proprietary stage1 bootloader running from on-chip +boot-flash. Stage1 bootloader locates and jumps to U-Boot programmed on +another onchip program flash. Finally U-Boot locates and loads OS image +(along with other required files for booting) from either uSD card, or +ethernet, or from USB storage connected on-chip USB controller. + +To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot +environment file), uImage, *.dtb (platform device-tree-blob file). + +U-Boot jumps to Linux using UHI specification. + +Visit http://microchip.com for details.
board/microchip/pic32mzda/config.mk new file +4 -0
@@ -0,0 +1,4 @@ +# +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU) +# +CONFIG_SYS_TEXT_BASE = 0x9d004000
board/microchip/pic32mzda/ddr.c new file +389 -0
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board/microchip/pic32mzda/ddr.h new file +46 -0
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board/microchip/pic32mzda/pic32mzda.c new file +41 -0
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configs/pic32mzdask_defconfig new file +22 -0
@@ -0,0 +1,22 @@ +CONFIG_MIPS=y +CONFIG_MACH_PIC32=y +CONFIG_SOC_PIC32MZDA=y +CONFIG_TARGET_PIC32MZDASK=y +CONFIG_PIC32_SUPPORTS_FDT_BOOT=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_HUSH_PARSER=y +CONFIG_SYS_PROMPT="dask # " +CONFIG_CMD_TIME=y +# CONFIG_CMD_IMLS is not set +CONFIG_SUPPORT_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_DM_SERIAL=y +CONFIG_PIC32_SERIAL=y +CONFIG_CLK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_PIC32_PINCTRL=y
include/configs/pic32mzdask.h new file +110 -0
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Signature · 1 line
1.8.3.1
PATCH 7/18 board: Add Microchip PIC32MZ[DA] Starter Kit board.
On Thursday, December 17, 2015 at 06:30:38 PM, Purna Chandra Mandal wrote:
[...]
Quoted 78 lines
(quoted diff) +0
-0
b/board/microchip/pic32mzda/config.mknew file mode 100644 index 0000000..a12e712board/microchip/pic32mzda/config.mk new file +4
-0@@ -0,0 +1,4 @@ +# +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU) +# +CONFIG_SYS_TEXT_BASE = 0x9d004000(quoted diff) +0
-0
b/board/microchip/pic32mzda/ddr.cnew file mode 100644 index 0000000..31a44faboard/microchip/pic32mzda/ddr.c new file +59
-0@@ -0,0 +1,389 @@ +/* +* (c) 2015 Paul Thacker <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +* +*/ + +#include <asm/io.h> +#include <stdint.h> +#include <config.h> +#include <linux/kernel.h> +#include <asm/mipsregs.h> +#include <asm/arch-pic32/pic32.h> + +#include "ddr.h" + +/* macros */ +#define hc_clk_dly (dly) \ + (max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2) + +/* Host Commands */ +#define IDLE_NOP 0x00FFFFFF +#define PRECH_ALL_CMD 0x00FFF401 +#define REF_CMD 0x00FFF801 +#define LOAD_MODE_CMD 0x00FFF001 +#define CKE_LOW 0x00FFEFFE + +#define NUM_HOST_CMDS 12 + +/* DDR address decoding */ +#define COL_HI_RSHFT 0 +#define COL_HI_MASK 0 +#define COL_LO_MASK ((1 << COL_BITS) - 1) + +#define BA_RSHFT COL_BITS +#define BANK_ADDR_MASK ((1 << BA_BITS) - 1) + +#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) +#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) + +#define CS_ADDR_RSHIFT 0 +#define CS_ADDR_MASK 0 + +/* MPLL freq is 400MHz */ +#define CLK_PERIOD 2500/* 2500 psec */ +#define CTRL_CLK_PERIOD (CLK_PERIOD * 2) + +/* Arbiter */ +#define NUM_AGENTS 5 +#define MIN_LIM_WIDTH 5 +#define RQST_PERIOD_WIDTH 8 +#define MIN_CMDACPT_WIDTH 8 + +#define EN_AUTO_PRECH 0 +#define SB_PRI 1 +#define BIG_ENDIAN 0 +#define HALF_RATE_MODE 1 + +/************************************************************************* ****/ +/* DDR definitions */ +/************************************************************************* ****/ +
board/microchip/pic32mzda/ddr.c line 67
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board/microchip/pic32mzda/ddr.c new file +5
-0+/* DDR Address Mapping: CS, ROW, BA, COL */ +#define COL_BITS 10 +#define ROW_BITS 13 +#define BA_BITS 3 +#define CS_BITS 1
OK, so how many copies of this code will we have by the end of the day ? One for each board ? That ain't gonna work ...
Quoted 7 lines
board/microchip/pic32mzda/ddr.c new file +7
-0+/* DDR constants */ +#define BL 2/* Burst length in cycles */ + +/* default CAS latency for all speed grades */ +#define RL 5 + +/* default write latency for all speed grades = CL-1 */
board/microchip/pic32mzda/ddr.c line 85
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board/microchip/pic32mzda/ddr.c new file +10
-0+#define WL 4 + +#define MAX_BURST 3 + +/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */ +#define tRFC_MIN 127500/* psec */ +#define tWR 15000/* psec */ +#define tRP 12500/* psec */ +#define tRCD 12500/* psec */ +#define tRRD 7500/* psec */
This is board specific, but the code is not I believe. So the common code should go into drivers/ddr/
Quoted 3 lines
board/microchip/pic32mzda/ddr.c new file +3
-0+/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */ +#define tRRD_TCK 2 +#define tWTR 7500/* psec */
[...]
board/microchip/pic32mzda/ddr.c line 297
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board/microchip/pic32mzda/ddr.c new file +8
-0+/* ODT Config */ +writel (0x00000000 ,DDR2ODTCFG ); +writel (0x00010000 ,DDR2ODTENCFG );/* WREN on CS */ + +writel (((RL -3 ) <<8 ) | ((WL -3 ) <<12 ) | (2 <<16 ) | (3 <<20 ), +DDR2ODTCFG ); + +/* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY */ + writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4 << 4) |
board/microchip/pic32mzda/ddr.c new file +3
-0+ (/*(RL - 1)*/ 2 <<16 ) | + (MAX_BURST <<24 ) | (7 <<28 ) | (BIG_ENDIAN <<31 ), + DDR2XFERCFG);
Fixme please ;-)
Quoted 15 lines
board/microchip/pic32mzda/ddr.c new file +15
-0+/* DRAM Initialization */ +/* bring CKE high after reset and wait 400 nsec */ +writel (IDLE_NOP ,DDR2CMD10 ); +writel ((0x00 | (0x00 <<8 ) | (hc_clk_dly (400000 ) <<11 )), +DDR2CMD20 ); + +/* issue precharge all command */ +writel (PRECH_ALL_CMD ,DDR2CMD10 +0x04 ); +writel ((0x04 | (0x00 <<8 ) | (hc_clk_dly (tRP +CLK_PERIOD ) <<11 )), +DDR2CMD20 +0x04 ); + +/* initialize EMR2 */ +writel (LOAD_MODE_CMD ,DDR2CMD10 +0x08 ); +writel ((0x00 | (0x02 <<8 ) | (hc_clk_dly (tMRD *CLK_PERIOD ) <<11 )), +DDR2CMD20 +0x08 );
[...]
board/microchip/pic32mzda/ddr.c line 379
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board/microchip/pic32mzda/ddr.c new file +5
-0+writel (0x1B ,DDR2CMDISSUE ); +writel (0x01 ,DDR2MEMCON ); + +while (readl (DDR2CMDISSUE ) &0x10 ) + ;
Use the wait_for_bit() function here and for the other unbounded while loop below. This will add timeout to the wait, so your code will not get stuck in an endless loop.
Quoted 17 lines
board/microchip/pic32mzda/ddr.c new file +9
-0+writel (0x03 ,DDR2MEMCON ); + +/* SCL Start */ +writel (SCL_START |SCL_EN ,DDR2SCLSTART ); + +/* Wait for SCL byte to pass */ +while ((readl (DDR2SCLSTART ) &SCL_LUBPASS ) !=SCL_LUBPASS ) + ; +}(quoted diff) +0
-0
b/board/microchip/pic32mzda/ddr.hnew file mode 100644 index 0000000..7828169board/microchip/pic32mzda/ddr.h new file +2
-0@@ -0,0 +1,46 @@ +/* +* (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com>
board/microchip/pic32mzda/ddr.h line 12
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board/microchip/pic32mzda/ddr.h new file +10
-0+* +* SPDX-License-Identifier: GPL-2.0+ +* +*/ + +#ifndef __PIC32MZDA_DDR_H +#define __PIC32MZDA_DDR_H + +#define DDR2TSEL (PIC32_DDR2C_BASE + 0x00)/* ARB_AGENT_SEL */ +#define DDR2MINLIM (PIC32_DDR2C_BASE + 0x04)/* MIN_LIMIT */
Nuke the trailing indent in the comment please.
Quoted 11 lines
board/microchip/pic32mzda/ddr.h new file +11
-0+#define DDR2REQPRD (PIC32_DDR2C_BASE + 0x08)/* RQST_PERIOD */ +#define DDR2MINCMD (PIC32_DDR2C_BASE + 0x0c)/* MIN_CMD_ACPT */ +#define DDR2MEMCON (PIC32_DDR2C_BASE + 0x10)/* MEM_START */ +#define DDR2MEMCFG0 (PIC32_DDR2C_BASE + 0x14)/* MEM_CONFIG_1 */ +#define DDR2MEMCFG1 (PIC32_DDR2C_BASE + 0x18)/* MEM_CONFIG_2 */ +#define DDR2MEMCFG2 (PIC32_DDR2C_BASE + 0x1c)/* MEM_CONFIG_3 */ +#define DDR2MEMCFG3 (PIC32_DDR2C_BASE + 0x20)/* MEM_CONFIG_4 */ +#define DDR2MEMCFG4 (PIC32_DDR2C_BASE + 0x24)/* MEM_CONFIG_5 */ +#define DDR2REFCFG (PIC32_DDR2C_BASE + 0x28)/* REF_CONFIG */ +#define DDR2PWRCFG (PIC32_DDR2C_BASE + 0x2c)/* PWR_SAVE_ECC_CONFIG */ +#define DDR2DLYCFG0 (PIC32_DDR2C_BASE + 0x30)/* DLY_CONFIG1 */
[...]
PATCH 7/18 board: Add Microchip PIC32MZ[DA] Starter Kit board.
Quoted 80 lines · Marek Vasut
On Thursday, December 17, 2015 at 06:30:38 PM, Purna Chandra Mandal wrote:
[...]Quoted 77 lines
(quoted diff) +0
-0
b/board/microchip/pic32mzda/config.mknew file mode 100644 index 0000000..a12e712board/microchip/pic32mzda/config.mk new file +4
-0@@ -0,0 +1,4 @@ +# +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU) +# +CONFIG_SYS_TEXT_BASE = 0x9d004000(quoted diff) +0
-0
b/board/microchip/pic32mzda/ddr.cnew file mode 100644 index 0000000..31a44faboard/microchip/pic32mzda/ddr.c new file +59
-0@@ -0,0 +1,389 @@ +/* +* (c) 2015 Paul Thacker <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +* +*/ + +#include <asm/io.h> +#include <stdint.h> +#include <config.h> +#include <linux/kernel.h> +#include <asm/mipsregs.h> +#include <asm/arch-pic32/pic32.h> + +#include "ddr.h" + +/* macros */ +#define hc_clk_dly (dly) \ + (max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2) + +/* Host Commands */ +#define IDLE_NOP 0x00FFFFFF +#define PRECH_ALL_CMD 0x00FFF401 +#define REF_CMD 0x00FFF801 +#define LOAD_MODE_CMD 0x00FFF001 +#define CKE_LOW 0x00FFEFFE + +#define NUM_HOST_CMDS 12 + +/* DDR address decoding */ +#define COL_HI_RSHFT 0 +#define COL_HI_MASK 0 +#define COL_LO_MASK ((1 << COL_BITS) - 1) + +#define BA_RSHFT COL_BITS +#define BANK_ADDR_MASK ((1 << BA_BITS) - 1) + +#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) +#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) + +#define CS_ADDR_RSHIFT 0 +#define CS_ADDR_MASK 0 + +/* MPLL freq is 400MHz */ +#define CLK_PERIOD 2500/* 2500 psec */ +#define CTRL_CLK_PERIOD (CLK_PERIOD * 2) + +/* Arbiter */ +#define NUM_AGENTS 5 +#define MIN_LIM_WIDTH 5 +#define RQST_PERIOD_WIDTH 8 +#define MIN_CMDACPT_WIDTH 8 + +#define EN_AUTO_PRECH 0 +#define SB_PRI 1 +#define BIG_ENDIAN 0 +#define HALF_RATE_MODE 1 + +/************************************************************************* ****/ +/* DDR definitions */ +/*************************************************************************
Quoted 8 lines
board/microchip/pic32mzda/ddr.c line 67
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****/ +
board/microchip/pic32mzda/ddr.c new file +5
-0+/* DDR Address Mapping: CS, ROW, BA, COL */ +#define COL_BITS 10 +#define ROW_BITS 13 +#define BA_BITS 3 +#define CS_BITS 1OK, so how many copies of this code will we have by the end of the day ? One for each board ? That ain't gonna work ...
Ack. Will re-organize this code into two parts - common code will go to drivers/ddr/ and board specific parameters (like arbiter parameters, DDR2 timing parameters) will be separated.
Quoted 11 lines
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board/microchip/pic32mzda/ddr.c new file +11
-0+/* DDR constants */ +#define BL 2/* Burst length in cycles */ + +/* default CAS latency for all speed grades */ +#define RL 5 + +/* default write latency for all speed grades = CL-1 */ +#define WL 4 + +#define MAX_BURST 3 +
Quoted 8 lines
board/microchip/pic32mzda/ddr.c line 85
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board/microchip/pic32mzda/ddr.c new file +6
-0+/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */ +#define tRFC_MIN 127500/* psec */ +#define tWR 15000/* psec */ +#define tRP 12500/* psec */ +#define tRCD 12500/* psec */ +#define tRRD 7500/* psec */ This is board specific, but the code is not I believe. So the common code should go into
drivers/ddr/
ack.
Quoted 5 lines
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board/microchip/pic32mzda/ddr.c new file +3
-0+/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */ +#define tRRD_TCK 2 +#define tWTR 7500/* psec */ [...]
Quoted 13 lines
board/microchip/pic32mzda/ddr.c line 297
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board/microchip/pic32mzda/ddr.c new file +8
-0+/* ODT Config */ +writel (0x00000000 ,DDR2ODTCFG ); +writel (0x00010000 ,DDR2ODTENCFG );/* WREN on CS */ + +writel (((RL -3 ) <<8 ) | ((WL -3 ) <<12 ) | (2 <<16 ) | (3 <<20 ), +DDR2ODTCFG ); + +/* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY */ + writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4 << 4) |
board/microchip/pic32mzda/ddr.c new file +3
-0+ (/*(RL - 1)*/ 2 <<16 ) | + (MAX_BURST <<24 ) | (7 <<28 ) | (BIG_ENDIAN <<31 ), + DDR2XFERCFG);Fixme please ;-)
ack.
Quoted 17 lines
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board/microchip/pic32mzda/ddr.c new file +15
-0+/* DRAM Initialization */ +/* bring CKE high after reset and wait 400 nsec */ +writel (IDLE_NOP ,DDR2CMD10 ); +writel ((0x00 | (0x00 <<8 ) | (hc_clk_dly (400000 ) <<11 )), +DDR2CMD20 ); + +/* issue precharge all command */ +writel (PRECH_ALL_CMD ,DDR2CMD10 +0x04 ); +writel ((0x04 | (0x00 <<8 ) | (hc_clk_dly (tRP +CLK_PERIOD ) <<11 )), +DDR2CMD20 +0x04 ); + +/* initialize EMR2 */ +writel (LOAD_MODE_CMD ,DDR2CMD10 +0x08 ); +writel ((0x00 | (0x02 <<8 ) | (hc_clk_dly (tMRD *CLK_PERIOD ) <<11 )), +DDR2CMD20 +0x08 );[...]
Quoted 8 lines
board/microchip/pic32mzda/ddr.c line 379
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board/microchip/pic32mzda/ddr.c new file +5
-0+writel (0x1B ,DDR2CMDISSUE ); +writel (0x01 ,DDR2MEMCON ); + +while (readl (DDR2CMDISSUE ) &0x10 ) + ;Use the
wait_for_bit()function here and for the other unbounded while loop below. This will add timeout to the wait, so your code will not get stuck in an endless loop.
ack.
Quoted 20 lines
Quoted 20 lines
board/microchip/pic32mzda/ddr.c new file +9
-0+writel (0x03 ,DDR2MEMCON ); + +/* SCL Start */ +writel (SCL_START |SCL_EN ,DDR2SCLSTART ); + +/* Wait for SCL byte to pass */ +while ((readl (DDR2SCLSTART ) &SCL_LUBPASS ) !=SCL_LUBPASS ) + ; +}(quoted diff) +0
-0
b/board/microchip/pic32mzda/ddr.hnew file mode 100644 index 0000000..7828169board/microchip/pic32mzda/ddr.h new file +5
-0@@ -0,0 +1,46 @@ +/* +* (c) 2015 Purna Chandra Mandal purna.mandal at microchip.com> +* +* SPDX-License-Identifier: GPL-2.0+ +*
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board/microchip/pic32mzda/ddr.h line 12
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board/microchip/pic32mzda/ddr.h new file +7
-0+*/ + +#ifndef __PIC32MZDA_DDR_H +#define __PIC32MZDA_DDR_H + +#define DDR2TSEL (PIC32_DDR2C_BASE + 0x00)/* ARB_AGENT_SEL */ +#define DDR2MINLIM (PIC32_DDR2C_BASE + 0x04)/* MIN_LIMIT */ Nuke the trailing indent in the comment please.
ack.
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board/microchip/pic32mzda/ddr.h new file +11
-0+#define DDR2REQPRD (PIC32_DDR2C_BASE + 0x08)/* RQST_PERIOD */ +#define DDR2MINCMD (PIC32_DDR2C_BASE + 0x0c)/* MIN_CMD_ACPT */ +#define DDR2MEMCON (PIC32_DDR2C_BASE + 0x10)/* MEM_START */ +#define DDR2MEMCFG0 (PIC32_DDR2C_BASE + 0x14)/* MEM_CONFIG_1 */ +#define DDR2MEMCFG1 (PIC32_DDR2C_BASE + 0x18)/* MEM_CONFIG_2 */ +#define DDR2MEMCFG2 (PIC32_DDR2C_BASE + 0x1c)/* MEM_CONFIG_3 */ +#define DDR2MEMCFG3 (PIC32_DDR2C_BASE + 0x20)/* MEM_CONFIG_4 */ +#define DDR2MEMCFG4 (PIC32_DDR2C_BASE + 0x24)/* MEM_CONFIG_5 */ +#define DDR2REFCFG (PIC32_DDR2C_BASE + 0x28)/* REF_CONFIG */ +#define DDR2PWRCFG (PIC32_DDR2C_BASE + 0x2c)/* PWR_SAVE_ECC_CONFIG */ +#define DDR2DLYCFG0 (PIC32_DDR2C_BASE + 0x30)/* DLY_CONFIG1 */ [...]