scsi-mq performance check
Hi,
I have started to enable scsi-mq on the HiSilicon SAS driver.
Are there hints/checks I should use to make sure it is configured correctly/optimally? In my initial testing I have seen some performance improvements, but none like what I have seen in presentations.
Cheers,
John
Quoted 9 lines · John Garry
Hi,
I have started to enable scsi-mq on the HiSilicon SAS driver.
Are there hints/checks I should use to make sure it is configured correctly/optimally? In my initial testing I have seen some performance improvements, but none like what I have seen in presentations.
The whole thing is build around having symmetric submit and receive queues, so that we can tack a send/receive queue pair to the same CPU. With that we can ensure that we don't have any cache invalidation, as the request is already in the cache for that CPU when the completion is recieved. _And_ we can get rid of most spinlocks as other CPUs cannot access our request.
So make sure to have the submit and receive queues properly done, and ensure you don't have any global resources within your driver which needs to be locked. Or move access to those resources out of the fast path.
Cheers,
Hannes
Signature · 9 lines
Dr. Hannes Reinecke zSeries & Storage [email protected] +49 911 74053 688 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton HRB 21284 (AG Nürnberg) -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
Quoted 17 lines · Hannes Reinecke
Quoted 9 lines · John Garry
Hi,
I have started to enable scsi-mq on the HiSilicon SAS driver.
Are there hints/checks I should use to make sure it is configured correctly/optimally? In my initial testing I have seen some performance improvements, but none like what I have seen in presentations.
The whole thing is build around having symmetric submit and receive queues, so that we can tack a send/receive queue pair to the same CPU. With that we can ensure that we don't have any cache invalidation, as the request is already in the cache for that CPU when the completion is recieved. _And_ we can get rid of most spinlocks as other CPUs cannot access our request.
Quoted 3 lines
So make sure to have the submit and receive queues properly done, and ensure you don't have any global resources within your driver which needs to be locked. Or move access to those resources out of the fast path.
Hello John,
It's great news that you started looking into scsi-mq support :-) As Hannes wrote, if the performance improvement is not as big as you expected this could be caused e.g. by lock contention. Are you familiar with the perf tool ? The perf tool can be a great help to verify whether lock contention occurs and also which lock(s) cause it.
Bart.
Quoted 31 lines · Bart Van Assche
Quoted 17 lines · Hannes Reinecke
Quoted 9 lines · John Garry
Hi,
I have started to enable scsi-mq on the HiSilicon SAS driver.
Are there hints/checks I should use to make sure it is configured correctly/optimally? In my initial testing I have seen some performance improvements, but none like what I have seen in presentations.
The whole thing is build around having symmetric submit and receive queues, so that we can tack a send/receive queue pair to the same CPU. With that we can ensure that we don't have any cache invalidation, as the request is already in the cache for that CPU when the completion is recieved. _And_ we can get rid of most spinlocks as other CPUs cannot access our request.
Quoted 4 lines
So make sure to have the submit and receive queues properly done, and ensure you don't have any global resources within your driver which needs to be locked. Or move access to those resources out of the fast path.
Hello John,
It's great news that you started looking into scsi-mq support :-) As Hannes wrote, if the performance improvement is not as big as you expected this could be caused e.g. by lock contention. Are you familiar with the perf tool ? The perf tool can be a great help to verify whether lock contention occurs and also which lock(s) cause it.
Quoted 6 lines
Bart.
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Thanks for the replies.
One of my main concerns is how we use a spinlock in our task exec function to prepare and deliver a frame to the hardware:hisi_sas_task_exec()
{
...
/* protect task_prep and start_delivery sequence */
spin_lock_irqsave(&hisi_hba->lock, flags);
rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass);
...
hisi_hba->hw->start_delivery(hisi_hba);
spin_unlock_irqrestore(&hisi_hba->lock, flags);
...
}We have to lock due to how we reserve a slot in the delivery queue. We are looking to optimise this, but it's not straightforward.
Perf is a good strategy, but, to be honest, I have not spent a lot of time looking at this so I'm looking for low hanging fruit initially.
FYI, our hardware does have the same number of delivery and completion queues (32), and 16 cores. One thing to note is that a command which was sent on queue x is not quaranteed to complete on queue y.
cheers,
Quoted 70 lines · John Garry
Quoted 39 lines · Bart Van Assche
Quoted 21 lines · Hannes Reinecke
Quoted 9 lines · John Garry
Hi,
I have started to enable scsi-mq on the HiSilicon SAS driver.
Are there hints/checks I should use to make sure it is configured correctly/optimally? In my initial testing I have seen some performance improvements, but none like what I have seen in presentations.
The whole thing is build around having symmetric submit and receive queues, so that we can tack a send/receive queue pair to the same CPU.
With that we can ensure that we don't have any cache invalidation, as
the request is already in the cache for that CPU when the completion is
recieved. _And_ we can get rid of most spinlocks as other CPUs cannot
access our request.Quoted 6 lines
So make sure to have the submit and receive queues properly done, and
ensure you don't have any global resources within your driver which needs to be locked. Or move access to those resources out of the fast
path.Hello John,
It's great news that you started looking into scsi-mq support :-) As Hannes wrote, if the performance improvement is not as big as you expected this could be caused e.g. by lock contention. Are you familiar
with the perf tool ? The perf tool can be a great help to verify whether
lock contention occurs and also which lock(s) cause it.Quoted 7 lines
Bart.
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To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.htmlThanks for the replies.
One of my main concerns is how we use a spinlock in our task exec function to prepare and deliver a frame to the hardware:
hisi_sas_task_exec(){ ... /* protect task_prep and start_delivery sequence */ spin_lock_irqsave(&hisi_hba->lock, flags); rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass); ... hisi_hba->hw->start_delivery(hisi_hba); spin_unlock_irqrestore(&hisi_hba->lock, flags); ... }We have to lock due to how we reserve a slot in the delivery queue. We are looking to optimise this, but it's not straightforward.
Quoted 8 lines
Perf is a good strategy, but, to be honest, I have not spent a lot of time looking at this so I'm looking for low hanging fruit initially.
FYI, our hardware does have the same number of delivery and completion queues (32), and 16 cores. One thing to note is that a command which was sent on queue x is not quaranteed to complete on queue y.
... then don't bother looking at scsi-mq. That is the very thing it relies on ...
Time to change the firmware?
Cheers,
Hannes
Signature · 9 lines
Dr. Hannes Reinecke zSeries & Storage [email protected] +49 911 74053 688 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton HRB 21284 (AG Nürnberg) -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
Quoted 12 lines
Quoted 4 lines
We have to lock due to how we reserve a slot in the delivery queue. We are looking to optimise this, but it's not straightforward.
Quoted 8 lines
Perf is a good strategy, but, to be honest, I have not spent a lot of time looking at this so I'm looking for low hanging fruit initially.
FYI, our hardware does have the same number of delivery and completion queues (32), and 16 cores. One thing to note is that a command which was sent on queue x is not quaranteed to complete on queue y.
Quoted 8 lines
... then don't bother looking at scsi-mq. That is the very thing it relies on ...
Time to change the firmware?
Cheers,
Hannes
Hi,
Even though a slot delivered on queue x is not guaranteed to complete on completion queue x, is nearly always does (I just quickly tested on our new chip, and 100% of the time it is the same - I need to check with our hardware guys if this was only v1 of the IP).
As for firmware, our controller does not have any.
cheers,