powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

PATCH New Bryan Hundven 4 participants 10 messages Dec 19, 2015 – Jul 19, 2016 1 message not in the archive

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Bryan Hundven

author

2015-12-19 04:16 UTC #0 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

As I work to re-add p1_p2_rdb, CONFIG_P2020RDB conflicts with p1_p2_rdb's CONFIG_P2020RDB.

Rename p1_p2_rdb_pc's CONFIG_P2020RDB to CONFIG_P2020RDB_PC.

Signed-off-by Bryan Hundven <[email protected]>

Cc Andy Fleming <[email protected]>

Cc York Sun <[email protected]>

---
 board/freescale/p1_p2_rdb_pc/ddr.c           | 2 +-
 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 2 +-
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 2 +-
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +-
 configs/P2020RDB-PC_36BIT_defconfig          | 2 +-
 configs/P2020RDB-PC_NAND_defconfig           | 2 +-
 configs/P2020RDB-PC_SDCARD_defconfig         | 2 +-
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 2 +-
 configs/P2020RDB-PC_defconfig                | 2 +-
 include/configs/p1_p2_rdb_pc.h               | 8 ++++----
 10 files changed, 13 insertions(+), 13 deletions(-)

board/freescale/p1_p2_rdb_pc/ddr.c +1 -1

index 946d503..ef59b58 100644
@@ -49,7 +49,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_P2020RDB_PC)
 /* Micron MT41J128M16_15E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,

configs/P2020RDB-PC_36BIT_NAND_defconfig +1 -1

index 578bfc5..c7bb971 100644
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_SDCARD_defconfig +1 -1

index 19c795a..c79399e 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +1 -1

index bdc5e43..898993f 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_defconfig +1 -1

index b9d4a47..16af720 100644
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_NAND_defconfig +1 -1

index ea9f830..19ec9d2 100644
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_SDCARD_defconfig +1 -1

index 997887d..ee0fd33 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_SPIFLASH_defconfig +1 -1

index e547ea4..40190c4 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

configs/P2020RDB-PC_defconfig +1 -1

index fdad880..6629285 100644
@@ -1,7 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y

include/configs/p1_p2_rdb_pc.h +4 -4

index 60bedaa..e64805a 100644
@@ -154,7 +154,7 @@
 #define CONFIG_SYS_L2_SIZE	(256 << 10)
 #endif
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
 #define CONFIG_BOARDNAME "P2020RDB-PCA"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P2020

@@ -323,7 +323,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
 #define CONFIG_SYS_CLK_FREQ	100000000
 #else
 #define CONFIG_SYS_CLK_FREQ	66666666

@@ -382,7 +382,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 
 /* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_P2020RDB_PC
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000

@@ -618,7 +618,7 @@
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
 #else
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)

Signature · 1 line

2.5.0

Sinan Akman

2015-12-23 18:26 UTC #2 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Hi Bryan

Quoted 172 lines · Bryan Hundven

York,

Just checking if you had seen this patch?

Cheers,

-Bryan

Quoted 163 lines · Bryan Hundven

As I work to re-add p1_p2_rdb, CONFIG_P2020RDB conflicts with p1_p2_rdb's CONFIG_P2020RDB.

Rename p1_p2_rdb_pc's CONFIG_P2020RDB to CONFIG_P2020RDB_PC.

Signed-off-by Bryan Hundven <[email protected]>

Cc Andy Fleming <[email protected]>

Cc York Sun <[email protected]>

---
  board/freescale/p1_p2_rdb_pc/ddr.c           | 2 +-
  configs/P2020RDB-PC_36BIT_NAND_defconfig     | 2 +-
  configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 2 +-
  configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +-
  configs/P2020RDB-PC_36BIT_defconfig          | 2 +-
  configs/P2020RDB-PC_NAND_defconfig           | 2 +-
  configs/P2020RDB-PC_SDCARD_defconfig         | 2 +-
  configs/P2020RDB-PC_SPIFLASH_defconfig       | 2 +-
  configs/P2020RDB-PC_defconfig                | 2 +-
  include/configs/p1_p2_rdb_pc.h               | 8 ++++----
  10 files changed, 13 insertions(+), 13 deletions(-)

board/freescale/p1_p2_rdb_pc/ddr.c +1 -1

index 946d503..ef59b58 100644
@@ -49,7 +49,7 @@ dimm_params_t ddr_raw_timing = {
         .refresh_rate_ps = 7800000,
         .tfaw_ps = 37500,
  };
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_P2020RDB_PC)
  /* Micron MT41J128M16_15E */
  dimm_params_t ddr_raw_timing = {
         .n_ranks = 1,

configs/P2020RDB-PC_36BIT_NAND_defconfig +1 -1

index 578bfc5..c7bb971 100644
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
  CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,NAND"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_SDCARD_defconfig +1 -1

index 19c795a..c79399e 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SDCARD"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +1 -1

index bdc5e43..898993f 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SPIFLASH"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_36BIT_defconfig +1 -1

index b9d4a47..16af720 100644
@@ -1,7 +1,7 @@
  CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_NAND_defconfig +1 -1

index ea9f830..19ec9d2 100644
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
  CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,NAND"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_SDCARD_defconfig +1 -1

index 997887d..ee0fd33 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SDCARD"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_SPIFLASH_defconfig +1 -1

index e547ea4..40190c4 100644
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SPIFLASH"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

configs/P2020RDB-PC_defconfig +1 -1

index fdad880..6629285 100644
@@ -1,7 +1,7 @@
  CONFIG_PPC=y
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y

include/configs/p1_p2_rdb_pc.h +2 -2

index 60bedaa..e64805a 100644
@@ -154,7 +154,7 @@
  #define CONFIG_SYS_L2_SIZE     (256 << 10)
  #endif
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_BOARDNAME "P2020RDB-PCA"
  #define CONFIG_NAND_FSL_ELBC
  #define CONFIG_P2020

@@ -323,7 +323,7 @@
  #define CONFIG_LIBATA
  #define CONFIG_LBA48
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_SYS_CLK_FREQ    100000000
  #else
  #define CONFIG_SYS_CLK_FREQ    66666666

@@ -382,7 +382,7 @@
  #define CONFIG_DIMM_SLOTS_PER_CTLR     1

Quoted 15 lines

Quoted 7 lines

include/configs/p1_p2_rdb_pc.h +1 -1

  /* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_P2020RDB_PC
  #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
  #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
  #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000

include/configs/p1_p2_rdb_pc.h line 624

Quoted 8 lines

include/configs/p1_p2_rdb_pc.h +1 -1

@@ -618,7 +618,7 @@
  #define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  #define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
  #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_SPL_RELOC_MALLOC_SIZE   (364 << 10)
  #else
  #define CONFIG_SPL_RELOC_MALLOC_SIZE   (108 << 10)

I wonder if it would better that you create a new macro
e.g. CONFIG_P2020RDB_PAB and leave the existing p1_p2_rdb_pc unmodified. I thought this way you could continue developing the support for older boards without changing anything in the current version so the potential risk would be lower.

Just my two cents ;)

Regards
Sinan Akman

Bryan Hundven

author

2015-12-23 18:39 UTC #3 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512

Sinan, List,

Quoted 211 lines · Sinan Akman

Hi Bryan
Quoted 9 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Cheers,
-Bryan
On Fri, Dec 18, 2015 at 8:16 PM, Bryan Hundven
Quoted 21 lines · <[email protected]> wrote:
Quoted 21 lines
As I work to re-add p1_p2_rdb, CONFIG_P2020RDB conflicts with p1_p2_rdb's CONFIG_P2020RDB.
Rename p1_p2_rdb_pc's CONFIG_P2020RDB to CONFIG_P2020RDB_PC.
Signed-off-by Bryan Hundven <[email protected]>
Cc Andy Fleming <[email protected]>
Cc York Sun <[email protected]>
---
  board/freescale/p1_p2_rdb_pc/ddr.c           | 2 +-
  configs/P2020RDB-PC_36BIT_NAND_defconfig     | 2 +-
  configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 2 +-
  configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +-
  configs/P2020RDB-PC_36BIT_defconfig          | 2 +-
  configs/P2020RDB-PC_NAND_defconfig           | 2 +-
  configs/P2020RDB-PC_SDCARD_defconfig         | 2 +-
  configs/P2020RDB-PC_SPIFLASH_defconfig       | 2 +-
  configs/P2020RDB-PC_defconfig                | 2 +-
  include/configs/p1_p2_rdb_pc.h               | 8 ++++----
  10 files changed, 13 insertions(+), 13 deletions(-)
Quoted 1 line
Review
Quoted 1 line
(quoted diff) +0 -0
b/board/freescale/p1_p2_rdb_pc/ddr.c
Quoted 5 lines
Quoted 5 lines
index 946d503..ef59b58 100644
board/freescale/p1_p2_rdb_pc/ddr.c +0 -0
@@ -49,7 +49,7 @@ dimm_params_t ddr_raw_timing = {
         .refresh_rate_ps = 7800000,
Quoted 8 lines
Review
Quoted 8 lines
board/freescale/p1_p2_rdb_pc/ddr.c +1 -1
         .tfaw_ps = 37500,
  };
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_P2020RDB_PC)
  /* Micron MT41J128M16_15E */
  dimm_params_t ddr_raw_timing = {
         .n_ranks = 1,
(quoted diff) +0 -0
b/configs/P2020RDB-PC_36BIT_NAND_defconfig
Quoted 5 lines
Quoted 5 lines
index 578bfc5..c7bb971 100644
configs/P2020RDB-PC_36BIT_NAND_defconfig +0 -0
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_36BIT_NAND_defconfig +1 -1
  CONFIG_SPL=y
  CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,NAND"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
Quoted 5 lines
Quoted 5 lines
index 19c795a..c79399e 100644
configs/P2020RDB-PC_36BIT_SDCARD_defconfig +0 -0
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_36BIT_SDCARD_defconfig +1 -1
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SDCARD"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
Quoted 5 lines
Quoted 5 lines
index bdc5e43..898993f 100644
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +0 -0
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +1 -1
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SPIFLASH"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_36BIT_defconfig
Quoted 5 lines
Quoted 5 lines
index b9d4a47..16af720 100644
configs/P2020RDB-PC_36BIT_defconfig +0 -0
@@ -1,7 +1,7 @@
  CONFIG_PPC=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_36BIT_defconfig +1 -1
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_NAND_defconfig
Quoted 5 lines
Quoted 5 lines
index ea9f830..19ec9d2 100644
configs/P2020RDB-PC_NAND_defconfig +0 -0
@@ -3,7 +3,7 @@ CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_NAND_defconfig +1 -1
  CONFIG_SPL=y
  CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,NAND"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_SDCARD_defconfig
Quoted 5 lines
Quoted 5 lines
index 997887d..ee0fd33 100644
configs/P2020RDB-PC_SDCARD_defconfig +0 -0
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_SDCARD_defconfig +1 -1
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SDCARD"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_SPIFLASH_defconfig
Quoted 5 lines
Quoted 5 lines
index e547ea4..40190c4 100644
configs/P2020RDB-PC_SPIFLASH_defconfig +0 -0
@@ -2,7 +2,7 @@ CONFIG_PPC=y
  CONFIG_MPC85xx=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_SPIFLASH_defconfig +1 -1
  CONFIG_TARGET_P1_P2_RDB_PC=y
  CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SPIFLASH"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/configs/P2020RDB-PC_defconfig
Quoted 5 lines
Quoted 5 lines
index fdad880..6629285 100644
configs/P2020RDB-PC_defconfig +0 -0
@@ -1,7 +1,7 @@
  CONFIG_PPC=y
Quoted 8 lines
Review
Quoted 8 lines
configs/P2020RDB-PC_defconfig +1 -1
  CONFIG_MPC85xx=y
  CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC"
  CONFIG_SPI_FLASH=y
  CONFIG_SPI_FLASH_SPANSION=y
  CONFIG_NETDEVICES=y
(quoted diff) +0 -0
b/include/configs/p1_p2_rdb_pc.h
Quoted 24 lines
Quoted 24 lines
index 60bedaa..e64805a 100644
include/configs/p1_p2_rdb_pc.h +2 -2
@@ -154,7 +154,7 @@
  #define CONFIG_SYS_L2_SIZE     (256 << 10)
  #endif
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_BOARDNAME "P2020RDB-PCA"
  #define CONFIG_NAND_FSL_ELBC
  #define CONFIG_P2020
@@ -323,7 +323,7 @@
  #define CONFIG_LIBATA
  #define CONFIG_LBA48
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_SYS_CLK_FREQ    100000000
  #else
  #define CONFIG_SYS_CLK_FREQ    66666666
@@ -382,7 +382,7 @@
  #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 
Quoted 8 lines
include/configs/p1_p2_rdb_pc.h line 618
Quoted 8 lines
include/configs/p1_p2_rdb_pc.h +1 -1
  /* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_P2020RDB_PC
  #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
  #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
  #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
@@ -618,7 +618,7 @@
  #define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR +
116 * 1024)
Quoted 2 lines
include/configs/p1_p2_rdb_pc.h line 620
Quoted 2 lines
include/configs/p1_p2_rdb_pc.h +0 -0
  #define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
  #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR +
148 * 1024)
Quoted 5 lines
include/configs/p1_p2_rdb_pc.h line 624
Quoted 5 lines
include/configs/p1_p2_rdb_pc.h +1 -1
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_P2020RDB_PC)
  #define CONFIG_SPL_RELOC_MALLOC_SIZE   (364 << 10)
  #else
  #define CONFIG_SPL_RELOC_MALLOC_SIZE   (108 << 10)
I wonder if it would better that you create a new macro
e.g. CONFIG_P2020RDB_PAB and leave the existing p1_p2_rdb_pc unmodified. I thought this way you could continue developing the support for older boards without changing anything in the current version so the potential risk would be lower.

Quoted 1 line

Just my two cents ;)

The goal is to re-add p1011rdb, p1020rdb, p2010rdb, and p2020rdb into the same directory and rename p1_p2_rdb_pc to p1_p2_rdb as they are all subtle variants of the same board.

As far as I can tell, the risk of changing CONFIG_P2020 to CONFIG_P2020_PC is already pretty low.

It's also a matter of consistency. All of the other boards are suffixed with '_PC' or '_PD' except this one.

I am also considering giving the '_PA' and '_PB' suffix to the older boards. If that happens, which board is newer? P2020 or P2020_PA?

- -Bryan

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York Sun

2016-01-05 17:01 UTC #4 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

In reply to Bryan Hundven

Quoted 4 lines · Bryan Hundven

York,
Just checking if you had seen this patch?

Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?

York

Bryan Hundven

author

2016-01-05 18:38 UTC #5 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Quoted 10 lines · York Sun

Quoted 4 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?

It may be irrelevant. I have a p1020rdb-pb. So technically, unless we want to support p2020rdb-pb (which I don't have, and cannot test), you can ignore this one.

I have work here: https://github.com/bhundven/u-boot/tree/p1_p2_rdb-wip
where I have reverted removing the p1_p2_rdb board, but have started to clean up the difference between p1_p2_rdb and p1_p2_rdb_pc. Eventually, it makes sense to me to move p1_p2_rdb_pc to p1_p2_rdb, as it has pc, and pd. If I can get time to finish, it would have p1020rdb-pb. Then just add the small difference for p1011rdb/p1020rdb-pb.
What are your opinions on that?

The things that are difficult right now are:
* ddr(2) does not use spd on pb?
* I have the ltib cds that came with the board, but I still feel like I'm missing a reference manual that is for the pb version. I can find the pc and pd versions of the 1020RM online. pb just seems a little different.

-Bryan
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York Sun

2016-01-05 21:37 UTC #6 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Quoted 16 lines · Bryan Hundven

Quoted 10 lines · York Sun
Quoted 4 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?
It may be irrelevant. I have a p1020rdb-pb. So technically, unless we want to support p2020rdb-pb (which I don't have, and cannot test), you can ignore this one.

Quoted 7 lines

I have work here: https://github.com/bhundven/u-boot/tree/p1_p2_rdb-wip
where I have reverted removing the p1_p2_rdb board, but have started to clean up the difference between p1_p2_rdb and p1_p2_rdb_pc. Eventually, it makes sense to me to move p1_p2_rdb_pc to p1_p2_rdb, as it has pc, and pd. If I can get time to finish, it would have p1020rdb-pb. Then just add the small difference for p1011rdb/p1020rdb-pb.
What are your opinions on that?

I like clean and small changes.

Quoted 3 lines

The things that are difficult right now are:
* ddr(2) does not use spd on pb?

If I remember correctly, these boards have fixed DDR. RAW timing method was introduced to p1_p2_rdb_pc. You are welcome to use this method. It should be easy to back port.

Quoted 4 lines

* I have the ltib cds that came with the board, but I still feel like I'm missing a reference manual that is for the pb version. I can find the pc and pd versions of the 1020RM online. pb just seems a little different.

These boards are actually made by third parties. I have P1010RDB on my hand. If you need P1020RDB, I can find it for you.

York

york sun

2016-01-05 21:57 UTC #7 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Quoted 37 lines · York Sun

Quoted 16 lines · Bryan Hundven
Quoted 10 lines · York Sun
Quoted 4 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?
It may be irrelevant. I have a p1020rdb-pb. So technically, unless we want to support p2020rdb-pb (which I don't have, and cannot test), you can ignore this one.
Quoted 7 lines
I have work here: https://github.com/bhundven/u-boot/tree/p1_p2_rdb-wip
where I have reverted removing the p1_p2_rdb board, but have started to clean up the difference between p1_p2_rdb and p1_p2_rdb_pc. Eventually, it makes sense to me to move p1_p2_rdb_pc to p1_p2_rdb, as it has pc, and pd. If I can get time to finish, it would have p1020rdb-pb. Then just add the small difference for p1011rdb/p1020rdb-pb.
What are your opinions on that?
I like clean and small changes.
Quoted 3 lines
The things that are difficult right now are:
* ddr(2) does not use spd on pb?
If I remember correctly, these boards have fixed DDR. RAW timing method was introduced to p1_p2_rdb_pc. You are welcome to use this method. It should be easy to back port.

Quoted 8 lines

Quoted 4 lines
* I have the ltib cds that came with the board, but I still feel like I'm missing a reference manual that is for the pb version. I can find the pc and pd versions of the 1020RM online. pb just seems a little different.
These boards are actually made by third parties. I have P1010RDB on my hand. If you need P1020RDB, I can find it for you.

Bryan,

I checked the last release for P1020RDB. It was on 2010-11-01. The schematic is included in the LTIB DVD under help/Hardware/P1020RDB.

York

A message that is not in the archive (sent off-list or not yet received): [email protected]

york sun

2016-07-19 21:50 UTC #9 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Quoted 43 lines · york.sun at nxp.com

Quoted 42 lines · York Sun
Quoted 16 lines · Bryan Hundven
Quoted 10 lines · York Sun
Quoted 4 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?
It may be irrelevant. I have a p1020rdb-pb. So technically, unless we want to support p2020rdb-pb (which I don't have, and cannot test), you can ignore this one.
Quoted 7 lines
I have work here: https://github.com/bhundven/u-boot/tree/p1_p2_rdb-wip
where I have reverted removing the p1_p2_rdb board, but have started to clean up the difference between p1_p2_rdb and p1_p2_rdb_pc. Eventually, it makes sense to me to move p1_p2_rdb_pc to p1_p2_rdb, as it has pc, and pd. If I can get time to finish, it would have p1020rdb-pb. Then just add the small difference for p1011rdb/p1020rdb-pb.
What are your opinions on that?
I like clean and small changes.
Quoted 3 lines
The things that are difficult right now are:
* ddr(2) does not use spd on pb?
If I remember correctly, these boards have fixed DDR. RAW timing method was introduced to p1_p2_rdb_pc. You are welcome to use this method. It should be easy to back port.
Quoted 4 lines
* I have the ltib cds that came with the board, but I still feel like I'm missing a reference manual that is for the pb version. I can find the pc and pd versions of the 1020RM online. pb just seems a little different.

Quoted 9 lines

Quoted 3 lines
These boards are actually made by third parties. I have P1010RDB on my hand. If you need P1020RDB, I can find it for you.
Bryan,
I checked the last release for P1020RDB. It was on 2010-11-01. The schematic is included in the LTIB DVD under help/Hardware/P1020RDB.

Bryan,

Where are we on this patch? If you don't want to move forward, I can drop this for now.

York

Bryan Hundven

author

2016-07-19 21:51 UTC #10 lore raw

PATCH 1/1 powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC

Quoted 55 lines · york sun

Quoted 43 lines · york.sun at nxp.com
Quoted 42 lines · York Sun
Quoted 16 lines · Bryan Hundven
Quoted 10 lines · York Sun
Quoted 4 lines · Bryan Hundven
York,
Just checking if you had seen this patch?
Yes, I noticed. You rename P2020RDB to P2020RDB_PC. Do you have another patch using P2020RDB?
It may be irrelevant. I have a p1020rdb-pb. So technically, unless we want to support p2020rdb-pb (which I don't have, and cannot test), you can ignore this one.
Quoted 7 lines
I have work here: https://github.com/bhundven/u-boot/tree/p1_p2_rdb-wip
where I have reverted removing the p1_p2_rdb board, but have started to clean up the difference between p1_p2_rdb and p1_p2_rdb_pc. Eventually, it makes sense to me to move p1_p2_rdb_pc to p1_p2_rdb, as it has pc, and pd. If I can get time to finish, it would have p1020rdb-pb. Then just add the small difference for p1011rdb/p1020rdb-pb.
What are your opinions on that?
I like clean and small changes.
Quoted 3 lines
The things that are difficult right now are:
* ddr(2) does not use spd on pb?
If I remember correctly, these boards have fixed DDR. RAW timing method was introduced to p1_p2_rdb_pc. You are welcome to use this method. It should be easy to back port.
Quoted 4 lines
* I have the ltib cds that came with the board, but I still feel like I'm missing a reference manual that is for the pb version. I can find the pc and pd versions of the 1020RM online. pb just seems a little different.
Quoted 9 lines
Quoted 3 lines
These boards are actually made by third parties. I have P1010RDB on my hand. If you need P1020RDB, I can find it for you.
Bryan,
I checked the last release for P1020RDB. It was on 2010-11-01. The schematic is included in the LTIB DVD under help/Hardware/P1020RDB.

Quoted 7 lines

Bryan,
Where are we on this patch? If you don't want to move forward, I can drop this for now.
York

York,

Yea, for now I'm not even tracking u-boot. You can drop this.

-Bryan