include: Add support for "do_div" macro

Use the div64 header files from the kernel.

Signed-off-by Wills Wang <[email protected]>

---

Quoted 4 lines · Wills Wang

Use the div64 header files from the kernel.

Signed-off-by Wills Wang <[email protected]>

---

We already have include/div64.h , is that what you're after ?

Best regards,
Marek Vasut

Use the div64 header files from the kernel.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/include/asm/div64.h | 68 +++++++++++++++++++++++++++++++++++++++++++
 include/asm-generic/div64.h   | 59 +++++++++++++++++++++++++++++++++++++
 2 files changed, 127 insertions(+)
 create mode 100644 arch/mips/include/asm/div64.h
 create mode 100644 include/asm-generic/div64.h

arch/mips/include/asm/div64.h new file +68 -0

new file mode 100644
index 0000000..e5e6782
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2000, 2004  Maciej W. Rozycki
+ * Copyright (C) 2003, 07 Ralf Baechle (ralf at linux-mips.org)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_DIV64_H
+#define __ASM_DIV64_H
+
+#include <asm-generic/div64.h>
+
+#if BITS_PER_LONG == 64
+
+#include <linux/types.h>
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define __div64_32(n, base)						\
+({									\
+	unsigned long __cf, __tmp, __tmp2, __i;				\
+	unsigned long __quot32, __mod32;				\
+	unsigned long __high, __low;					\
+	unsigned long long __n;						\
+									\
+	__high = *__n >> 32;						\
+	__low = __n;							\
+	__asm__(							\
+	"	.set	push\n"						\
+	"	.set	noat\n"						\
+	"	.set	noreorder\n"					\
+	"	move	%2, $0\n"					\
+	"	move	%3, $0\n"					\
+	"	b	1f\n"						\
+	"	 li	%4, 0x21\n"					\
+	"0:\n"								\
+	"	sll	$1, %0, 0x1\n"					\
+	"	srl	%3, %0, 0x1f\n"					\
+	"	or	%0, $1, %5\n"					\
+	"	sll	%1, %1, 0x1\n"					\
+	"	sll	%2, %2, 0x1\n"					\
+	"1:\n"								\
+	"	bnez	%3, 2f\n"					\
+	"	 sltu	%5, %0, %z6\n"					\
+	"	bnez	%5, 3f\n"					\
+	"2:\n"								\
+	"	 addiu	%4, %4, -1\n"					\
+	"	subu	%0, %0, %z6\n"					\
+	"	addiu	%2, %2, 1\n"					\
+	"3:\n"								\
+	"	bnez	%4, 0b\n\t"					\
+	"	 srl	%5, %1, 0x1f\n\t"				\
+	"	.set	pop"						\
+	: "=&r" (__mod32), "=&r" (__tmp),				\
+	  "=&r" (__quot32), "=&r" (__cf),				\
+	  "=&r" (__i), "=&r" (__tmp2)					\
+	: "Jr" (base), "0" (__high), "1" (__low));			\
+									\
+	(__n) = __quot32;						\
+	__mod32;							\
+})
+
+#endif /* BITS_PER_LONG == 64 */
+
+#endif /* __ASM_DIV64_H */

include/asm-generic/div64.h new file +59 -0

new file mode 100644
index 0000000..d689fc4
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <[email protected]>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *  uint32_t remainder = *n % base;
+ *  *n = *n / base;
+ *  return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#if BITS_PER_LONG == 64
+
+# define do_div(n, base) ({					\
+	uint32_t __base = (base);				\
+	uint32_t __rem;						\
+	__rem = ((uint64_t)(n)) % __base;			\
+	(n) = ((uint64_t)(n)) / __base;				\
+	__rem;							\
+})
+
+#elif BITS_PER_LONG == 32
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n, base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (likely(((n) >> 32) == 0)) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+})
+
+#else /* BITS_PER_LONG == ?? */
+
+# error do_div() does not yet support the C64
+
+#endif /* BITS_PER_LONG */
+
+#endif /* _ASM_GENERIC_DIV64_H */

Am 25.12.2015 um 19:56 schrieb Wills Wang:

Quoted 9 lines

Use the div64 header files from the kernel.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

Quoted 5 lines

  arch/mips/include/asm/div64.h | 68 +++++++++++++++++++++++++++++++++++++++++++
  include/asm-generic/div64.h   | 59 +++++++++++++++++++++++++++++++++++++
  2 files changed, 127 insertions(+)

create mode 100644 arch/mips/include/asm/div64.h create mode 100644 include/asm-generic/div64.h

please drop this patch, we already have a generic do_div() implementation. Also we do not really need an assembly optimized implementation for MIPS.

Quoted 140 lines

arch/mips/include/asm/div64.h new file +68 -0

new file mode 100644
index 0000000..e5e6782
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2000, 2004  Maciej W. Rozycki
+ * Copyright (C) 2003, 07 Ralf Baechle (ralf at linux-mips.org)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_DIV64_H
+#define __ASM_DIV64_H
+
+#include <asm-generic/div64.h>
+
+#if BITS_PER_LONG == 64
+
+#include <linux/types.h>
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define __div64_32(n, base)						\
+({									\
+	unsigned long __cf, __tmp, __tmp2, __i;				\
+	unsigned long __quot32, __mod32;				\
+	unsigned long __high, __low;					\
+	unsigned long long __n;						\
+									\
+	__high = *__n >> 32;						\
+	__low = __n;							\
+	__asm__(							\
+	"	.set	push\n"						\
+	"	.set	noat\n"						\
+	"	.set	noreorder\n"					\
+	"	move	%2, $0\n"					\
+	"	move	%3, $0\n"					\
+	"	b	1f\n"						\
+	"	 li	%4, 0x21\n"					\
+	"0:\n"								\
+	"	sll	$1, %0, 0x1\n"					\
+	"	srl	%3, %0, 0x1f\n"					\
+	"	or	%0, $1, %5\n"					\
+	"	sll	%1, %1, 0x1\n"					\
+	"	sll	%2, %2, 0x1\n"					\
+	"1:\n"								\
+	"	bnez	%3, 2f\n"					\
+	"	 sltu	%5, %0, %z6\n"					\
+	"	bnez	%5, 3f\n"					\
+	"2:\n"								\
+	"	 addiu	%4, %4, -1\n"					\
+	"	subu	%0, %0, %z6\n"					\
+	"	addiu	%2, %2, 1\n"					\
+	"3:\n"								\
+	"	bnez	%4, 0b\n\t"					\
+	"	 srl	%5, %1, 0x1f\n\t"				\
+	"	.set	pop"						\
+	: "=&r" (__mod32), "=&r" (__tmp),				\
+	  "=&r" (__quot32), "=&r" (__cf),				\
+	  "=&r" (__i), "=&r" (__tmp2)					\
+	: "Jr" (base), "0" (__high), "1" (__low));			\
+									\
+	(__n) = __quot32;						\
+	__mod32;							\
+})
+
+#endif /* BITS_PER_LONG == 64 */
+
+#endif /* __ASM_DIV64_H */

include/asm-generic/div64.h new file +59 -0

new file mode 100644
index 0000000..d689fc4
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <[email protected]>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *  uint32_t remainder = *n % base;
+ *  *n = *n / base;
+ *  return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#if BITS_PER_LONG == 64
+
+# define do_div(n, base) ({					\
+	uint32_t __base = (base);				\
+	uint32_t __rem;						\
+	__rem = ((uint64_t)(n)) % __base;			\
+	(n) = ((uint64_t)(n)) / __base;				\
+	__rem;							\
+})
+
+#elif BITS_PER_LONG == 32
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n, base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (likely(((n) >> 32) == 0)) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+})
+
+#else /* BITS_PER_LONG == ?? */
+
+# error do_div() does not yet support the C64
+
+#endif /* BITS_PER_LONG */
+
+#endif /* _ASM_GENERIC_DIV64_H */

U-boot just use the no MMU virtual address segment(KSEG0/1), this patch enable access the uncached memory range(KSEG1) by flag "MAP_NOCACHE", other flag for KSEG0 access.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/include/asm/io.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/mips/include/asm/io.h +0 -0

index a7ab087..943053d 100644

arch/mips/include/asm/io.h +0 -0

 #define MAP_WRCOMBINE	(0)
 #define MAP_WRBACK	(0)
 #define MAP_WRTHROUGH	(0)

@@ -493,7 +493,10 @@ static inline void sync(void)
 static inline void *

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

---

arch/mips/mach-ath79/ar933x/cpu.c new file +7 -0

+int arch_cpu_init(void)
+{
+	u32 val;
+
+	/*
+	 * Set GPIO10 (UART_SO) as output and enable UART,
+	 * BIT(15) in GPIO_FUNCTION_1 register must be written with 1

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +20 -0

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define DRAM_K0(x)      KSEG0ADDR(x)
+#define DRAM_K1(x)      KSEG1ADDR(x)
+
+	.text
+	.set noreorder
+

arch/mips/mach-ath79/cpu.c new file +21 -0

new file mode 100644
index 0000000..681127c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	char *chip = "????";
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;

Quoted 4 lines · Wills Wang

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

---

[...]

Quoted 11 lines

arch/mips/mach-ath79/ar933x/cpu.c new file +11 -0

+int arch_cpu_init(void)
+{
+	u32 val;
+
+	/*
+	 * Set GPIO10 (UART_SO) as output and enable UART,
+	 * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+	 */
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+	val |= BIT(10);
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));

arch/mips/mach-ath79/ar933x/cpu.c line 32

Quoted 6 lines

arch/mips/mach-ath79/ar933x/cpu.c new file +6 -0

+
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+	val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+	return 0;
+}

Pinmux should be done on a per-board basis, not per-CPU. Also, please use setbits_le32().

Quoted 29 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +23 -0

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define DRAM_K0(x)      KSEG0ADDR(x)
+#define DRAM_K1(x)      KSEG1ADDR(x)
+
+	.text
+	.set noreorder
+
+LEAF(ddr_tap_init)
+	/* Tap settings for the DDR */
+	li      t0, 0xffffffff

arch/mips/mach-ath79/ar933x/ddr_tap.S line 30

Quoted 7 lines

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +7 -0

+	li      t1, DRAM_K0(0x500000)
+	sw      t0, 0x0(t1)
+	sw      t0, 0x4(t1)
+	sw      t0, 0x8(t1)
+	sw      t0, 0xc(t1)
+	nop
+	nop

This should be C code, pretty please.

[...]

arch/mips/mach-ath79/ar933x/lowlevel_init.S

Quoted 5 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +0 -0

lowlevel_init.S should be C code too, I don't see anything which would require this to be ASM .

[...]

Quoted 30 lines

arch/mips/mach-ath79/cpu.c new file +24 -0

new file mode 100644
index 0000000..681127c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	char *chip = "????";
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+	major = id & REV_ID_MAJOR_MASK;

arch/mips/mach-ath79/cpu.c line 31

Quoted 7 lines

arch/mips/mach-ath79/cpu.c new file +7 -0

+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {

I did review this already and my suggestions were ignored :-( I stop here ...

[...]

Quoted 18 lines · Wills Wang

Quoted 4 lines

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

---

[...]

Quoted 11 lines

arch/mips/mach-ath79/ar933x/cpu.c new file +11 -0

+int arch_cpu_init(void)
+{
+    u32 val;
+
+    /*
+     * Set GPIO10 (UART_SO) as output and enable UART,
+     * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+     */
+    val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+    val |= BIT(10);
+    writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));

Quoted 8 lines

arch/mips/mach-ath79/ar933x/cpu.c line 32

Quoted 6 lines

arch/mips/mach-ath79/ar933x/cpu.c new file +6 -0

+
+    val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+    val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+    writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+    return 0;
+}

Pinmux should be done on a per-board basis, not per-CPU. Also, please use setbits_le32().

I don't find other more fit entry for pinctrl initialization. We must set these IO pin before serial initialization. Put it into board directory?

Quoted 29 lines

Quoted 29 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +23 -0

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define DRAM_K0(x)      KSEG0ADDR(x)
+#define DRAM_K1(x)      KSEG1ADDR(x)
+
+    .text
+    .set noreorder
+
+LEAF(ddr_tap_init)
+    /* Tap settings for the DDR */
+    li      t0, 0xffffffff

Quoted 8 lines

arch/mips/mach-ath79/ar933x/ddr_tap.S line 30

Quoted 7 lines

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +7 -0

+    li      t1, DRAM_K0(0x500000)
+    sw      t0, 0x0(t1)
+    sw      t0, 0x4(t1)
+    sw      t0, 0x8(t1)
+    sw      t0, 0xc(t1)
+    nop
+    nop

This should be C code, pretty please.

Must this be change to c code?
I think there should be no problem.

Quoted 10 lines

[...]

arch/mips/mach-ath79/ar933x/lowlevel_init.S

Quoted 5 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +0 -0

lowlevel_init.S should be C code too, I don't see anything which would require this to be ASM .

I don't find SRAM in this chip, we need DDR memory to handle C runtime statck.

Quoted 18 lines

[...]

Quoted 16 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

new file mode 100644
index 0000000..681127c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 18

Quoted 8 lines

arch/mips/mach-ath79/cpu.c new file +8 -0

+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+int print_cpuinfo(void)
+{
+    enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+    char *chip = "????";

Quoted 7 lines

Quoted 7 lines

arch/mips/mach-ath79/cpu.c new file +7 -0

+    u32 id, major, minor;
+    u32 rev = 0;
+    u32 ver = 1;
+
+    id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+    major = id & REV_ID_MAJOR_MASK;
+

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 31

Quoted 6 lines

arch/mips/mach-ath79/cpu.c new file +6 -0

+    switch (major) {
+    case REV_ID_MAJOR_AR71XX:
+        minor = id & AR71XX_REV_ID_MINOR_MASK;
+        rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+        rev &= AR71XX_REV_ID_REVISION_MASK;
+        switch (minor) {

I did review this already and my suggestions were ignored :-( I stop here ...

Sorry, I forget this.
This code inherit from kernel, to change would maintain it much more difficult.

Quoted 1 line

Quoted 4 lines

Quoted 1 line

This should be C code, pretty please.

Must this be change to c code?
I think there should be no problem.

this function is only called from init_dram() which already runs in a full C environment. The conversion to C should be simple. But I would accept the current patch for the initial merge if you do the conversion later.

Quoted 11 lines

Quoted 10 lines

[...]

arch/mips/mach-ath79/ar933x/lowlevel_init.S

Quoted 5 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +0 -0

lowlevel_init.S should be C code too, I don't see anything which would require this to be ASM .

Quoted 2 lines

I don't find SRAM in this chip, we need DDR memory to handle C runtime statck.

currently lowlevel_init() must be coded in assembly because it runs before RAM and caches are initialized. This function only exists to do that initialization. MIPS did this from the beginning. Maybe I will send some patches to use locked cache lines, but that should not be a hard requirement for adding new SoC's. Actually all modern MIPS based SoC's have some type of SRAM or first-stage bootloaders, thus adding the cache line lock feature was not really necessary. I would accept the current patch for the initial merge.

Quoted 15 lines

Quoted 15 lines

arch/mips/mach-ath79/cpu.c line 31

Quoted 13 lines

arch/mips/mach-ath79/cpu.c new file +13 -0

+    u32 id, major, minor;
+    u32 rev = 0;
+    u32 ver = 1;
+
+    id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+    major = id & REV_ID_MAJOR_MASK;
+
+    switch (major) {
+    case REV_ID_MAJOR_AR71XX:
+        minor = id & AR71XX_REV_ID_MINOR_MASK;
+        rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+        rev &= AR71XX_REV_ID_REVISION_MASK;
+        switch (minor) {

I did review this already and my suggestions were ignored :-( I stop here ...

Quoted 3 lines

Sorry, I forget this.
This code inherit from kernel, to change would maintain it much more difficult.

I agree with Marek that a lookup table would be better. But why do you want to add all possible QCA based SoC's? Until there is no supported board for other SoC's than yours, this would be dead code.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/serial/Makefile        |   1 +
 drivers/serial/serial_ar933x.c | 225 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 226 insertions(+)
 create mode 100644 drivers/serial/serial_ar933x.c

drivers/serial/Makefile +1 -0

index dd87147..9a7ad89 100644
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +4 -0

new file mode 100644
index 0000000..efca93c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *

drivers/serial/serial_ar933x.c new file +14 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2

drivers/serial/serial_ar933x.c new file +78 -0

+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+					u32 val, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+				       u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);

drivers/serial/serial_ar933x.c new file +4 -0

+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+

drivers/serial/serial_ar933x.c new file +43 -0

+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+			    AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	u32 val;
+
+	priv->regs = plat->regs;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+	return 0;
+}
+
+static int ar933x_serial_ofdata_to_platdata(struct udevice *dev)
+{

drivers/serial/serial_ar933x.c new file +11 -0

+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {

drivers/serial/serial_ar933x.c new file +5 -0

+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};

Am 25.12.2015 um 19:56 schrieb Wills Wang:

Quoted 37 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

  drivers/serial/Makefile        |   1 +
  drivers/serial/serial_ar933x.c | 225 +++++++++++++++++++++++++++++++++++++++++
  2 files changed, 226 insertions(+)

create mode 100644 drivers/serial/serial_ar933x.c

drivers/serial/Makefile +1 -0

index dd87147..9a7ad89 100644
@@ -17,6 +17,7 @@ endif
 
  obj-$(CONFIG_ALTERA_UART) += altera_uart.o
  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
  obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +7 -0

new file mode 100644
index 0000000..efca93c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+

drivers/serial/serial_ar933x.c line 14

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/div64.h>

use the existing and generic implementation in include/div64.h

drivers/serial/serial_ar933x.c line 16

Quoted 2 lines

drivers/serial/serial_ar933x.c new file +2 -0

+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>

#include <mach/ar71xx_regs.h>

I wonder how you can stil compile your code

Quoted 19 lines

drivers/serial/serial_ar933x.c new file +17 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2
+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff

drivers/serial/serial_ar933x.c line 40

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_platdata {
+	void __iomem *regs;
+};

if you always support device-tree, you do not need platform data

Quoted 81 lines

drivers/serial/serial_ar933x.c new file +81 -0

+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+					u32 val, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+				       u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);
+
+	return 0;
+}

drivers/serial/serial_ar933x.c line 128

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+	u32 data;
+
+	if (c == '\n')
+		ar933x_serial_putc(dev, '\r');

remove this, the serial core driver takes care of it

drivers/serial/serial_ar933x.c line 132

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+
+	do {
+		data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_TX_CSR));

remove this, the serial core driver takes care of it via your pending callback (ar933x_serial_pending)

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+	return 0;
+}
+

drivers/serial/serial_ar933x.c line 146

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+static int ar933x_serial_getc(struct udevice *dev)
+{
+	u32 data;
+
+	do {
+		data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_RX_CSR));

dito

Quoted 46 lines

drivers/serial/serial_ar933x.c new file +46 -0

+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+			    AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	u32 val;
+
+	priv->regs = plat->regs;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+	return 0;
+}
+
+static int ar933x_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+

drivers/serial/serial_ar933x.c line 199

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs = map_physmem(addr,
+				 AR933X_UART_SIZE,
+				 MAP_NOCACHE);

move this code to function ar933x_serial_probe and drop this function

Quoted 14 lines

drivers/serial/serial_ar933x.c new file +14 -0

+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "ath79,ar933x-uart" },
+	{ }
+};

drivers/serial/serial_ar933x.c line 220

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.ofdata_to_platdata = ar933x_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ar933x_serial_platdata),

drop the two lines, you do not need to allocate platdata

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +5 -0

+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};

Quoted 40 lines

Am 25.12.2015 um 19:56 schrieb Wills Wang:

Quoted 38 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

  drivers/serial/Makefile        |   1 +
  drivers/serial/serial_ar933x.c | 225
+++++++++++++++++++++++++++++++++++++++++
  2 files changed, 226 insertions(+)

create mode 100644 drivers/serial/serial_ar933x.c

drivers/serial/Makefile +1 -0

index dd87147..9a7ad89 100644
@@ -17,6 +17,7 @@ endif
    obj-$(CONFIG_ALTERA_UART) += altera_uart.o
  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
  obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +7 -0

new file mode 100644
index 0000000..efca93c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+

Quoted 8 lines

drivers/serial/serial_ar933x.c line 14

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/div64.h>

use the existing and generic implementation in include/div64.h

Ok.

Quoted 5 lines

drivers/serial/serial_ar933x.c line 16

Quoted 2 lines

drivers/serial/serial_ar933x.c new file +2 -0

+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>

#include <mach/ar71xx_regs.h>

I wonder how you can stil compile your code

U-boot create symbolic links from arch/mips/mach-ath79/include/mach to arch/mips/include/asm/arch.

Quoted 19 lines

Quoted 19 lines

drivers/serial/serial_ar933x.c new file +17 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2
+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff

Quoted 8 lines

drivers/serial/serial_ar933x.c line 40

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_platdata {
+    void __iomem *regs;
+};

if you always support device-tree, you do not need platform data

Ok.

Quoted 81 lines

Quoted 81 lines

drivers/serial/serial_ar933x.c new file +81 -0

+
+struct ar933x_serial_priv {
+    void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+                    u32 val, u32 offset)
+{
+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+    u64 t;
+    u32 div;
+
+    div = (2 << 16) * (scale + 1);
+    t = clk;
+    t *= step;
+    t += (div / 2);
+    do_div(t, div);
+
+    return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+                       u32 *scale, u32 *step)
+{
+    u32 tscale, baudrate;
+    long min_diff;
+
+    *scale = 0;
+    *step = 0;
+
+    min_diff = baud;
+    for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+        u64 tstep;
+        int diff;
+
+        tstep = baud * (tscale + 1);
+        tstep *= (2 << 16);
+        do_div(tstep, clk);
+
+        if (tstep > AR933X_UART_CLK_STEP_M)
+            break;
+
+        baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+        diff = abs(baudrate - baud);
+        if (diff < min_diff) {
+            min_diff = diff;
+            *scale = tscale;
+            *step = tstep;
+        }
+    }
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+    u32 val, scale, step;
+
+    val = get_serial_clock();
+    ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+    val  = (scale & AR933X_UART_CLK_SCALE_M)
+            << AR933X_UART_CLK_SCALE_S;
+    val |= (step & AR933X_UART_CLK_STEP_M)
+            << AR933X_UART_CLK_STEP_S;
+    ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);
+
+    return 0;
+}

Quoted 8 lines

drivers/serial/serial_ar933x.c line 128

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+    u32 data;
+
+    if (c == '\n')
+        ar933x_serial_putc(dev, '\r');

remove this, the serial core driver takes care of it

Ok.

Quoted 6 lines

drivers/serial/serial_ar933x.c line 132

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+
+    do {
+        data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_TX_CSR));

remove this, the serial core driver takes care of it via your pending callback (ar933x_serial_pending)

Ok.

Quoted 7 lines

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+    data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+    ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+    return 0;
+}
+

Quoted 8 lines

drivers/serial/serial_ar933x.c line 146

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+static int ar933x_serial_getc(struct udevice *dev)
+{
+    u32 data;
+
+    do {
+        data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_RX_CSR));

dito

Ok.

Quoted 46 lines

Quoted 46 lines

drivers/serial/serial_ar933x.c new file +46 -0

+
+    data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+                AR933X_UART_DATA_REG);
+    return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+    u32 data;
+
+    data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    if (input)
+        return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+    else
+        return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+    u32 val;
+
+    priv->regs = plat->regs;
+
+    /*
+     * UART controller configuration:
+     * - no DMA
+     * - no interrupt
+     * - DCE mode
+     * - no flow control
+     * - set RX ready oride
+     * - set TX ready oride
+     */
+    val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+          AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+    ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+    return 0;
+}
+
+static int ar933x_serial_ofdata_to_platdata(struct udevice *dev)
+{
+    struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+    fdt_addr_t addr;
+

Quoted 8 lines

drivers/serial/serial_ar933x.c line 199

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+    addr = dev_get_addr(dev);
+    if (addr == FDT_ADDR_T_NONE)
+        return -EINVAL;
+
+    plat->regs = map_physmem(addr,
+                 AR933X_UART_SIZE,
+                 MAP_NOCACHE);

move this code to function ar933x_serial_probe and drop this function

Ok.

Quoted 14 lines

Quoted 14 lines

drivers/serial/serial_ar933x.c new file +14 -0

+    return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+    .putc = ar933x_serial_putc,
+    .pending = ar933x_serial_pending,
+    .getc = ar933x_serial_getc,
+    .setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+    { .compatible = "ath79,ar933x-uart" },
+    { }
+};

Quoted 9 lines

drivers/serial/serial_ar933x.c line 220

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+U_BOOT_DRIVER(serial_ar933x) = {
+    .name   = "serial_ar933x",
+    .id = UCLASS_SERIAL,
+    .of_match = ar933x_serial_ids,
+    .ofdata_to_platdata = ar933x_serial_ofdata_to_platdata,
+    .platdata_auto_alloc_size = sizeof(struct ar933x_serial_platdata),

drop the two lines, you do not need to allocate platdata

Ok.

Quoted 6 lines

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +5 -0

+    .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+    .probe = ar933x_serial_probe,
+    .ops    = &ar933x_serial_ops,
+    .flags = DM_FLAG_PRE_RELOC,
+};

Am 25.12.2015 um 19:56 schrieb Wills Wang:

Quoted 34 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

  drivers/serial/Makefile        |   1 +
  drivers/serial/serial_ar933x.c | 225 +++++++++++++++++++++++++++++++++++++++++
  2 files changed, 226 insertions(+)

create mode 100644 drivers/serial/serial_ar933x.c

drivers/serial/Makefile +1 -0

index dd87147..9a7ad89 100644
@@ -17,6 +17,7 @@ endif
 
  obj-$(CONFIG_ALTERA_UART) += altera_uart.o
  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
  obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +4 -0

new file mode 100644
index 0000000..efca93c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *

drivers/serial/serial_ar933x.c line 14

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/div64.h>

use the existing and generic implementation in include/div64.h

drivers/serial/serial_ar933x.c line 16

Quoted 2 lines

drivers/serial/serial_ar933x.c new file +2 -0

+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>

#include <mach/ar71xx_regs.h>

I wonder how you can stil compile your code

Quoted 14 lines

drivers/serial/serial_ar933x.c new file +14 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2

drivers/serial/serial_ar933x.c line 40

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff
+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_platdata {
+	void __iomem *regs;
+};

if you always support device-tree, you do not need platform data

Quoted 78 lines

drivers/serial/serial_ar933x.c new file +78 -0

+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+					u32 val, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+				       u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);

drivers/serial/serial_ar933x.c line 128

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+
+	return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+	u32 data;
+
+	if (c == '\n')
+		ar933x_serial_putc(dev, '\r');

remove this, the serial core driver takes care of it

drivers/serial/serial_ar933x.c line 132

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+
+	do {
+		data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_TX_CSR));

remove this, the serial core driver takes care of it via your pending callback (ar933x_serial_pending)

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+	return 0;
+}
+

drivers/serial/serial_ar933x.c line 146

Quoted 7 lines

drivers/serial/serial_ar933x.c new file +7 -0

+static int ar933x_serial_getc(struct udevice *dev)
+{
+	u32 data;
+
+	do {
+		data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_RX_CSR));

dito

Quoted 44 lines

drivers/serial/serial_ar933x.c new file +43 -0

+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+			    AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	u32 val;
+
+	priv->regs = plat->regs;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+	return 0;
+}
+
+static int ar933x_serial_ofdata_to_platdata(struct udevice *dev)
+{

drivers/serial/serial_ar933x.c line 199

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs = map_physmem(addr,
+				 AR933X_UART_SIZE,
+				 MAP_NOCACHE);

move this code to function ar933x_serial_probe and drop this function

Quoted 11 lines

drivers/serial/serial_ar933x.c new file +11 -0

+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {

drivers/serial/serial_ar933x.c line 220

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+	{ .compatible = "ath79,ar933x-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.ofdata_to_platdata = ar933x_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ar933x_serial_platdata),

drop the two lines, you do not need to allocate platdata

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +5 -0

+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};

Quoted 12 lines

drivers/serial/serial_ar933x.c line 128

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +6 -0

+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+    u32 data;
+
+    if (c == '\n')
+        ar933x_serial_putc(dev, '\r');

remove this, the serial core driver takes care of it

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+
+    do {
+        data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_TX_CSR));

Quoted 3 lines

remove this, the serial core driver takes care of it via your pending callback (ar933x_serial_pending)

Serial core driver don't query and wait the pending function before "serial_getc" and "serial_putc", so these statements can't remove, or board don't work.

Quoted 25 lines

drivers/serial/serial_ar933x.c new file +25 -0

+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	u32 val;
+
+	priv->regs = plat->regs;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+	return 0;
+}
+
+static int ar933x_serial_ofdata_to_platdata(struct udevice *dev)
+{

drivers/serial/serial_ar933x.c line 199

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+	struct ar933x_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs = map_physmem(addr,
+				 AR933X_UART_SIZE,
+				 MAP_NOCACHE);

move this code to function ar933x_serial_probe and drop this function

Quoted 15 lines

drivers/serial/serial_ar933x.c new file +15 -0

+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "ath79,ar933x-uart" },
+	{ }
+};
+

drivers/serial/serial_ar933x.c line 220

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +6 -0

+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.ofdata_to_platdata = ar933x_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ar933x_serial_platdata),

drop the two lines, you do not need to allocate platdata

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/spi/Kconfig     |   8 ++
 drivers/spi/Makefile    |   1 +
 drivers/spi/ath79_spi.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 220 insertions(+)
 create mode 100644 drivers/spi/ath79_spi.c

drivers/spi/Kconfig +8 -0

index 2cdb110..a9e1d31 100644
@@ -23,6 +23,14 @@ config ALTERA_SPI
 	  IP core. Please find details on the "Embedded Peripherals IP
 	  User Guide" of Altera.
 
+config ATH79_SPI
+	bool "Atheros SPI driver"
+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+	  to access SPI NOR flash and other SPI peripherals. This driver
+	  uses driver model and requires a device tree binding to
+	  operate.
+
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help

drivers/spi/Makefile +1 -0

index 3eca745..7fb2926 100644
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o

drivers/spi/ath79_spi.c new file +5 -0

new file mode 100644
index 0000000..dcce584
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+

drivers/spi/ath79_spi.c new file +152 -0

+
+struct ath79_spi_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	return readl(priv->regs + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus,
+					u32 val, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	writel(val, priv->regs + offset);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	uint8_t *rx = din;
+	const uint8_t *tx = dout;
+	uint8_t curbyte, curbitlen, restbits;
+	uint32_t bytes = bitlen / 8;
+	uint32_t out;
+	uint32_t in;
+
+	if (flags & SPI_XFER_BEGIN) {
+		ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+	}
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	/* enable chip select */
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+	while (bytes--) {
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		/* clock starts at inactive polarity */
+		for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			/* setup MSB (to slave) on trailing edge */
+			ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+			ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
+					AR71XX_SPI_REG_IOC);
+			curbyte <<= 1;
+		}
+
+		in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END) {
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
+				AR71XX_SPI_REG_IOC);
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+		ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	}
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	u32 val, div = 0;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
+	val &= ~AR71XX_SPI_CTRL_DIV_MASK;
+	val |= SPI_CLK_DIV(div);
+	ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct ath79_spi_platdata *plat = dev_get_platdata(bus);
+
+	priv->regs = plat->regs;
+
+	/* Init SPI Hardware, disable remap, set clock */
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8),
+			AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static int ath79_spi_ofdata_to_platdata(struct udevice *bus)
+{

drivers/spi/ath79_spi.c new file +14 -0

+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "ath79,ath79-spi" },

drivers/spi/ath79_spi.c new file +3 -0

+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};

Am 25.12.2015 um 19:56 schrieb Wills Wang:

Quoted 58 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

  drivers/spi/Kconfig     |   8 ++
  drivers/spi/Makefile    |   1 +
  drivers/spi/ath79_spi.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++
  3 files changed, 220 insertions(+)

create mode 100644 drivers/spi/ath79_spi.c

drivers/spi/Kconfig +8 -0

index 2cdb110..a9e1d31 100644
@@ -23,6 +23,14 @@ config ALTERA_SPI
  	  IP core. Please find details on the "Embedded Peripherals IP
  	  User Guide" of Altera.
 
+config ATH79_SPI
+	bool "Atheros SPI driver"
+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+	  to access SPI NOR flash and other SPI peripherals. This driver
+	  uses driver model and requires a device tree binding to
+	  operate.
+
  config CADENCE_QSPI
  	bool "Cadence QSPI driver"
  	help

drivers/spi/Makefile +1 -0

index 3eca745..7fb2926 100644
@@ -17,6 +17,7 @@ endif
 
  obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
  obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o

drivers/spi/ath79_spi.c new file +8 -0

new file mode 100644
index 0000000..dcce584
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

drivers/spi/ath79_spi.c line 15

Quoted 7 lines

drivers/spi/ath79_spi.c new file +7 -0

+#include <spi.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>

#include <mach/ar71xx_regs.h>

drivers/spi/ath79_spi.c line 22

Quoted 8 lines

drivers/spi/ath79_spi.c new file +7 -0

+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define SPI_CLK_DIV(x)     (((x) >> 1) - 1)
+
+struct ath79_spi_platdata {
+	void __iomem *regs;
+};

again, platdata is not needed

Quoted 155 lines

drivers/spi/ath79_spi.c new file +155 -0

+
+struct ath79_spi_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	return readl(priv->regs + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus,
+					u32 val, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	writel(val, priv->regs + offset);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	uint8_t *rx = din;
+	const uint8_t *tx = dout;
+	uint8_t curbyte, curbitlen, restbits;
+	uint32_t bytes = bitlen / 8;
+	uint32_t out;
+	uint32_t in;
+
+	if (flags & SPI_XFER_BEGIN) {
+		ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+	}
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	/* enable chip select */
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+	while (bytes--) {
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		/* clock starts at inactive polarity */
+		for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			/* setup MSB (to slave) on trailing edge */
+			ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+			ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
+					AR71XX_SPI_REG_IOC);
+			curbyte <<= 1;
+		}
+
+		in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END) {
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
+				AR71XX_SPI_REG_IOC);
+		ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+		ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	}
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	u32 val, div = 0;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL);
+	val &= ~AR71XX_SPI_CTRL_DIV_MASK;
+	val |= SPI_CLK_DIV(div);
+	ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct ath79_spi_platdata *plat = dev_get_platdata(bus);
+
+	priv->regs = plat->regs;
+
+	/* Init SPI Hardware, disable remap, set clock */
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8),
+			AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static int ath79_spi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct ath79_spi_platdata *plat = dev_get_platdata(bus);
+	fdt_addr_t addr;
+

drivers/spi/ath79_spi.c line 184

Quoted 7 lines

drivers/spi/ath79_spi.c new file +7 -0

+	addr = dev_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs = map_physmem(addr,
+				 AR71XX_SPI_SIZE,
+				 MAP_NOCACHE);

move this code to function ath79_spi_probe and drop this function

Quoted 17 lines

drivers/spi/ath79_spi.c new file +17 -0

+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "ath79,ath79-spi" },
+	{}
+};
+

drivers/spi/ath79_spi.c line 208

Quoted 7 lines

drivers/spi/ath79_spi.c new file +7 -0

+U_BOOT_DRIVER(ath79_spi) = {
+	.name   = "ath79_spi",
+	.id = UCLASS_SPI,
+	.of_match = ath79_spi_ids,
+	.ops    = &ath79_spi_ops,
+	.ofdata_to_platdata = ath79_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ath79_spi_platdata),

again, no platdata needed

Quoted 4 lines

drivers/spi/ath79_spi.c new file +3 -0

+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};

Signed-off-by Wills Wang <[email protected]>

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/Kconfig             |  8 +++++
 arch/mips/dts/Makefile        |  2 +-
 arch/mips/dts/ap121.dts       | 37 +++++++++++++++++++
 arch/mips/dts/ar933x.dtsi     | 64 +++++++++++++++++++++++++++++++++
 board/ath79/ap121/Kconfig     | 15 ++++++++
 board/ath79/ap121/MAINTAINERS |  6 ++++
 board/ath79/ap121/Makefile    |  8 +++++
 board/ath79/ap121/README      | 18 ++++++++++
 board/ath79/ap121/ap121.c     | 17 +++++++++
 board/ath79/ap121/config.mk   | 16 +++++++++
 configs/ap121_defconfig       | 42 ++++++++++++++++++++++
 include/configs/ap121.h       | 82 +++++++++++++++++++++++++++++++++++++++++++
 12 files changed, 314 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/ap121.dts
 create mode 100644 arch/mips/dts/ar933x.dtsi
 create mode 100644 board/ath79/ap121/Kconfig
 create mode 100644 board/ath79/ap121/MAINTAINERS
 create mode 100644 board/ath79/ap121/Makefile
 create mode 100644 board/ath79/ap121/README
 create mode 100644 board/ath79/ap121/ap121.c
 create mode 100644 board/ath79/ap121/config.mk
 create mode 100644 configs/ap121_defconfig
 create mode 100644 include/configs/ap121.h

arch/mips/Kconfig +0 -0

index 7f7e258..09b8709 100644