mips: implement to access the KSEG0/1 memory range in map_physmem

U-boot just use the no MMU virtual address segment(KSEG0/1), this patch enable access the uncached memory range(KSEG1) by flag "MAP_NOCACHE", other flag for KSEG0 access.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/include/asm/io.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/mips/include/asm/io.h +1 -1

index a7ab087..943053d 100644
@@ -485,7 +485,7 @@ static inline void sync(void)
  * that can be used to access the memory range with the caching
  * properties specified by "flags".
  */
-#define MAP_NOCACHE	(0)
+#define MAP_NOCACHE	(1)
 #define MAP_WRCOMBINE	(0)
 #define MAP_WRBACK	(0)
 #define MAP_WRTHROUGH	(0)

arch/mips/include/asm/io.h +1 -0

+		return (void *)KSEG0ADDR(paddr);
 }
 
 /*

Signature · 6 lines

1.9.1

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http://lists.denx.de/mailman/listinfo/u-boot

Quoted 29 lines · On Tue, 29 Dec 2015 19:17:09 +0800 Wills Wang <[email protected]> wrote:

U-boot just use the no MMU virtual address segment(KSEG0/1), this patch enable access the uncached memory range(KSEG1) by flag "MAP_NOCACHE", other flag for KSEG0 access.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

  arch/mips/include/asm/io.h | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)

arch/mips/include/asm/io.h +1 -1

index a7ab087..943053d 100644
@@ -485,7 +485,7 @@ static inline void sync(void)
   * that can be used to access the memory range with the caching
   * properties specified by "flags".
   */
-#define MAP_NOCACHE	(0)
+#define MAP_NOCACHE	(1)
  #define MAP_WRCOMBINE	(0)
  #define MAP_WRBACK	(0)
  #define MAP_WRTHROUGH	(0)

@@ -493,7 +493,10 @@ static inline void sync(void)

arch/mips/include/asm/io.h static inline void sync(void) · line 498

Quoted 7 lines

arch/mips/include/asm/io.h +3 -1

  static inline void *
  map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
  {
-	return (void *)paddr;
+	if (flags)
+		return (void *)KSEG1ADDR(paddr);
+	else

This 'else' is redundant here.

Quoted 11 lines

arch/mips/include/asm/io.h +1 -0

+		return (void *)KSEG0ADDR(paddr);
  }
 
  /*

Signature · 6 lines

1.9.1

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

U-boot just use the no MMU virtual address segment(KSEG0/1), this patch enable access the uncached memory range(KSEG1) by flag "MAP_NOCACHE", other flag for KSEG0 access.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/include/asm/io.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/mips/include/asm/io.h +1 -1

index a7ab087..943053d 100644
@@ -485,7 +485,7 @@ static inline void sync(void)
  * that can be used to access the memory range with the caching
  * properties specified by "flags".
  */
-#define MAP_NOCACHE	(0)
+#define MAP_NOCACHE	(1)
 #define MAP_WRCOMBINE	(0)
 #define MAP_WRBACK	(0)
 #define MAP_WRTHROUGH	(0)

arch/mips/include/asm/io.h +0 -0

 /*
 

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v5:
- Add independent Kconfig
- Use SRAM for initial stack
- Move DDR initialization into board_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version into arch_global_data

Changes in v4:
- Use global_data to save CPU/DDR/AHB clock
- Use arch_global_data to save SOC's type, revison and id

Changes in v3:
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion

Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79

 arch/mips/Kconfig                               |    6 +
 arch/mips/Makefile                              |    1 +
 arch/mips/include/asm/global_data.h             |    6 +
 arch/mips/mach-ath79/Kconfig                    |   20 +
 arch/mips/mach-ath79/Makefile                   |    9 +
 arch/mips/mach-ath79/ar933x/Makefile            |    8 +
 arch/mips/mach-ath79/ar933x/board.c             |   42 +
 arch/mips/mach-ath79/ar933x/clk.c               |   86 ++
 arch/mips/mach-ath79/ar933x/ddr.c               |  215 +++++
 arch/mips/mach-ath79/ar933x/lowlevel_init.S     |  286 ++++++
 arch/mips/mach-ath79/cpu.c                      |  173 ++++
 arch/mips/mach-ath79/dram.c                     |   17 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1136 +++++++++++++++++++++++
 arch/mips/mach-ath79/include/mach/ath79.h       |  143 +++
 arch/mips/mach-ath79/include/mach/ddr.h         |   14 +
 arch/mips/mach-ath79/reset.c                    |   46 +
 16 files changed, 2208 insertions(+)
 create mode 100644 arch/mips/mach-ath79/Kconfig
 create mode 100644 arch/mips/mach-ath79/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/board.c
 create mode 100644 arch/mips/mach-ath79/ar933x/clk.c
 create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c
 create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S
 create mode 100644 arch/mips/mach-ath79/cpu.c
 create mode 100644 arch/mips/mach-ath79/dram.c
 create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h
 create mode 100644 arch/mips/mach-ath79/reset.c

arch/mips/Kconfig +6 -0

index 388e4c0..c9c6aae 100644
@@ -53,6 +53,11 @@ config TARGET_PB1X00
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 	select MIPS_TUNE_4KC
 
+config ARCH_ATH79
+	bool "Support ath79"
+	select OF_CONTROL
+	select DM
+
 endchoice
 
 source "board/dbau1x00/Kconfig"

@@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
 
 if MIPS
 

arch/mips/Makefile +1 -0

index 90cd590..93c461c 100644
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)

arch/mips/include/asm/global_data.h +0 -0

index 2d9a0c9..3799e98 100644

arch/mips/include/asm/global_data.h +0 -0

 };
 
 #include <asm-generic/global_data.h>

arch/mips/mach-ath79/Kconfig new file +20 -0

new file mode 100644
index 0000000..52766c9
@@ -0,0 +1,20 @@
+menu "QCA/Atheros ath79 platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"
+
+config SYS_SOC
+	default "ath79"
+
+config SOC_AR933X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select SYS_MIPS_CACHE_INIT_RAM_LOAD
+	select MIPS_TUNE_24KC
+	help
+	  This supports QCA/Atheros ar933x family SOCs.
+
+endmenu

arch/mips/mach-ath79/Makefile new file +9 -0

new file mode 100644
index 0000000..bc0a41f
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X)	+= ar933x/

arch/mips/mach-ath79/ar933x/Makefile new file +8 -0

new file mode 100644
index 0000000..27c7855
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += board.o
+obj-y += lowlevel_init.o
+obj-y += ddr.o

arch/mips/mach-ath79/ar933x/board.c new file +32 -0

new file mode 100644
index 0000000..b4a76e8
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uart_pin_init(void)
+{
+	u32 val;
+
+	/*
+	 * Set GPIO10 (UART_SO) as output and enable UART,
+	 * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+	 */
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+	val |= BIT(10);
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+	val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+}

arch/mips/mach-ath79/ar933x/clk.c new file +10 -0

new file mode 100644
index 0000000..cfc4bb9
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>

arch/mips/mach-ath79/ar933x/clk.c new file +7 -0

+	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)

arch/mips/mach-ath79/ar933x/clk.c new file +7 -0

+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */

arch/mips/mach-ath79/ar933x/clk.c new file +32 -0

+
+	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
+	div = ((val >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT)
+			& AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+	gd->cpu_clk = pll / div;
+
+	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
+	div = ((val >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT)
+			& AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+	gd->mem_clk = pll / div;
+
+	/* AHB_CLK = PLLOUT / AHB_POST_DIV */
+	div = ((val >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT)
+			& AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+	gd->bus_clk = pll / div;
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+	return gd->mem_clk;
+}

arch/mips/mach-ath79/ar933x/ddr.c new file +8 -0

new file mode 100644
index 0000000..3985299
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

arch/mips/mach-ath79/ar933x/ddr.c new file +95 -0

+	if (val & AR933X_BOOTSTRAP_DDR2) {
+		/* Enable DDR2 */
+		writel(0xA59, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+		/* Precharge All */
+		writel(0x08, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Disable High Temperature Self-Refresh Rate */
+		writel(0x00, regs + AR933X_DDR_REG_EMR2);
+		/* Extended Mode Register 2 Set (EMR2S) */
+		writel(0x10, regs + AR71XX_DDR_REG_CONTROL);
+
+		writel(0x00, regs + AR933X_DDR_REG_EMR3);
+		/* Extended Mode Register 3 Set (EMR3S) */
+		writel(0x20, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL */
+		writel(0x00, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(0x02, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL */
+		writel(0x100, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(0x01, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(0x08, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Auto Refresh */
+		writel(0x04, regs + AR71XX_DDR_REG_CONTROL);
+		writel(0x04, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Write recovery (WR) 6 clock, CAS Latency 3,
+		 * Burst Length 8 */
+		writel(0xa33, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(0x01, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* E7,E8,E9 equal to 1(Enable OCD defaults),
+		 * Enable DLL, Reduced Drive Strength */
+		writel(0x382, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(0x02, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* E7,E8,E9 equal to 0(OCD exit), Enable DLL,
+		 * Reduced Drive Strength */
+		writel(0x402, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(0x02, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh control. Bit 14 is enable.
+		 * Bits<13:0> Refresh time */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(0x4270, regs + AR71XX_DDR_REG_REFRESH);
+		else
+			writel(0x4186, regs + AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */
+		writel(0x08, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		/* DQS 1 Tap Control */
+		writel(0x09, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* For 16-bit DDR */
+		writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+	} else {
+		/* Precharge All */
+		writel(0x08, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Write Mode Word */
+		writel(0x133, regs + AR71XX_DDR_REG_MODE);
+		/* Forces an MRS update cycle in DDR */
+		writel(0x01, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL, High drive strength from DDR */
+		writel(0x02, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(0x02, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(0x08, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* DLL out of reset, CAS Latency 3 */
+		writel(0x33, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(0x01, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh control. Bit 14 is enable.
+		 * Bits<13:0> Refresh time */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(0x4270, regs + AR71XX_DDR_REG_REFRESH);
+		else
+			writel(0x4186, regs + AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */

arch/mips/mach-ath79/ar933x/ddr.c new file +83 -0

+	u32 *addr_k0, *addr_k1, *addr;
+	u32 tap, tap_val, upper, lower;
+	int i, j, dir, err, done;
+
+	addr = (void *)KSEG0ADDR(0x2000);
+	for (i = 0; i < 256; i++) {
+		tap_val = 0;
+		for (j = 0; j < 8; j++) {
+			if (i & (1 << j)) {
+				if (j % 2)
+					tap_val |= 0xffff0000;
+				else
+					tap_val |= 0x0000ffff;
+			}
+
+			if (j % 2) {
+				*addr++ = tap_val;
+				tap_val = 0;
+			}
+		}
+	}
+
+	err = 0;
+	done = 0;
+	dir = 1;
+
+	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	tap_val = tap;
+	while (!done) {
+		err = 0;
+		writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+		for (i = 0; i < 2; i++) {
+			addr_k1 = (void *)KSEG1ADDR(0x2000);
+			addr_k0 = (void *)KSEG0ADDR(0x2000);
+			addr = (void *)KSEG0ADDR(0x3000);
+
+			while (addr_k0 < addr) {
+				if (*addr_k1++ != *addr_k0++) {
+					err = 1;
+					break;
+				}
+			}
+
+			if (err)
+				break;
+		}
+
+		if (err) {
+			if (dir) {
+				dir = 0;
+				tap_val--;
+				upper = tap_val;
+				tap_val = tap;
+			} else {
+				tap_val++;
+				lower = tap_val;
+				done = 1;
+			}
+		} else {
+			if (dir) {
+				if (tap_val < 0x20) {
+					tap_val++;
+				} else {
+					dir = 0;
+					upper = tap_val;
+					tap_val = tap;
+				}
+			} else {
+				if (!tap_val) {
+					lower = tap_val;
+					done = 1;
+				} else {
+					tap_val--;
+				}
+			}
+		}
+	}
+	tap_val = (upper + lower) / 2;
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	tap_val++;
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +286 -0

new file mode 100644
index 0000000..9cc32bf
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val)     SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val)     SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *                      =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *                      =>  1   (0x1)   [Must start at values 1]
+ * bits 21      (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *                      =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *                      =>  1   (0x1)   [0 is illegal!]
+ *                              PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2       (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *                      Software must enable the CPU PLL for normal and
+ *                      then set this bit to 0)
+ * bits 5..6    (2bit)  CPU_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV    =>  1   (DEFAULT, Ratio = 2)
+ *                      AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+	/* These three WLAN_RESET will avoid original issue */
+	li      t3, 0x03
+1:
+	li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	ori     t1, t1, 0x0800
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0xfffff7ff
+	and     t1, t1, t2
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 1b
+	nop
+
+	li      t2, 0x20
+2:
+	beqz    t2, 1b
+	nop
+	addi    t2, t2, -1
+	lw      t5, AR933X_RESET_REG_BOOTSTRAP(t0)
+	andi    t1, t5, 0x10
+	bnez    t1, 2b
+	nop
+
+	li      t1, 0x02110E
+	sw      t1, AR933X_RESET_REG_BOOTSTRAP(t0)
+	nop
+
+	/* RTC Force Wake */
+	li      t0, KSEG1ADDR(AR933X_RTC_BASE)
+	li      t1, 0x03
+	sw      t1, AR933X_RTC_REG_FORCE_WAKE(t0)
+	nop
+	nop
+
+	/* RTC Reset */
+	li      t1, 0x00
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	li      t1, 0x01
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	/* Wait for RTC in on state */
+1:
+	lw      t1, AR933X_RTC_REG_STATUS(t0)
+	andi    t1, t1, 0x02
+	beqz    t1, 1b
+	nop
+
+	/* Program ki/kd */
+	li      t0, KSEG1ADDR(AR933X_SRIF_BASE)
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x19e82f01
+	b       2f
+	nop
+1:
+	li      t1, 0x18e82f01
+2:
+	sw      t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
+
+	/* Program phase shift */
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xc07fffff
+	and     t1, t1, t2
+	li      t2, 0x800000            # meas_at_txon
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* Max AHB Master wait time out ... */
+	li      t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE)
+	li      t1, 0xfffff
+	sw      t1, AR933X_DDR_REG_TIMEOUT_MAX(t0)
+	nop
+
+	/* in some cases, the SoC doesn't start with higher clock on AHB */
+	li      t0, KSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
+	sw      t1, AR933X_PLL_CLOCK_CTRL_REG(t0)
+	nop
+
+	/* Set SETTLE_TIME in CPU PLL */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x0352
+	b       2f
+	nop
+1:
+	li      t1, 0x0550
+2:
+	sw      t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
+	nop
+
+	/* Set nint, frac, refdiv, outdiv, range according to xtal */
+0:
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
+	b       2f
+	nop
+1:
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Put frac bit19:10 configuration */
+	li      t1, 0x1003E8
+	sw      t1, AR933X_PLL_DITHER_FRAC_REG(t0)
+	nop
+
+	/* Clear PLL power down bit in CPU PLL configuration */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, PLL_CPU_CONFIG_VAL_25M
+	b       2f
+	nop
+1:
+	li      t1, PLL_CPU_CONFIG_VAL_40M
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Confirm DDR PLL lock */
+	li      t3, 100
+	li      t4, 0
+
+2:
+	addi    t4, t4, 1
+	bgt     t4, t3, 0b
+	nop
+
+	li      t3, 5
+3:
+	/* Clear do_meas */
+	li      t0, KSEG1ADDR(AR933X_SRIF_BASE)
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xBFFFFFFF
+	and     t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	li      t2, 10
+1:
+	subu    t2, t2, 1
+	bnez    t2, 1b
+	nop
+
+	/* Set do_meas */
+	li      t2, 0x40000000
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* Check meas_done */
+1:
+	lw      t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
+	andi    t1, t1, 0x8
+	beqz    t1, 1b
+	nop
+
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0x007FFFF8
+	and     t1, t1, t2
+	srl     t1, t1, 3
+	li      t2, 0x4000
+	bgt     t1, t2, 2b
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 3b
+	nop
+
+	/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+	li      t0, KSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, PLL_CLK_CONTROL_VAL
+	sw      t1, AR933X_PLL_CLOCK_CTRL_REG(t0)
+	nop
+
+	nop
+	jr ra
+	nop
+    END(lowlevel_init)

arch/mips/mach-ath79/cpu.c new file +8 -0

new file mode 100644
index 0000000..c03480d
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

arch/mips/mach-ath79/cpu.c new file +124 -0

+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			chip = "7130";
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;
+			chip = "7141";
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			chip = "7161";
+			break;
+		}
+		break;
+
+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		chip = "7240";
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR7241:
+		soc = ATH79_SOC_AR7241;
+		chip = "7241";
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR7242:
+		soc = ATH79_SOC_AR7242;
+		chip = "7242";
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR913X:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR913X_REV_ID_MINOR_AR9130:
+			soc = ATH79_SOC_AR9130;
+			chip = "9130";
+			break;
+
+		case AR913X_REV_ID_MINOR_AR9132:
+			soc = ATH79_SOC_AR9132;
+			chip = "9132";
+			break;
+		}
+		break;
+
+	case REV_ID_MAJOR_AR9330:
+		soc = ATH79_SOC_AR9330;
+		chip = "9330";
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR9331:
+		soc = ATH79_SOC_AR9331;
+		chip = "9331";
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR9341:
+		soc = ATH79_SOC_AR9341;
+		chip = "9341";
+		rev = id & AR934X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR9342:
+		soc = ATH79_SOC_AR9342;
+		chip = "9342";
+		rev = id & AR934X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR9344:
+		soc = ATH79_SOC_AR9344;
+		chip = "9344";
+		rev = id & AR934X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9533_V2:
+		ver = 2;
+		/* drop through */
+
+	case REV_ID_MAJOR_QCA9533:
+		soc = ATH79_SOC_QCA9533;
+		chip = "9533";
+		rev = id & QCA953X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9556:
+		soc = ATH79_SOC_QCA9556;
+		chip = "9556";
+		rev = id & QCA955X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9558:
+		soc = ATH79_SOC_QCA9558;
+		chip = "9558";
+		rev = id & QCA955X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_TP9343:
+		soc = ATH79_SOC_TP9343;
+		chip = "9343";
+		rev = id & QCA956X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9561:

arch/mips/mach-ath79/cpu.c new file +21 -0

+	puts("SoC:   ");
+	switch (soc) {
+	case ATH79_SOC_QCA9533:
+	case ATH79_SOC_QCA9556:
+	case ATH79_SOC_QCA9558:
+	case ATH79_SOC_QCA9561:
+		printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
+		       ver, rev);
+		break;
+	case ATH79_SOC_TP9343:
+		printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
+		break;
+	case ATH79_SOC_UNKNOWN:
+		printf("ATH79: unknown SoC, id:0x%08x", id);
+		break;
+	default:
+		printf("Atheros AR%s rev %u\n", chip, rev);
+	}
+
+	return 0;
+}

arch/mips/mach-ath79/dram.c new file +6 -0

new file mode 100644
index 0000000..dbd56d2
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */

arch/mips/mach-ath79/dram.c new file +1 -0

+}

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +1136 -0

new file mode 100644
index 0000000..61321e8
@@ -0,0 +1,1136 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015 Wills Wang, <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)			(1UL << (nr))
+#endif
+#endif
+
+#define AR71XX_APB_BASE		0x18000000
+#define AR71XX_GE0_BASE		0x19000000
+#define AR71XX_GE0_SIZE		0x10000
+#define AR71XX_GE1_BASE		0x1a000000
+#define AR71XX_GE1_SIZE		0x10000
+#define AR71XX_EHCI_BASE	0x1b000000
+#define AR71XX_EHCI_SIZE	0x1000
+#define AR71XX_OHCI_BASE	0x1c000000
+#define AR71XX_OHCI_SIZE	0x1000
+#define AR71XX_SPI_BASE		0x1f000000
+#define AR71XX_SPI_SIZE		0x01000000
+
+#define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE	0x100
+#define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE	0x100
+#define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE	0x100
+#define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE	0x100
+#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE		0x100
+#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE	0x100
+#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE		0x100
+
+#define AR71XX_PCI_MEM_BASE	0x10000000
+#define AR71XX_PCI_MEM_SIZE	0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS	0x10000000
+#define AR71XX_PCI_WIN1_OFFS	0x11000000
+#define AR71XX_PCI_WIN2_OFFS	0x12000000
+#define AR71XX_PCI_WIN3_OFFS	0x13000000
+#define AR71XX_PCI_WIN4_OFFS	0x14000000
+#define AR71XX_PCI_WIN5_OFFS	0x15000000
+#define AR71XX_PCI_WIN6_OFFS	0x16000000
+#define AR71XX_PCI_WIN7_OFFS	0x07000000
+
+#define AR71XX_PCI_CFG_BASE	\
+	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE	0x100
+
+#define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE	0x100
+#define AR7240_OHCI_BASE	0x1b000000
+#define AR7240_OHCI_SIZE	0x1000
+
+#define AR724X_PCI_MEM_BASE	0x10000000
+#define AR724X_PCI_MEM_SIZE	0x04000000
+
+#define AR724X_PCI_CFG_BASE	0x14000000
+#define AR724X_PCI_CFG_SIZE	0x1000
+#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE	0x1000
+#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE	0x100
+
+#define AR724X_EHCI_BASE	0x1b000000
+#define AR724X_EHCI_SIZE	0x1000
+
+#define AR913X_EHCI_BASE	0x1b000000
+#define AR913X_EHCI_SIZE	0x1000
+#define AR913X_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE	0x30000
+
+#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE	0x14
+#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE	0x04
+#define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE	0x20000
+#define AR933X_RTC_BASE		(AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE		0x1000
+#define AR933X_EHCI_BASE	0x1b000000
+#define AR933X_EHCI_SIZE	0x1000
+#define AR933X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE	0x1000
+
+#define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE	0x14
+#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE	0x20000
+#define AR934X_EHCI_BASE	0x1b000000
+#define AR934X_EHCI_SIZE	0x200
+#define AR934X_NFC_BASE		0x1b000200
+#define AR934X_NFC_SIZE		0xb8
+#define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE	0x1000
+
+#define QCA953X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE	0x14
+#define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE	0x20000
+#define QCA953X_EHCI_BASE	0x1b000000
+#define QCA953X_EHCI_SIZE	0x200
+#define QCA953X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE	0x1000
+
+#define QCA953X_PCI_CFG_BASE0	0x14000000
+#define QCA953X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0	0x10000000
+#define QCA953X_PCI_MEM_SIZE	0x02000000
+
+#define QCA955X_PCI_MEM_BASE0	0x10000000
+#define QCA955X_PCI_MEM_BASE1	0x12000000
+#define QCA955X_PCI_MEM_SIZE	0x02000000
+#define QCA955X_PCI_CFG_BASE0	0x14000000
+#define QCA955X_PCI_CFG_BASE1	0x16000000
+#define QCA955X_PCI_CFG_SIZE	0x1000
+#define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE	0x1000
+#define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE	0x100
+
+#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE	0x40
+#define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE	0x20000
+#define QCA955X_EHCI0_BASE	0x1b000000
+#define QCA955X_EHCI1_BASE	0x1b400000
+#define QCA955X_EHCI_SIZE	0x1000
+#define QCA955X_NFC_BASE	0x1b800200
+#define QCA955X_NFC_SIZE	0xb8
+
+#define QCA956X_PCI_MEM_BASE1	0x12000000
+#define QCA956X_PCI_MEM_SIZE	0x02000000
+#define QCA956X_PCI_CFG_BASE1	0x16000000
+#define QCA956X_PCI_CFG_SIZE	0x1000
+#define QCA956X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE	0x1000
+#define QCA956X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE	0x100
+
+#define QCA956X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE	0x20000
+#define QCA956X_EHCI0_BASE	0x1b000000
+#define QCA956X_EHCI1_BASE	0x1b400000
+#define QCA956X_EHCI_SIZE	0x200
+#define QCA956X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE	0x64
+
+#define AR9300_OTP_BASE		0x14000
+#define AR9300_OTP_STATUS	0x15f18
+#define AR9300_OTP_STATUS_TYPE		0x7
+#define AR9300_OTP_STATUS_VALID		0x4
+#define AR9300_OTP_STATUS_ACCESS_BUSY	0x2
+#define AR9300_OTP_STATUS_SM_BUSY	0x1
+#define AR9300_OTP_READ_DATA	0x15f1c
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_CONFIG		0x00
+#define AR71XX_DDR_REG_CONFIG2		0x04
+#define AR71XX_DDR_REG_MODE		0x08
+#define AR71XX_DDR_REG_EMR		0x0c
+#define AR71XX_DDR_REG_CONTROL		0x10
+#define AR71XX_DDR_REG_REFRESH		0x14
+#define AR71XX_DDR_REG_RD_CYCLE		0x18
+#define AR71XX_DDR_REG_TAP_CTRL0	0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1	0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0		0x7c
+#define AR71XX_DDR_REG_PCI_WIN1		0x80
+#define AR71XX_DDR_REG_PCI_WIN2		0x84
+#define AR71XX_DDR_REG_PCI_WIN3		0x88
+#define AR71XX_DDR_REG_PCI_WIN4		0x8c
+#define AR71XX_DDR_REG_PCI_WIN5		0x90
+#define AR71XX_DDR_REG_PCI_WIN6		0x94
+#define AR71XX_DDR_REG_PCI_WIN7		0x98
+#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
+#define AR71XX_DDR_REG_FLUSH_USB	0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI	0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0	0x7c
+#define AR724X_DDR_REG_FLUSH_GE1	0x80
+#define AR724X_DDR_REG_FLUSH_USB	0x84
+#define AR724X_DDR_REG_FLUSH_PCIE	0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0	0x7c
+#define AR913X_DDR_REG_FLUSH_GE1	0x80
+#define AR913X_DDR_REG_FLUSH_USB	0x84
+#define AR913X_DDR_REG_FLUSH_WMAC	0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0	0x7c
+#define AR933X_DDR_REG_FLUSH_GE1	0x80
+#define AR933X_DDR_REG_FLUSH_USB	0x84
+#define AR933X_DDR_REG_FLUSH_WMAC	0x88
+#define AR933X_DDR_REG_DDR2_CONFIG	0x8c
+#define AR933X_DDR_REG_EMR2		0x90
+#define AR933X_DDR_REG_EMR3		0x94
+#define AR933X_DDR_REG_BURST		0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX	0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT	0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR	0x9c
+
+#define AR934X_DDR_REG_FLUSH_GE0	0x9c
+#define AR934X_DDR_REG_FLUSH_GE1	0xa0
+#define AR934X_DDR_REG_FLUSH_USB	0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC	0xac
+
+#define QCA953X_DDR_REG_FLUSH_GE0	0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1	0xa0
+#define QCA953X_DDR_REG_FLUSH_USB	0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE	0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC	0xac
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG	0x00
+#define AR71XX_PLL_REG_SEC_CONFIG	0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14
+
+#define AR71XX_PLL_DIV_SHIFT		3
+#define AR71XX_PLL_DIV_MASK		0x1f
+#define AR71XX_CPU_DIV_SHIFT		16
+#define AR71XX_CPU_DIV_MASK		0x3
+#define AR71XX_DDR_DIV_SHIFT		18
+#define AR71XX_DDR_DIV_MASK		0x3
+#define AR71XX_AHB_DIV_SHIFT		20
+#define AR71XX_AHB_DIV_MASK		0x7
+
+#define AR71XX_ETH0_PLL_SHIFT		17
+#define AR71XX_ETH1_PLL_SHIFT		19
+
+#define AR724X_PLL_REG_CPU_CONFIG	0x00
+#define AR724X_PLL_REG_PCIE_CONFIG	0x18
+
+#define AR724X_PLL_DIV_SHIFT		0
+#define AR724X_PLL_DIV_MASK		0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT	10
+#define AR724X_PLL_REF_DIV_MASK		0xf
+#define AR724X_AHB_DIV_SHIFT		19
+#define AR724X_AHB_DIV_MASK		0x1
+#define AR724X_DDR_DIV_SHIFT		22
+#define AR724X_DDR_DIV_MASK		0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG	0x00
+#define AR913X_PLL_REG_ETH_CONFIG	0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK	0x18
+
+#define AR913X_PLL_DIV_SHIFT		0
+#define AR913X_PLL_DIV_MASK		0x3ff
+#define AR913X_DDR_DIV_SHIFT		22
+#define AR913X_DDR_DIV_MASK		0x3
+#define AR913X_AHB_DIV_SHIFT		19
+#define AR913X_AHB_DIV_MASK		0x1
+
+#define AR913X_ETH0_PLL_SHIFT		20
+#define AR913X_ETH1_PLL_SHIFT		22
+
+#define AR933X_PLL_CPU_CONFIG_REG	0x00
+#define AR933X_PLL_CLOCK_CTRL_REG	0x08
+#define AR933X_PLL_DITHER_FRAC_REG	0x10
+
+#define AR933X_PLL_CPU_CONFIG_DIVINT_SHIFT	10
+#define AR933X_PLL_CPU_CONFIG_DIVINT_MASK	0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG		0x00
+#define AR934X_PLL_DDR_CONFIG_REG		0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
+
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG		0x00
+#define QCA953X_PLL_DDR_CONFIG_REG		0x04
+#define QCA953X_PLL_CLK_CTRL_REG		0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG	0x2c
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG	0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT	6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK	0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT	10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK	0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA955X_PLL_CPU_CONFIG_REG		0x00
+#define QCA955X_PLL_DDR_CONFIG_REG		0x04
+#define QCA955X_PLL_CLK_CTRL_REG		0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG			0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG			0x04
+#define QCA956X_PLL_DDR_CONFIG_REG			0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG			0x0c
+#define QCA956X_PLL_CLK_CTRL_REG			0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL	BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ	0x00
+#define AR71XX_USB_CTRL_REG_CONFIG	0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER			0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD		0x04
+#define AR71XX_RESET_REG_WDOG_CTRL		0x08
+#define AR71XX_RESET_REG_WDOG			0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
+#define AR71XX_RESET_REG_RESET_MODULE		0x24
+#define AR71XX_RESET_REG_PERFC_CTRL		0x2c
+#define AR71XX_RESET_REG_PERFC0			0x30
+#define AR71XX_RESET_REG_PERFC1			0x34
+#define AR71XX_RESET_REG_REV_ID			0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS	0x18
+#define AR913X_RESET_REG_RESET_MODULE		0x1c
+#define AR913X_RESET_REG_PERF_CTRL		0x20
+#define AR913X_RESET_REG_PERFC0			0x24
+#define AR913X_RESET_REG_PERFC1			0x28
+
+#define AR724X_RESET_REG_RESET_MODULE		0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE		0x1c
+#define AR933X_RESET_REG_BOOTSTRAP		0xac
+
+#define AR934X_RESET_REG_RESET_MODULE		0x1c
+#define AR934X_RESET_REG_BOOTSTRAP		0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE		0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP		0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE		0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP		0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE		0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP		0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS	0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK	BIT(28)
+#define MISC_INT_ETHSW			BIT(12)
+#define MISC_INT_TIMER4			BIT(10)
+#define MISC_INT_TIMER3			BIT(9)
+#define MISC_INT_TIMER2			BIT(8)
+#define MISC_INT_DMA			BIT(7)
+#define MISC_INT_OHCI			BIT(6)
+#define MISC_INT_PERFC			BIT(5)
+#define MISC_INT_WDOG			BIT(4)
+#define MISC_INT_UART			BIT(3)
+#define MISC_INT_GPIO			BIT(2)
+#define MISC_INT_ERROR			BIT(1)
+#define MISC_INT_TIMER			BIT(0)
+
+#define AR71XX_RESET_EXTERNAL		BIT(28)
+#define AR71XX_RESET_FULL_CHIP		BIT(24)
+#define AR71XX_RESET_CPU_NMI		BIT(21)
+#define AR71XX_RESET_CPU_COLD		BIT(20)
+#define AR71XX_RESET_DMA		BIT(19)
+#define AR71XX_RESET_SLIC		BIT(18)
+#define AR71XX_RESET_STEREO		BIT(17)
+#define AR71XX_RESET_DDR		BIT(16)
+#define AR71XX_RESET_GE1_MAC		BIT(13)
+#define AR71XX_RESET_GE1_PHY		BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE	BIT(10)
+#define AR71XX_RESET_GE0_MAC		BIT(9)
+#define AR71XX_RESET_GE0_PHY		BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL	BIT(6)
+#define AR71XX_RESET_USB_HOST		BIT(5)
+#define AR71XX_RESET_USB_PHY		BIT(4)
+#define AR71XX_RESET_PCI_BUS		BIT(1)
+#define AR71XX_RESET_PCI_CORE		BIT(0)
+
+#define AR7240_RESET_USB_HOST		BIT(5)
+#define AR7240_RESET_OHCI_DLL		BIT(3)
+
+#define AR724X_RESET_GE1_MDIO		BIT(23)
+#define AR724X_RESET_GE0_MDIO		BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
+#define AR724X_RESET_PCIE_PHY		BIT(7)
+#define AR724X_RESET_PCIE		BIT(6)
+#define AR724X_RESET_USB_HOST		BIT(5)
+#define AR724X_RESET_USB_PHY		BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC		BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE	BIT(10)
+#define AR913X_RESET_USB_HOST		BIT(5)
+#define AR913X_RESET_USB_PHY		BIT(4)
+
+#define AR933X_RESET_GE1_MDIO		BIT(23)
+#define AR933X_RESET_GE0_MDIO		BIT(22)
+#define AR933X_RESET_GE1_MAC		BIT(13)
+#define AR933X_RESET_WMAC		BIT(11)
+#define AR933X_RESET_GE0_MAC		BIT(9)
+#define AR933X_RESET_USB_HOST		BIT(5)
+#define AR933X_RESET_USB_PHY		BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define AR934X_RESET_HOST		BIT(31)
+#define AR934X_RESET_SLIC		BIT(30)
+#define AR934X_RESET_HDMA		BIT(29)
+#define AR934X_RESET_EXTERNAL		BIT(28)
+#define AR934X_RESET_RTC		BIT(27)
+#define AR934X_RESET_PCIE_EP_INT	BIT(26)
+#define AR934X_RESET_CHKSUM_ACC		BIT(25)
+#define AR934X_RESET_FULL_CHIP		BIT(24)
+#define AR934X_RESET_GE1_MDIO		BIT(23)
+#define AR934X_RESET_GE0_MDIO		BIT(22)
+#define AR934X_RESET_CPU_NMI		BIT(21)
+#define AR934X_RESET_CPU_COLD		BIT(20)
+#define AR934X_RESET_HOST_RESET_INT	BIT(19)
+#define AR934X_RESET_PCIE_EP		BIT(18)
+#define AR934X_RESET_UART1		BIT(17)
+#define AR934X_RESET_DDR		BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF		BIT(14)
+#define AR934X_RESET_GE1_MAC		BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
+#define AR934X_RESET_HOST_DMA_INT	BIT(10)
+#define AR934X_RESET_GE0_MAC		BIT(9)
+#define AR934X_RESET_ETH_SWITCH		BIT(8)
+#define AR934X_RESET_PCIE_PHY		BIT(7)
+#define AR934X_RESET_PCIE		BIT(6)
+#define AR934X_RESET_USB_HOST		BIT(5)
+#define AR934X_RESET_USB_PHY		BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
+#define AR934X_RESET_LUT		BIT(2)
+#define AR934X_RESET_MBOX		BIT(1)
+#define AR934X_RESET_I2S		BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR	BIT(29)
+#define QCA953X_RESET_EXTERNAL		BIT(28)
+#define QCA953X_RESET_RTC		BIT(27)
+#define QCA953X_RESET_FULL_CHIP		BIT(24)
+#define QCA953X_RESET_GE1_MDIO		BIT(23)
+#define QCA953X_RESET_GE0_MDIO		BIT(22)
+#define QCA953X_RESET_CPU_NMI		BIT(21)
+#define QCA953X_RESET_CPU_COLD		BIT(20)
+#define QCA953X_RESET_DDR		BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA953X_RESET_GE1_MAC		BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG	BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG	BIT(11)
+#define QCA953X_RESET_GE0_MAC		BIT(9)
+#define QCA953X_RESET_ETH_SWITCH	BIT(8)
+#define QCA953X_RESET_PCIE_PHY		BIT(7)
+#define QCA953X_RESET_PCIE		BIT(6)
+#define QCA953X_RESET_USB_HOST		BIT(5)
+#define QCA953X_RESET_USB_PHY		BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define QCA955X_RESET_HOST		BIT(31)
+#define QCA955X_RESET_SLIC		BIT(30)
+#define QCA955X_RESET_HDMA		BIT(29)
+#define QCA955X_RESET_EXTERNAL		BIT(28)
+#define QCA955X_RESET_RTC		BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
+#define QCA955X_RESET_FULL_CHIP		BIT(24)
+#define QCA955X_RESET_GE1_MDIO		BIT(23)
+#define QCA955X_RESET_GE0_MDIO		BIT(22)
+#define QCA955X_RESET_CPU_NMI		BIT(21)
+#define QCA955X_RESET_CPU_COLD		BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
+#define QCA955X_RESET_PCIE_EP		BIT(18)
+#define QCA955X_RESET_UART1		BIT(17)
+#define QCA955X_RESET_DDR		BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF		BIT(14)
+#define QCA955X_RESET_GE1_MAC		BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
+#define QCA955X_RESET_GE0_MAC		BIT(9)
+#define QCA955X_RESET_SGMII		BIT(8)
+#define QCA955X_RESET_PCIE_PHY		BIT(7)
+#define QCA955X_RESET_PCIE		BIT(6)
+#define QCA955X_RESET_USB_HOST		BIT(5)
+#define QCA955X_RESET_USB_PHY		BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
+#define QCA955X_RESET_LUT		BIT(2)
+#define QCA955X_RESET_MBOX		BIT(1)
+#define QCA955X_RESET_I2S		BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
+#define AR933X_BOOTSTRAP_DDR2		BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1		BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2	BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1	BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE	BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40	BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1		BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40	BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX			BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
+#define QCA955X_EXT_INT_USB1			BIT(24)
+#define QCA955X_EXT_INT_USB2			BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC		BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX			BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP		BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP		BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1		BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0		BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1		BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2		BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3		BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2		BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0		BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1		BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2		BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3		BIT(16)
+#define QCA956X_EXT_INT_USB1			BIT(24)
+#define QCA956X_EXT_INT_USB2			BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+	 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+	(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+	(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK		0xfff0
+#define REV_ID_MAJOR_AR71XX		0x00a0
+#define REV_ID_MAJOR_AR913X		0x00b0
+#define REV_ID_MAJOR_AR7240		0x00c0
+#define REV_ID_MAJOR_AR7241		0x0100
+#define REV_ID_MAJOR_AR7242		0x1100
+#define REV_ID_MAJOR_AR9330		0x0110
+#define REV_ID_MAJOR_AR9331		0x1110
+#define REV_ID_MAJOR_AR9341		0x0120
+#define REV_ID_MAJOR_AR9342		0x1120
+#define REV_ID_MAJOR_AR9344		0x2120
+#define REV_ID_MAJOR_QCA9533		0x0140
+#define REV_ID_MAJOR_QCA9533_V2		0x0160
+#define REV_ID_MAJOR_QCA9556		0x0130
+#define REV_ID_MAJOR_QCA9558		0x1130
+#define REV_ID_MAJOR_TP9343		0x0150
+#define REV_ID_MAJOR_QCA9561		0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK	0x3
+#define AR71XX_REV_ID_MINOR_AR7130	0x0
+#define AR71XX_REV_ID_MINOR_AR7141	0x1
+#define AR71XX_REV_ID_MINOR_AR7161	0x2
+#define AR71XX_REV_ID_REVISION_MASK	0x3
+#define AR71XX_REV_ID_REVISION_SHIFT	2
+
+#define AR913X_REV_ID_MINOR_AR9130	0x0
+#define AR913X_REV_ID_MINOR_AR9132	0x1
+
+#define AR934X_REV_ID_REVISION_MASK	0xf
+#define QCA953X_REV_ID_REVISION_MASK	0xf
+#define QCA955X_REV_ID_REVISION_MASK	0xf
+#define QCA956X_REV_ID_REVISION_MASK	0xf
+
+/*
+ * RTC block
+ */
+#define AR933X_RTC_REG_RESET		0x40
+#define AR933X_RTC_REG_STATUS		0x44
+#define AR933X_RTC_REG_DERIVED		0x48
+#define AR933X_RTC_REG_FORCE_WAKE	0x4c
+#define AR933X_RTC_REG_INT_CAUSE	0x50
+#define AR933X_RTC_REG_CAUSE_CLR	0x50
+#define AR933X_RTC_REG_INT_ENABLE	0x54
+#define AR933X_RTC_REG_INT_MASKE	0x58
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS	0x00	/* Function Select */
+#define AR71XX_SPI_REG_CTRL	0x04	/* SPI Control */
+#define AR71XX_SPI_REG_IOC	0x08	/* SPI I/O Control */
+#define AR71XX_SPI_REG_RDS	0x0c	/* Read Data Shift */
+
+#define AR71XX_SPI_FS_GPIO	BIT(0)	/* Enable GPIO mode */
+
+#define AR71XX_SPI_CTRL_RD	BIT(6)	/* Remap Disable */
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO	BIT(0)	/* Data Out pin */
+#define AR71XX_SPI_IOC_CLK	BIT(8)	/* CLK pin */
+#define AR71XX_SPI_IOC_CS(n)	BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0	AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1	AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2	AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
+				 AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE		0x00
+#define AR71XX_GPIO_REG_IN		0x04
+#define AR71XX_GPIO_REG_OUT		0x08
+#define AR71XX_GPIO_REG_SET		0x0c
+#define AR71XX_GPIO_REG_CLEAR		0x10
+#define AR71XX_GPIO_REG_INT_MODE	0x14
+#define AR71XX_GPIO_REG_INT_TYPE	0x18
+#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
+#define AR71XX_GPIO_REG_INT_PENDING	0x20
+#define AR71XX_GPIO_REG_INT_ENABLE	0x24
+#define AR71XX_GPIO_REG_FUNC		0x28
+#define AR933X_GPIO_REG_FUNC		0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0	0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1	0x30
+#define AR934X_GPIO_REG_OUT_FUNC2	0x34
+#define AR934X_GPIO_REG_OUT_FUNC3	0x38
+#define AR934X_GPIO_REG_OUT_FUNC4	0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5	0x40
+#define AR934X_GPIO_REG_FUNC		0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0	0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1	0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2	0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3	0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4	0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0	0x44
+#define QCA953X_GPIO_REG_FUNC		0x6c
+
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1		10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2		11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0		9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK		8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI		12
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1		41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2		42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3		43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5		45
+
+#define QCA955X_GPIO_REG_OUT_FUNC0	0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1	0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2	0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3	0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4	0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5	0x40
+#define QCA955X_GPIO_REG_FUNC		0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0	0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1	0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2	0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3	0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4	0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5	0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0	0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3	0x50
+#define QCA956X_GPIO_REG_FUNC		0x6c
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO	32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC	33
+
+#define AR71XX_GPIO_COUNT		16
+#define AR7240_GPIO_COUNT		18
+#define AR7241_GPIO_COUNT		20
+#define AR913X_GPIO_COUNT		22
+#define AR933X_GPIO_COUNT		30
+#define AR934X_GPIO_COUNT		23
+#define QCA953X_GPIO_COUNT		18
+#define QCA955X_GPIO_COUNT		24
+#define QCA956X_GPIO_COUNT		23
+
+/*
+ * SRIF block
+ */
+#define AR933X_SRIF_DDR_DPLL1_REG	0x240
+#define AR933X_SRIF_DDR_DPLL2_REG	0x244
+#define AR933X_SRIF_DDR_DPLL3_REG	0x248
+#define AR933X_SRIF_DDR_DPLL4_REG	0x24c
+
+#define AR934X_SRIF_CPU_DPLL1_REG	0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG	0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG	0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG	0x240
+#define AR934X_SRIF_DDR_DPLL2_REG	0x244
+#define AR934X_SRIF_DDR_DPLL3_REG	0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT	18
+#define AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+
+#define QCA953X_SRIF_CPU_DPLL1_REG	0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG	0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG	0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG	0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG	0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG	0x248
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT	27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK	0x1f
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT	18
+#define QCA953X_SRIF_DPLL1_NINT_MASK	0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT	13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK	0x7
+
+#define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN		BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)
+
+#define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN		BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
+
+#define AR933X_GPIO_FUNC_XLNA_EN		BIT(12)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO		0
+#define AR934X_GPIO_OUT_SPI_CS1	7
+#define AR934X_GPIO_OUT_LED_LINK0	41
+#define AR934X_GPIO_OUT_LED_LINK1	42
+#define AR934X_GPIO_OUT_LED_LINK2	43
+#define AR934X_GPIO_OUT_LED_LINK3	44
+#define AR934X_GPIO_OUT_LED_LINK4	45
+#define AR934X_GPIO_OUT_EXT_LNA0	46
+#define AR934X_GPIO_OUT_EXT_LNA1	47
+
+#define QCA955X_GPIO_OUT_GPIO		0
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL	0x00
+#define AR71XX_MII_REG_MII1_CTRL	0x04
+
+#define AR71XX_MII_CTRL_IF_MASK		3
+#define AR71XX_MII_CTRL_SPEED_SHIFT	4
+#define AR71XX_MII_CTRL_SPEED_MASK	3
+#define AR71XX_MII_CTRL_SPEED_10	0
+#define AR71XX_MII_CTRL_SPEED_100	1
+#define AR71XX_MII_CTRL_SPEED_1000	2
+
+#define AR71XX_MII0_CTRL_IF_GMII	0
+#define AR71XX_MII0_CTRL_IF_MII		1
+#define AR71XX_MII0_CTRL_IF_RGMII	2
+#define AR71XX_MII0_CTRL_IF_RMII	3
+
+#define AR71XX_MII1_CTRL_IF_RGMII	0
+#define AR71XX_MII1_CTRL_IF_RMII	1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG		0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
+#define AR933X_ETH_CFG_MII_GE0		BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG		0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14
+#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG		0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE		BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP		BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS		BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG	0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
+
+#endif /* __ASM_AR71XX_H */

arch/mips/mach-ath79/include/mach/ath79.h new file +143 -0

new file mode 100644
index 0000000..58c8224
@@ -0,0 +1,143 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ * Copyright (C) 2015 Wills Wang, <[email protected]>
+ * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type {
+	ATH79_SOC_UNKNOWN,
+	ATH79_SOC_AR7130,
+	ATH79_SOC_AR7141,
+	ATH79_SOC_AR7161,
+	ATH79_SOC_AR7240,
+	ATH79_SOC_AR7241,
+	ATH79_SOC_AR7242,
+	ATH79_SOC_AR9130,
+	ATH79_SOC_AR9132,
+	ATH79_SOC_AR9330,
+	ATH79_SOC_AR9331,
+	ATH79_SOC_AR9341,
+	ATH79_SOC_AR9342,
+	ATH79_SOC_AR9344,
+	ATH79_SOC_QCA9533,
+	ATH79_SOC_QCA9556,
+	ATH79_SOC_QCA9558,
+	ATH79_SOC_TP9343,
+	ATH79_SOC_QCA9561,
+};
+
+static inline int soc_is_ar71xx(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7130 ||
+		gd->arch.soc == ATH79_SOC_AR7141 ||
+		gd->arch.soc == ATH79_SOC_AR7161;
+}
+
+static inline int soc_is_ar724x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240 ||
+		gd->arch.soc == ATH79_SOC_AR7241 ||
+		gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar7240(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240;
+}
+
+static inline int soc_is_ar7241(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7241;
+}
+
+static inline int soc_is_ar7242(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar913x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9130 ||
+		gd->arch.soc == ATH79_SOC_AR9132;
+}
+
+static inline int soc_is_ar933x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9330 ||
+		gd->arch.soc == ATH79_SOC_AR9331;
+}
+
+static inline int soc_is_ar9341(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9341;
+}
+
+static inline int soc_is_ar9342(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9342;
+}
+
+static inline int soc_is_ar9344(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9344;
+}
+
+static inline int soc_is_ar934x(void)
+{
+	return soc_is_ar9341() ||
+		soc_is_ar9342() ||
+		soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+	return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+	return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+	return gd->arch.soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9561;
+}
+
+static inline int soc_is_qca956x(void)
+{
+	return soc_is_tp9343() || soc_is_qca9561();
+}
+
+#endif /* __ASM_MACH_ATH79_H */

arch/mips/mach-ath79/include/mach/ddr.h new file +14 -0

new file mode 100644
index 0000000..3a6097e
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+void ddr_init(void);
+void ddr_tap_tunning(void);
+
+#endif /* __ASM_MACH_DDR_H */

arch/mips/mach-ath79/reset.c new file +46 -0

new file mode 100644
index 0000000..c003c21
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+void _machine_restart(void)
+{
+	u32 val, reg = 0;
+
+	if (soc_is_ar71xx())
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x())
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x())
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca955x())
+		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else
+		puts("Reset register not defined for this SOC\n");
+
+	if (reg) {
+		val = readl(KSEG1ADDR(AR71XX_RESET_BASE + reg));
+		val |= AR71XX_RESET_FULL_CHIP;
+		writel(val, KSEG1ADDR(AR71XX_RESET_BASE + reg));
+	}
+
+	while (1)
+		/* NOP */;
+}

arch/mips/include/asm/global_data.h +6 -0

index 2d9a0c9..3799e98 100644
@@ -20,6 +20,12 @@ struct arch_global_data {
  	unsigned long tbl;
  	unsigned long lastinc;
  #endif
+#ifdef CONFIG_ARCH_ATH79
+	unsigned long id;
+	unsigned long soc;
+	unsigned long rev;
+	unsigned long ver;
+#endif

do you really need this at this location? global_data is only intended for variables needed before and after relocation and should be kept as small as possible. You can always read SoC info values directly from the hardware registers if you need them. There is no value in caching those infos in global_data.

arch/mips/mach-ath79/ar933x/board.c new file +42 -0

new file mode 100644
index 0000000..b4a76e8
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uart_pin_init(void)
+{
+	u32 val;
+
+	/*
+	 * Set GPIO10 (UART_SO) as output and enable UART,
+	 * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+	 */
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+	val |= BIT(10);
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE));
+
+	val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+	val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+	writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC));
+}
+
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	uart_pin_init();
+	ddr_init();
+	return 0;
+}
+#endif

the content of this file should be moved to your board directory. As Marek already mentioned, PIN setup is board-specific. Probably not all AR933x based boards need to setup that UART pin.

Quoted 16 lines

arch/mips/mach-ath79/ar933x/clk.c new file +10 -0

new file mode 100644
index 0000000..cfc4bb9
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>

arch/mips/mach-ath79/ar933x/clk.c line 20

Quoted 10 lines

arch/mips/mach-ath79/ar933x/clk.c new file +10 -0

+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+	u32 val;
+
+	val = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR933X_RESET_REG_BOOTSTRAP));

now that you have implemented map_phymem(), you should always use it.

const void __iomem *regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, MAP_NOCACHE);
...
val = readl(regs + AR933X_RESET_REG_BOOTSTRAP);

I'm going to sync asm/io.h and others with the kernel. Thus your current code would not compile without warnings any more. Please fix all locations in your code.

Apart from this you read the bootstrap settings in several places. You could create something like <mach/reset.h> and add a function like this

static inline u32 ar933x_get_bootstrap(void)

{
     const void __iomem *regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, MAP_NOCACHE);

     return readl(regs + AR933X_RESET_REG_BOOTSTRAP);
}

Quoted 10 lines

arch/mips/mach-ath79/ar933x/clk.c new file +10 -0

+	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return ar933x_get_xtal();
+}

arch/mips/mach-ath79/ar933x/clk.c line 37

Quoted 7 lines

arch/mips/mach-ath79/ar933x/clk.c new file +7 -0

+
+int get_clocks(void)
+{
+	u32 val, xtal, pll, div;
+
+	xtal = ar933x_get_xtal();
+	val = readl(KSEG1ADDR(AR71XX_PLL_BASE + AR933X_PLL_CPU_CONFIG_REG));

readl(regs + ...) as mentioned above

Quoted 10 lines

arch/mips/mach-ath79/ar933x/clk.c new file +10 -0

+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> AR933X_PLL_CPU_CONFIG_DIVINT_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_DIVINT_MASK;
+	pll *= div;

arch/mips/mach-ath79/ar933x/clk.c line 54

Quoted 7 lines

arch/mips/mach-ath79/ar933x/clk.c new file +7 -0

+	div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	val = readl(KSEG1ADDR(AR71XX_PLL_BASE + AR933X_PLL_CLOCK_CTRL_REG));

readl(regs + ...) as mentioned above

arch/mips/mach-ath79/ar933x/ddr.c new file +18 -0

new file mode 100644
index 0000000..3985299
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ddr_init(void)
+{
+	void __iomem *regs = (void *)KSEG1ADDR(AR71XX_DDR_CTRL_BASE);

map_physmem()

arch/mips/mach-ath79/ar933x/clk.c line 58

Quoted 4 lines

arch/mips/mach-ath79/ar933x/clk.c new file +4 -0

+	u32 val;
+
+	writel(0x7fbc8cd0, regs + AR71XX_DDR_REG_CONFIG);
+	writel(0x9dd0e6a8, regs + AR71XX_DDR_REG_CONFIG2);

do not use magic values. These should be defined somewhere with descriptive names.

arch/mips/mach-ath79/ar933x/clk.c line 61

Quoted 3 lines

arch/mips/mach-ath79/ar933x/clk.c new file +3 -0

+
+	val = readl(KSEG1ADDR(AR71XX_RESET_BASE) +
+			AR933X_RESET_REG_BOOTSTRAP);

use the suggested ar933x_get_bootstrap() function

arch/mips/mach-ath79/ar933x/ddr.c new file +2 -0

+
+void ddr_tap_tunning(void)

do you mean ddr_tap_tuning() ?

arch/mips/mach-ath79/ar933x/clk.c line 63

Quoted 3 lines

arch/mips/mach-ath79/ar933x/clk.c new file +2 -0

+{
+	void __iomem *regs = (void *)KSEG1ADDR(AR71XX_DDR_CTRL_BASE);

map_physmem()

arch/mips/mach-ath79/cpu.c new file +18 -0

new file mode 100644
index 0000000..c03480d
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	char *chip = "????";

const char *chip

arch/mips/mach-ath79/dram.c new file +16 -0

new file mode 100644
index 0000000..dbd56d2
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/addrspace.h>
+#include <mach/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+	ddr_tap_tunning();
+	return get_ram_size((void *)KSEG1, SZ_256M);

is that information available in memory controller registers?

+DECLARE_GLOBAL_DATA_PTR;

drivers/serial/serial_ar933x.c new file +5 -0

+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+	return 0;

drivers/serial/serial_ar933x.c new file +4 -0

+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+			    AR933X_UART_DATA_REG);

Hi Wills,

Quoted 1 line · Wills Wang

+DECLARE_GLOBAL_DATA_PTR;

The gd is not used in this patch. It can be removed.

drivers/serial/serial_ar933x.c line 125

Quoted 8 lines

drivers/serial/serial_ar933x.c new file +7 -0

+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+    u32 data;
+
 
+    do {
+        data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_TX_CSR));

    data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
    if (!(data & AR933X_UART_DATA_TX_CSR))
        return -EAGAIN;

Quoted 5 lines

drivers/serial/serial_ar933x.c new file +5 -0

+
+    data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+    ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+    return 0;

drivers/serial/serial_ar933x.c line 139

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +9 -0

+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+    u32 data;
+
 
+    do {
+        data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_RX_CSR));

    data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
    if (!(data & AR933X_UART_DATA_RX_CSR))
        return -EAGAIN;

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+
+    data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+    ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+                AR933X_UART_DATA_REG);

drivers/serial/serial_ar933x.c line 163

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +9 -0

+    return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
 
+static int ar933x_serial_probe(struct udevice *dev)
+{
+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    u32 val;
+
+    fdt_addr_t addr;

Why extra blank line above "fdt_addr_t addr;"?

=========================

checkpatch.pl,

WARNING: Missing a blank line after declarations
#206: FILE: drivers/serial/serial_ar933x.c:45:

drivers/serial/serial_ar933x.c new file +2 -0

+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    return readl(priv->regs + offset);

CHECK: Alignment should match open parenthesis
#210: FILE: drivers/serial/serial_ar933x.c:49:

drivers/serial/serial_ar933x.c new file +2 -0

+static inline void ar933x_serial_write(struct udevice *dev,
+                    u32 val, u32 offset)

WARNING: Missing a blank line after declarations
#213: FILE: drivers/serial/serial_ar933x.c:52:

(quoted diff) +2 -0

+    struct ar933x_serial_priv *priv = dev_get_priv(dev);
+    writel(val, priv->regs + offset);

CHECK: Alignment should match open parenthesis
#234: FILE: drivers/serial/serial_ar933x.c:73:

drivers/serial/serial_ar933x.c new file +2 -0

+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+                       u32 *scale, u32 *step)

CHECK: Please don't use multiple blank lines
#393: FILE: drivers/serial/serial_ar933x.c:232:

(quoted diff) +2 -0

+
+

Thanks.

Regards,
Thomas