ARM: OMAP4: hwmod clkctrl conversion to DT + clock driver
Subsystems (8)
cover ARM: OMAP4: hwmod clkctrl conversion to DT + clock driver
Hi,
This series adds support for hwmod gate clock type, and changes OMAP4 as an example to use the new clock type, converting the existing hwmod_data clkctrl definitions to clock nodes under device tree. Some additional magic is required for handling timer clocks, as the clock driver assumes it can do mux operations on the hwmod main clock, the mux-mod clock type variants are for this purpose.
The data files have been automatically converted by scripting, so doing the same conversion for any AMxyz / OMAP4+ SoC should be relatively easy to do.
Boot tested on OMAP4 panda ES board, also tried that suspend-resume / cpuidle works fine. Testing done on top of 4.4-rc3.
This series is one part of the work to get rid of hwmod data from kernel.
-Tero
RFC 1/9 ARM: OMAP2+: omap_device: create clock alias purely from DT data
This avoids the need to add most of the clock aliases under drivers/clk/ti/clk-xyz.c files.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/omap_device.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/mach-omap2/omap_device.c +12 -0
@@ -62,6 +62,18 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,return ; } + r =clk_get_sys (NULL , clk_name); + +if (IS_ERR (r) &&of_have_populated_dt ()) { +struct of_phandle_args clkspec; + + clkspec.np =of_find_node_by_name (NULL , clk_name); + + r =of_clk_get_from_provider (&clkspec); + +clk_register_clkdev (r, clk_name,NULL ); + } + rc =clk_add_alias (clk_alias,dev_name (&od->pdev->dev), clk_name,NULL );if (rc) {if (rc == -ENODEV || rc == -ENOMEM )
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerRFC 1/9 ARM: OMAP2+: omap_device: create clock alias purely from DT data
Quoted 2 lines · Tero Kristo
This avoids the need to add most of the clock aliases under
drivers/clk/ti/clk-xyz.cfiles.
Yup is badly needed. Right now we have strange hidden dependencies in multiple subsystems to enable a single device driver:
1. Add a clock alias for a device
2. Add hwmod entries for a device
3. Add dts entries for a device
4. Add a device driver
We really should only need steps 3 and 4 to do that, hopefully this takes out #1 on the list above.
Regards,
Tony
RFC 2/9 ARM: OMAP2+: hwmod: initialize main clocks directly from DT
In reply to Tero KristoThis avoids the need to add clock aliases under drivers/clk/ti/clk-xyz.c files.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/omap_hwmod.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +14 -5
@@ -786,11 +786,20 @@ static int _init_main_clk(struct omap_hwmod *oh)if (!oh->main_clk)return 0 ; - oh->_clk =clk_get (NULL , oh->main_clk); -if (IS_ERR (oh->_clk)) { -pr_warn ("omap_hwmod: %s: cannot clk_get main_clk %s\n" , - oh->name, oh->main_clk); -return -EINVAL ; +if (of_have_populated_dt ()) { +struct of_phandle_args clkspec; + + clkspec.np =of_find_node_by_name (NULL , oh->main_clk); + oh->_clk =of_clk_get_from_provider (&clkspec); + } + +if (!oh->_clk) { + oh->_clk =clk_get (NULL , oh->main_clk); +if (IS_ERR (oh->_clk)) { +pr_warn ("omap_hwmod: %s: cannot clk_get main_clk %s\n" , + oh->name, oh->main_clk); +return -EINVAL ; + } }/* * HACK: This needs a re-visit once clk_prepare() is implemented
Signature · 1 line
1.7.9.5
RFC 3/9 clk: ti: remove un-used definitions from public clk_hw_omap struct
In reply to Tero KristoClksel support has been deprecated a while back, so remove these from the struct also.
Signed-off-by Tero Kristo <[email protected]>
--- include/linux/clk/ti.h | 4 ---- 1 file changed, 4 deletions(-)
include/linux/clk/ti.h +0 -4
@@ -127,8 +127,6 @@ struct clk_hw_omap_ops {* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) * @flags: see "struct clk.flags possibilities" above * @clksel_reg: for clksel clks, register va containing src/divisor select -* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector -* @clksel: for clksel clks, pointer to struct clksel for this clock * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock * @clkdm_name: clockdomain name that this clock is contained in * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
@@ -143,8 +141,6 @@ struct clk_hw_omap {u8 enable_bit;u8 flags;void __iomem *clksel_reg; -u32 clksel_mask; -const struct clksel *clksel;struct dpll_data *dpll_data;const char *clkdm_name;struct clockdomain *clkdm;
Signature · 1 line
1.7.9.5
RFC 4/9 clk: ti: mux: export mux clock APIs locally
In reply to Tero Kristoget_parent and set_parent are going to be required by the support of module clocks, so export these locally.
Signed-off-by Tero Kristo <[email protected]>
--- drivers/clk/ti/clock.h | 3 +++ drivers/clk/ti/mux.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-)
drivers/clk/ti/clock.h +3 -0
@@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;extern const struct clk_ops ti_clk_divider_ops;extern const struct clk_ops ti_clk_mux_ops; +u8 ti_clk_mux_get_parent (struct clk_hw *hw); +int ti_clk_mux_set_parent (struct clk_hw *hw,u8 index); +int omap2_clkops_enable_clkdm (struct clk_hw *hw);void omap2_clkops_disable_clkdm (struct clk_hw *hw);
drivers/clk/ti/mux.c +2 -2
@@ -28,7 +28,7 @@#define to_clk_mux (_hw) container_of(_hw, struct clk_mux, hw) -static u8 ti_clk_mux_get_parent (struct clk_hw *hw) +u8 ti_clk_mux_get_parent (struct clk_hw *hw) {struct clk_mux *mux =to_clk_mux (hw);int num_parents =clk_hw_get_num_parents (hw);
@@ -65,7 +65,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)return val; } -static int ti_clk_mux_set_parent (struct clk_hw *hw,u8 index) +int ti_clk_mux_set_parent (struct clk_hw *hw,u8 index) {struct clk_mux *mux =to_clk_mux (hw);u32 val;
Signature · 1 line
1.7.9.5
RFC 5/9 dt-bindings: clk: ti: Document module clock type
In reply to Tero KristoDocument the new TI module clock type, which is intended to replace the internal clock control handling within omap_hwmod. Module clock is effectively a gate clock controlling both interface and functional clocks for a single hardware IP block.
Signed-off-by Tero Kristo <[email protected]>
--- .../devicetree/bindings/clock/ti/module.txt | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/module.txt
Documentation/devicetree/bindings/clock/ti/module.txt new file +57 -0
@@ -0,0 +1,57 @@ +Binding for Texas Instruments module clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. This clock is +quite much similar to the basic gate-clock [2], however, internally +it controls an OMAP module clock, which effectively handles +both interface and functional clocks for a single module. In some +cases, support for mux clock [3] is composited to the same clock node, +currently only needed for proper support of timer module clocks. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/gate.txt +[3] Documentation/devicetree/bindings/clock/ti/mux.txt + +Required properties: +- compatible : shall be one of: + "ti,omap4-mod-clock" - basic module clock, no gating supported + "ti,omap4-hw-mod-clock" - module clock with hardware gating support + "ti,omap4-sw-mod-clock" - module clock with software forced gating support + "ti,omap4-mux-mod-clock" - composite clock with mux and module clocks, no + gating supported + "ti,omap4-hw-mux-mod-clock" - composite clock with mux and module clocks, + with hardware gating + "ti,omap4-sw-mux-mod-clock" - composite clock with mux and module clocks, + with software forced gating + +- #clock-cells : from common clock binding; shall be set to 0 +- clocks : link to phandle of parent clock(s) +- reg : offset for register controlling adjustable gate and optional mux + +Optional properties: +- ti,bit-shift : bit shift for programming the clock mux, only needed for + the nodes of the mux variant + +Examples: + timer6_mod_ck: timer6_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0570>; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + i2c1_mod_ck: i2c1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14a0>; + clocks = <&func_96m_fclk>; + }; + + hsi_mod_ck: hsi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1338>; + clocks = <&hsi_fck>; + };
Signature · 1 line
1.7.9.5
RFC 6/9 clk: ti: add support for omap4 module clocks
In reply to Tero KristoPreviously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT.
Signed-off-by Tero Kristo <[email protected]>
--- drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/clkt_mod.c | 351 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 + 3 files changed, 355 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clkt_mod.c
drivers/clk/ti/Makefile +2 -1
@@ -1,7 +1,8 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ - clkt_dpll.o clkt_iclk.o clkt_dflt.o + clkt_dpll.o clkt_iclk.o clkt_dflt.o \ + clkt_mod.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
drivers/clk/ti/clkt_mod.c new file +351 -0
351 lines not on this page · raw message
include/linux/clk/ti.h +2 -0
@@ -127,6 +127,7 @@ struct clk_hw_omap_ops {* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) * @flags: see "struct clk.flags possibilities" above * @clksel_reg: for clksel clks, register va containing src/divisor select +* @mux: for module clocks, pointer to the optional mux component * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock * @clkdm_name: clockdomain name that this clock is contained in * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
@@ -141,6 +142,7 @@ struct clk_hw_omap {u8 enable_bit;u8 flags;void __iomem *clksel_reg; +struct clk_hw *mux;struct dpll_data *dpll_data;const char *clkdm_name;struct clockdomain *clkdm;
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerRFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 9 lines · Tero Kristo
Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmod clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT.
Good to see this happening, few comments on what I've noticed so far that should be considered.
We should be able to do a generic "ti,mux-div-gate" clock and use it for the clkctrl too I think. See the suggested binding elsewhere in this thread. That would also work for the clkout register at least. Maybe the "ti,mux-div-gate" clock needs a separate clkctrl type compatible to know it needs to sleep to wait for the status bit.
Also, we already know these clkctrl register do have multiple clocks, like the GPIO debounce and dividers for debugss clock. And we want to get rid of the overlapping reg entries.
Quoted 31 lines
drivers/clk/ti/clkt_mod.c new file +31
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable (clk->clkdm, hw->clk); +if (ret) { +WARN (1 , +"%s: could not enable %s's clockdomain %s: %d\n" , + __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } + + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; + + ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );
drivers/clk/ti/clkt_mod.c line 107
Quoted 10 lines
drivers/clk/ti/clkt_mod.c new file +10
-0+ timeout++; +if (timeout >OMAP4_MAX_MODULE_READY_TIME ) { +pr_err ("%s: failed to enable\n" ,clk_hw_get_name (hw)); +return -EBUSY ; + } + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + } + +return 0 ; +}
Clocks that need to wait to lock need to be set up with clk_prepare instead of clk_enable as pointed out by TGLX recently. Also see the "[PATCH] clk: ti: Fix FAPLL udelay in clk_enable with clk_prepare".
Not sure what all needs to be fixed in the hwmod code for that to happen and PM to work, but that probably needs to be done first.
Regards,
Tony
RFC 6/9 clk: ti: add support for omap4 module clocks
In reply to Tero KristoHi Tero,
Quoting Tero Kristo (2015-12-18 05:58:58)
Quoted 9 lines
Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT.
I'm really happy to see this series. Looks pretty good to me.
Quoted 21 lines
drivers/clk/ti/clkt_mod.c new file +21
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable (clk->clkdm, hw->clk); +if (ret) { +WARN (1 , +"%s: could not enable %s's clockdomain %s: %d\n" , + __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } +
drivers/clk/ti/clkt_mod.c line 97
Quoted 10 lines
drivers/clk/ti/clkt_mod.c new file +10
-0+ val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; + + ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );
This should really be a .prepare callback if you plan to keep the delays in there.
Regards,
Mike
RFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 41 lines · Michael Turquette
Hi Tero,
Quoting Tero Kristo (2015-12-18 05:58:58)
Quoted 9 lines
Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT.
I'm really happy to see this series. Looks pretty good to me.
Quoted 26 lines
drivers/clk/ti/clkt_mod.c new file +26
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable (clk->clkdm, hw->clk); +if (ret) { +WARN (1 , +"%s: could not enable %s's clockdomain %s: %d\n" , + __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } + + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; +
Quoted 8 lines
drivers/clk/ti/clkt_mod.c line 97
Quoted 5 lines
drivers/clk/ti/clkt_mod.c new file +5
-0+ ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );This should really be a .prepare callback if you plan to keep the delays in there.
If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time. hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is:
device driver -> pm_runtime -> hwmod_core -> hwmod_clk_enable / disable.
The delay within this function should usually be pretty short, just to wait that the module comes up from idle.
I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then? Typically clk_enable/disable just becomes a NOP if it is not allowed to wait for hardware to complete transitioning before exiting the function.
-Tero
Quoted 4 lines
Regards,
Mike
RFC 6/9 clk: ti: add support for omap4 module clocks
Hi Tero,
Quoted 45 lines · Tero Kristo
Quoted 29 lines · Michael Turquette
Quoting Tero Kristo (2015-12-18 05:58:58)
Quoted 28 lines
drivers/clk/ti/clkt_mod.c new file +12
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm,
hw->clk);drivers/clk/ti/clkt_mod.c new file +3
-0+if (ret) { + WARN(1, + "%s: could not enable %s's clockdomain %s:%d\n",
drivers/clk/ti/clkt_mod.c new file +11
-0+ __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } + + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; +Quoted 8 lines
drivers/clk/ti/clkt_mod.c line 97
Quoted 5 lines
drivers/clk/ti/clkt_mod.c new file +5
-0+ ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );This should really be a .prepare callback if you plan to keep the delays in there.
If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time. hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is:
Quoted 4 lines
device driver ->
pm_runtime->hwmod_core->hwmod_clk_enable/ disable.The delay within this function should usually be pretty short, just to wait that the module comes up from idle.
Does it take multiple ?s? Perhaps even one ?s is much longer than needed?
Quoted 4 lines
I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then? Typically clk_enable/disable just becomes a NOP if it is not allowed to wait for hardware to complete transitioning before exiting the function.
FWIW, there are small loops with just a cpu_relax() in various clock drivers under drivers/clk/shmobile/.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 55 lines · Geert Uytterhoeven
Hi Tero,
Quoted 45 lines · Tero Kristo
Quoted 29 lines · Michael Turquette
Quoting Tero Kristo (2015-12-18 05:58:58)
Quoted 28 lines
drivers/clk/ti/clkt_mod.c new file +12
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm,
hw->clk);drivers/clk/ti/clkt_mod.c new file +3
-0+if (ret) { + WARN(1, + "%s: could not enable %s's clockdomain %s:%d\n",
drivers/clk/ti/clkt_mod.c new file +11
-0+ __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } + + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; +Quoted 8 lines
drivers/clk/ti/clkt_mod.c line 97
Quoted 5 lines
drivers/clk/ti/clkt_mod.c new file +5
-0+ ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );This should really be a .prepare callback if you plan to keep the delays in there.
If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time. hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is:
Quoted 4 lines
device driver ->
pm_runtime->hwmod_core->hwmod_clk_enable/ disable.The delay within this function should usually be pretty short, just to wait that the module comes up from idle.
Does it take multiple ?s? Perhaps even one ?s is much longer than needed?
Quoted 7 lines
Quoted 4 lines
I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then? Typically clk_enable/disable just becomes a NOP if it is not allowed to wait for hardware to complete transitioning before exiting the function.
FWIW, there are small loops with just a
cpu_relax()in various clock drivers underdrivers/clk/shmobile/.
Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding cpu_relax instead looks like a good change. I just verified that changing the udelay to cpu_relax works fine also, I just need to change the bail-out period to be something sane.
-Tero
Quoted 12 lines
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.orgIn personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 9 lines · Tero Kristo
Quoted 2 lines · Geert Uytterhoeven
FWIW, there are small loops with just a
cpu_relax()in various clock drivers underdrivers/clk/shmobile/.Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding
cpu_relaxinstead looks like a good change. I just verified that changing the udelay tocpu_relaxworks fine also, I just need to change the bail-out period to be something sane.
Was that profiling done with lockdep/lock debugging enabled or disabled?
Signature · 3 lines
RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
Tony Lindgren
maintainerRFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines · Tero Kristo
Quoted 2 lines · Geert Uytterhoeven
FWIW, there are small loops with just a
cpu_relax()in various clock drivers underdrivers/clk/shmobile/.
Quoted 7 lines
Quoted 5 lines
Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding
cpu_relaxinstead looks like a good change. I just verified that changing the udelay tocpu_relaxworks fine also, I just need to change the bail-out period to be something sane.Was that profiling done with lockdep/lock debugging enabled or disabled?
And also the thing to check from the hw folks is what all do these clkctrl bits really control. If they group together the OCP clock and an extra functional clock for some devices the delays could be larger.
In general, I think we need to get rid of pm_runtime_irq_safe usage to allow clocks to sleep properly. The other option is to allow toggling pm_runtime_irq_safe but that probably gets super messy.
Regards,
Tony
RFC 6/9 clk: ti: add support for omap4 module clocks
Quoted 6 lines · Tony Lindgren
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines · Tero Kristo
Quoted 2 lines · Geert Uytterhoeven
FWIW, there are small loops with just a
cpu_relax()in various clock drivers underdrivers/clk/shmobile/.
Quoted 7 lines
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Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding
cpu_relaxinstead looks like a good change. I just verified that changing the udelay tocpu_relaxworks fine also, I just need to change the bail-out period to be something sane.Was that profiling done with lockdep/lock debugging enabled or disabled?
omap2plus_defconfig, so lockdep was enabled. The profiling was done around the while {} block though, which should not have any locks within it (except for the SCM clocks, which may explain some of the higher latency numbers seen.)
Quoted 3 lines
And also the thing to check from the hw folks is what all do these clkctrl bits really control. If they group together the OCP clock and an extra functional clock for some devices the delays could be larger.
Does it matter really? The latencies are only imposed to the device in question, and lets face it, the same latencies are there already with the hwmod implementation. This series moves the implementation under clock driver with as less modifications as possible to avoid any problems.
Quoted 3 lines
In general, I think we need to get rid of
pm_runtime_irq_safeusage to allow clocks to sleep properly. The other option is to allow togglingpm_runtime_irq_safebut that probably gets super messy.
That is something not to be done with this set though.
-Tero
RFC 6/9 clk: ti: add support for omap4 module clocks
Quoting Tero Kristo (2016-01-04 11:15:36)
Quoted 20 lines · Tony Lindgren
Quoted 6 lines · Russell King - ARM Linux
Quoted 5 lines · Tero Kristo
Quoted 4 lines · Geert Uytterhoeven
Quoted 2 lines
FWIW, there are small loops with just a
cpu_relax()in various clock drivers underdrivers/clk/shmobile/.Quoted 7 lines
Quoted 7 lines
Quoted 5 lines
Just did a quick profiling round, and the clk_enable/disable delay loops take anything from 0...1500ns, most typically consuming some 400-600ns. So, based on this, dropping the udelay and adding
cpu_relaxinstead looks like a good change. I just verified that changing the udelay tocpu_relaxworks fine also, I just need to change the bail-out period to be something sane.Was that profiling done with lockdep/lock debugging enabled or disabled?
omap2plus_defconfig, so lockdep was enabled. The profiling was done around the while {} block though, which should not have any locks within it (except for the SCM clocks, which may explain some of the higher latency numbers seen.)
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And also the thing to check from the hw folks is what all do these clkctrl bits really control. If they group together the OCP clock and an extra functional clock for some devices the delays could be larger.
Does it matter really? The latencies are only imposed to the device in question, and lets face it, the same latencies are there already with the hwmod implementation. This series moves the implementation under clock driver with as less modifications as possible to avoid any problems.
So long as we can all convince ourselves that the flaw is not a flaw then I'm OK with it. No bugs were ever introduced that way ;-)
But in fairness, we've had these delays in the .enable callbacks for a while, so this patch does not introduce the regression. Furthermore it does clean up some code that needs more work, and I don't want to delay that.
I won't NACK the patch due to the delays, but it would be nice to revisit it some day.
Regards,
Mike
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Quoted 4 lines
In general, I think we need to get rid of
pm_runtime_irq_safeusage to allow clocks to sleep properly. The other option is to allow togglingpm_runtime_irq_safebut that probably gets super messy.That is something not to be done with this set though.
-Tero
RFC 6/9 clk: ti: add support for omap4 module clocks
In reply to Tero KristoQuoting Tero Kristo (2016-01-03 23:36:05)
Quoted 51 lines · Michael Turquette
Quoted 41 lines
Hi Tero,
Quoting Tero Kristo (2015-12-18 05:58:58)
Quoted 9 lines
Previously, hwmod core has been used for controlling the hwmod level clocks. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will be used to convert all the existing hwmdo clocks to. This helps to get rid of the clock related hwmod data from kernel and instead parsing this from DT.
I'm really happy to see this series. Looks pretty good to me.
Quoted 26 lines
drivers/clk/ti/clkt_mod.c new file +26
-0+static int _omap4_hwmod_clk_enable (struct clk_hw *hw) +{ +struct clk_hw_omap *clk =to_clk_hw_omap (hw); +u32 val; +int timeout =0 ; +int ret; + +if (!clk->enable_bit) +return 0 ; + +if (clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable (clk->clkdm, hw->clk); +if (ret) { +WARN (1 , +"%s: could not enable %s's clockdomain %s: %d\n" , + __func__,clk_hw_get_name (hw), + clk->clkdm_name, ret); +return ret; + } + } + + val = ti_clk_ll_ops->clk_readl (clk->enable_reg); + + val &= ~OMAP4_MODULEMODE_MASK ; + val |= clk->enable_bit; +Quoted 8 lines
drivers/clk/ti/clkt_mod.c line 97
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drivers/clk/ti/clkt_mod.c new file +5
-0+ ti_clk_ll_ops->clk_writel (val, clk->enable_reg); + +/* Wait until module is enabled */ +while (!_omap4_is_ready (val)) { +udelay (1 );This should really be a .prepare callback if you plan to keep the delays in there.
Quoted 2 lines
If this is changed to a .prepare, then all OMAP power management is effectively ruined as all clocks are going to be enabled all the time.
Let's not ruin system PM.
Quoted 5 lines
hwmod core doesn't support .prepare/.enable at the moment that well, and changing that is going to be a big burden (educated guess, haven't checked this yet)... The call chain that comes here is:
device driver ->
pm_runtime->hwmod_core->hwmod_clk_enable/ disable.
Right, and for calls to pm_runtime_get/put from process context it should result in a call to clk_prepare_enable/clk_disable_unprepare. I guess that change is hugely invasive from your statements above?
Quoted 6 lines
The delay within this function should usually be pretty short, just to wait that the module comes up from idle.
I recall the discussions regarding the udelays within clk_enable/disable calls, but what is the preferred approach then?
There are many cases where a clk only provides .{un}prepare ops and does NOT provide any .{en,dis}able ops.
Quoted 2 lines
Typically
clk_enable/disable just becomes a NOP
Yes, it becomes a NOP (though it is critical that drivers with knowledge of this do not try to skip the step of calling clk_enable).
Quoted 2 lines
if it is not allowed to wait for
hardware to complete transitioning before exiting the function.
The clk.h api clearly states that clk_prepare must be called and complete before calling clk_enable. So if a clk only provides a .prepare with delays but no .enable, and a consumer driver complies with that api rule then we're guaranteed to have a toggling line when clk_enable returns.
Regards,
Mike
Quoted 8 lines
-Tero
Quoted 4 lines
Regards,
Mike
RFC 7/9 ARM: dts: omap4: add hwmod module clocks
In reply to Tero KristoAdd clock nodes for the SoC hwmods. This is done in preparation to remove hwmod data from kernel, hwmod will use the clock nodes instead for module level enable / disable logic.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/omap44xx-clocks.dtsi | 854 +++++++++++++++++++++++++++++--- 1 file changed, 781 insertions(+), 73 deletions(-)
arch/arm/boot/dts/omap44xx-clocks.dtsi +781 -73
@@ -183,6 +183,20 @@ reg = <0x0528>; }; + aess_mod_ck: aess_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0528>; + clocks = <&aess_fclk>; + }; + + mcpdm_mod_ck: mcpdm_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0530>; + clocks = <&pad_clks_ck>; + }; + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { #clock-cells = <0>; compatible = "ti,divider-clock";
@@ -194,6 +208,34 @@ ti,invert-autoidle-bit; }; + mpu_mod_ck: mpu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0320>; + clocks = <&dpll_mpu_m2_ck>; + }; + + mmu_dsp_mod_ck: mmu_dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + }; + + dsp_mod_ck: dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + }; + + l4_abe_mod_ck: l4_abe_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0520>; + clocks = <&ocp_abe_iclk>; + }; + core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -480,6 +522,13 @@ reg = <0x0538>; }; + dmic_mod_ck: dmic_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0538>; + clocks = <&func_dmic_abe_gfclk>; + }; + func_dmic_abe_gfclk: func_dmic_abe_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -496,6 +545,13 @@ reg = <0x0540>; }; + mcasp_mod_ck: mcasp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0540>; + clocks = <&func_mcasp_abe_gfclk>; + }; + func_mcasp_abe_gfclk: func_mcasp_abe_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -520,6 +576,13 @@ reg = <0x0548>; }; + mcbsp1_mod_ck: mcbsp1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0548>; + clocks = <&func_mcbsp1_gfclk>; + }; + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -536,6 +599,13 @@ reg = <0x0550>; }; + mcbsp2_mod_ck: mcbsp2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0550>; + clocks = <&func_mcbsp2_gfclk>; + }; + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -552,6 +622,13 @@ reg = <0x0558>; }; + mcbsp3_mod_ck: mcbsp3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0558>; + clocks = <&func_mcbsp3_gfclk>; + }; + slimbus1_fclk_1: slimbus1_fclk_1 { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -568,52 +645,66 @@ reg = <0x0560>; }; - slimbus1_fclk_2: slimbus1_fclk_2 { + slimbus1_mod_ck: slimbus1_mod_ck { #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_ck>; - ti,bit-shift = <10>; + compatible = "ti,omap4-sw-mod-clock"; reg = <0x0560>; + clocks = <&slimbus1_fclk_0>; }; - slimbus1_slimbus_clk: slimbus1_slimbus_clk { + timer5_mod_ck: timer5_mod_ck { #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0568>; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; }; - timer5_sync_mux: timer5_sync_mux { + timer6_mod_ck: timer6_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0570>; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; - reg = <0x0568>; }; - timer6_sync_mux: timer6_sync_mux { + timer7_mod_ck: timer7_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0578>; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; - reg = <0x0570>; }; - timer7_sync_mux: timer7_sync_mux { + timer8_mod_ck: timer8_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0580>; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; - reg = <0x0578>; }; - timer8_sync_mux: timer8_sync_mux { + wd_timer3_mod_ck: wd_timer3_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0588>; + clocks = <&sys_32k_ck>; + }; + + slimbus1_fclk_2: slimbus1_fclk_2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pad_clks_ck>; + ti,bit-shift = <10>; + reg = <0x0560>; + }; + + slimbus1_slimbus_clk: slimbus1_slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&slimbus_clk>; + ti,bit-shift = <11>; + reg = <0x0560>; }; dummy_ck: dummy_ck {
@@ -622,6 +713,7 @@ clock-frequency = <0>; }; }; + &prm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>;
@@ -631,6 +723,20 @@ ti,index-starts-at-one; }; + l4_wkup_mod_ck: l4_wkup_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1820>; + clocks = <&l4_wkup_clk_mux_ck>; + }; + + wd_timer2_mod_ck: wd_timer2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1830>; + clocks = <&sys_32k_ck>; + }; + abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -677,12 +783,26 @@ reg = <0x1838>; }; - dmt1_clk_mux: dmt1_clk_mux { + gpio1_mod_ck: gpio1_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1838>; + clocks = <&l4_wkup_clk_mux_ck>; + }; + + timer1_mod_ck: timer1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1840>; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; - reg = <0x1840>; + }; + + counter_32k_mod_ck: counter_32k_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1850>; + clocks = <&sys_32k_ck>; }; usim_ck: usim_ck {
@@ -694,6 +814,13 @@ ti,dividers = <14>, <18>; }; + kbd_mod_ck: kbd_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1878>; + clocks = <&sys_32k_ck>; + }; + usim_fclk: usim_fclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -737,6 +864,13 @@ ti,dividers = <0>, <1>, <2>, <0>, <4>; }; + debugss_mod_ck: debugss_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1a20>; + clocks = <&trace_clk_div_ck>; + }; + trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock";
@@ -747,7 +881,14 @@ &prm_clockdomains { emu_sys_clkdm: emu_sys_clkdm { compatible = "ti,clockdomain"; - clocks = <&trace_clk_div_ck>; + clocks = <&debugss_mod_ck>, <&trace_clk_div_ck>; + }; + + l4_wkup_clkdm: l4_wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&timer1_mod_ck>, <&l4_wkup_mod_ck>, <&gpio1_mod_ck>, + <&wd_timer2_mod_ck>, <&counter_32k_mod_ck>, + <&kbd_mod_ck>; }; };
@@ -993,6 +1134,55 @@ reg = <0x1120>; }; + dss_venc_mod_ck: dss_venc_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_tv_clk>; + }; + + dss_dispc_mod_ck: dss_dispc_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_dss_clk>; + }; + + dss_dsi1_mod_ck: dss_dsi1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_dss_clk>; + }; + + dss_dsi2_mod_ck: dss_dsi2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_dss_clk>; + }; + + dss_core_mod_ck: dss_core_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1120>; + clocks = <&dss_dss_clk>; + }; + + dss_rfbi_mod_ck: dss_rfbi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_dss_clk>; + }; + + dss_hdmi_mod_ck: dss_hdmi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1120>; + clocks = <&dss_48mhz_clk>; + }; + dss_tv_clk: dss_tv_clk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1028,6 +1218,13 @@ ti,index-power-of-two; }; + fdif_mod_ck: fdif_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1028>; + clocks = <&fdif_fck>; + }; + gpio2_dbclk: gpio2_dbclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1036,6 +1233,13 @@ reg = <0x1460>; }; + gpio2_mod_ck: gpio2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1460>; + clocks = <&l4_div_ck>; + }; + gpio3_dbclk: gpio3_dbclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1044,6 +1248,13 @@ reg = <0x1468>; }; + gpio3_mod_ck: gpio3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1468>; + clocks = <&l4_div_ck>; + }; + gpio4_dbclk: gpio4_dbclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1052,6 +1263,13 @@ reg = <0x1470>; }; + gpio4_mod_ck: gpio4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1470>; + clocks = <&l4_div_ck>; + }; + gpio5_dbclk: gpio5_dbclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1060,6 +1278,13 @@ reg = <0x1478>; }; + gpio5_mod_ck: gpio5_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1478>; + clocks = <&l4_div_ck>; + }; + gpio6_dbclk: gpio6_dbclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1068,6 +1293,55 @@ reg = <0x1480>; }; + gpio6_mod_ck: gpio6_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1480>; + clocks = <&l4_div_ck>; + }; + + hdq1w_mod_ck: hdq1w_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1488>; + clocks = <&func_12m_fclk>; + }; + + i2c1_mod_ck: i2c1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14a0>; + clocks = <&func_96m_fclk>; + }; + + i2c2_mod_ck: i2c2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14a8>; + clocks = <&func_96m_fclk>; + }; + + i2c3_mod_ck: i2c3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14b0>; + clocks = <&func_96m_fclk>; + }; + + i2c4_mod_ck: i2c4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14b8>; + clocks = <&func_96m_fclk>; + }; + + l4_per_mod_ck: l4_per_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x14c0>; + clocks = <&l4_div_ck>; + }; + sgx_clk_mux: sgx_clk_mux { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1076,6 +1350,13 @@ reg = <0x1220>; }; + gpu_mod_ck: gpu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1220>; + clocks = <&sgx_clk_mux>; + }; + hsi_fck: hsi_fck { #clock-cells = <0>; compatible = "ti,divider-clock";
@@ -1086,6 +1367,13 @@ ti,index-power-of-two; }; + hsi_mod_ck: hsi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1338>; + clocks = <&hsi_fck>; + }; + iss_ctrlclk: iss_ctrlclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1094,6 +1382,13 @@ reg = <0x1020>; }; + iss_mod_ck: iss_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1020>; + clocks = <&ducati_clk_mux_ck>; + }; + mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1102,6 +1397,55 @@ reg = <0x14e0>; }; + mcbsp4_mod_ck: mcbsp4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14e0>; + clocks = <&per_mcbsp4_gfclk>; + }; + + mcspi1_mod_ck: mcspi1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14f0>; + clocks = <&func_48m_fclk>; + }; + + mcspi2_mod_ck: mcspi2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14f8>; + clocks = <&func_48m_fclk>; + }; + + mcspi3_mod_ck: mcspi3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1500>; + clocks = <&func_48m_fclk>; + }; + + mcspi4_mod_ck: mcspi4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1508>; + clocks = <&func_48m_fclk>; + }; + + mmc3_mod_ck: mmc3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1520>; + clocks = <&func_48m_fclk>; + }; + + mmc4_mod_ck: mmc4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1528>; + clocks = <&func_48m_fclk>; + }; + per_mcbsp4_gfclk: per_mcbsp4_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1118,6 +1462,13 @@ reg = <0x1328>; }; + mmc1_mod_ck: mmc1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1328>; + clocks = <&hsmmc1_fclk>; + }; + hsmmc2_fclk: hsmmc2_fclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1126,6 +1477,13 @@ reg = <0x1330>; }; + mmc2_mod_ck: mmc2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1330>; + clocks = <&hsmmc2_fclk>; + }; + ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1134,6 +1492,68 @@ reg = <0x13e0>; }; + ocp2scp_usb_phy_mod_ck: ocp2scp_usb_phy_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x13e0>; + clocks = <&ocp2scp_usb_phy_phy_48m>; + }; + + timer10_mod_ck: timer10_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1428>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + timer11_mod_ck: timer11_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1430>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + timer2_mod_ck: timer2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1438>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + timer3_mod_ck: timer3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1440>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + timer4_mod_ck: timer4_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1448>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + timer9_mod_ck: timer9_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x1450>; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + elm_mod_ck: elm_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x1458>; + clocks = <&l4_div_ck>; + }; + sha2md5_fck: sha2md5_fck { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1166,76 +1586,91 @@ reg = <0x1538>; }; - smartreflex_core_fck: smartreflex_core_fck { + slimbus2_mod_ck: slimbus2_mod_ck { #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0638>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1538>; + clocks = <&slimbus2_fclk_0>; }; - smartreflex_iva_fck: smartreflex_iva_fck { + uart1_mod_ck: uart1_mod_ck { #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0630>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1540>; + clocks = <&func_48m_fclk>; }; - smartreflex_mpu_fck: smartreflex_mpu_fck { + uart2_mod_ck: uart2_mod_ck { #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0628>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1548>; + clocks = <&func_48m_fclk>; }; - cm2_dm10_mux: cm2_dm10_mux { + uart3_mod_ck: uart3_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1428>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1550>; + clocks = <&func_48m_fclk>; }; - cm2_dm11_mux: cm2_dm11_mux { + uart4_mod_ck: uart4_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1430>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1558>; + clocks = <&func_48m_fclk>; }; - cm2_dm2_mux: cm2_dm2_mux { + mmc5_mod_ck: mmc5_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1438>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1560>; + clocks = <&func_48m_fclk>; }; - cm2_dm3_mux: cm2_dm3_mux { + smartreflex_core_fck: smartreflex_core_fck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1440>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0638>; }; - cm2_dm4_mux: cm2_dm4_mux { + smartreflex_core_mod_ck: smartreflex_core_mod_ck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1448>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0638>; + clocks = <&smartreflex_core_fck>; }; - cm2_dm9_mux: cm2_dm9_mux { + smartreflex_iva_fck: smartreflex_iva_fck { #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1450>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0630>; + }; + + smartreflex_iva_mod_ck: smartreflex_iva_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0630>; + clocks = <&smartreflex_iva_fck>; + }; + + smartreflex_mpu_fck: smartreflex_mpu_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0628>; + }; + + smartreflex_mpu_mod_ck: smartreflex_mpu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x0628>; + clocks = <&smartreflex_mpu_fck>; }; usb_host_fs_fck: usb_host_fs_fck {
@@ -1246,6 +1681,13 @@ reg = <0x13d0>; }; + usb_host_fs_mod_ck: usb_host_fs_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x13d0>; + clocks = <&usb_host_fs_fck>; + }; + utmi_p1_gfclk: utmi_p1_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1262,6 +1704,13 @@ reg = <0x1358>; }; + usb_host_hs_mod_ck: usb_host_hs_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x1358>; + clocks = <&usb_host_hs_fck>; + }; + utmi_p2_gfclk: utmi_p2_gfclk { #clock-cells = <0>; compatible = "ti,mux-clock";
@@ -1342,6 +1791,13 @@ reg = <0x1360>; }; + usb_otg_hs_mod_ck: usb_otg_hs_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1360>; + clocks = <&usb_otg_hs_ick>; + }; + usb_otg_hs_xclk: usb_otg_hs_xclk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1366,6 +1822,139 @@ reg = <0x0640>; }; + l3_main_1_mod_ck: l3_main_1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0720>; + clocks = <&l3_div_ck>; + }; + + l3_main_2_mod_ck: l3_main_2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0820>; + clocks = <&l3_div_ck>; + }; + + gpmc_mod_ck: gpmc_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0828>; + clocks = <&l3_div_ck>; + }; + + ocmc_ram_mod_ck: ocmc_ram_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0830>; + clocks = <&l3_div_ck>; + }; + + ipu_mod_ck: ipu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0920>; + clocks = <&ducati_clk_mux_ck>; + }; + + mmu_ipu_mod_ck: mmu_ipu_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0920>; + clocks = <&ducati_clk_mux_ck>; + }; + + dma_system_mod_ck: dma_system_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0a20>; + clocks = <&l3_div_ck>; + }; + + dmm_mod_ck: dmm_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0b20>; + clocks = <&l3_div_ck>; + }; + + emif1_mod_ck: emif1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0b30>; + clocks = <&ddrphy_ck>; + }; + + emif2_mod_ck: emif2_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0b38>; + clocks = <&ddrphy_ck>; + }; + + c2c_mod_ck: c2c_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0c20>; + clocks = <&div_core_ck>; + }; + + l4_cfg_mod_ck: l4_cfg_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0d20>; + clocks = <&l4_div_ck>; + }; + + spinlock_mod_ck: spinlock_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0d28>; + clocks = <&l4_div_ck>; + }; + + mailbox_mod_ck: mailbox_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-mod-clock"; + reg = <0x0d30>; + clocks = <&l4_div_ck>; + }; + + l3_main_3_mod_ck: l3_main_3_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0e20>; + clocks = <&l3_div_ck>; + }; + + l3_instr_mod_ck: l3_instr_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0e28>; + clocks = <&l3_div_ck>; + }; + + ocp_wp_noc_mod_ck: ocp_wp_noc_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0e40>; + clocks = <&l3_div_ck>; + }; + + iva_mod_ck: iva_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0f20>; + clocks = <&dpll_iva_m5x2_ck>; + }; + + sl2if_mod_ck: sl2if_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0f28>; + clocks = <&dpll_iva_m5x2_ck>; + }; + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { #clock-cells = <0>; compatible = "ti,gate-clock";
@@ -1397,12 +1986,110 @@ ti,bit-shift = <0>; reg = <0x1368>; }; + + usb_tll_hs_mod_ck: usb_tll_hs_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1368>; + clocks = <&usb_tll_hs_ick>; + }; }; &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>; + clocks = <&mmc2_mod_ck>, <&usb_otg_hs_mod_ck>, + <&usb_host_fs_mod_ck>, <&usb_tll_hs_mod_ck>, + <&usb_host_hs_mod_ck>, <&mmc1_mod_ck>, <&hsi_mod_ck>, + <&ocp2scp_usb_phy_mod_ck>, <&dpll_usb_ck>, + <&usb_host_fs_fck>; + }; + + l3_gfx_clkdm: l3_gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpu_mod_ck>; + }; + + l4_per_clkdm: l4_per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&l4_per_mod_ck>, <&uart2_mod_ck>, <&uart1_mod_ck>, + <&timer10_mod_ck>, <&gpio2_mod_ck>, <&mcspi3_mod_ck>, + <&uart4_mod_ck>, <&gpio5_mod_ck>, <&hdq1w_mod_ck>, + <&mcbsp4_mod_ck>, <&i2c1_mod_ck>, <&i2c3_mod_ck>, + <&mcspi2_mod_ck>, <&timer9_mod_ck>, <&i2c4_mod_ck>, + <&timer2_mod_ck>, <&timer4_mod_ck>, <&mcspi4_mod_ck>, + <&timer11_mod_ck>, <&mcspi1_mod_ck>, <&timer3_mod_ck>, + <&mmc3_mod_ck>, <&mmc5_mod_ck>, <&gpio4_mod_ck>, + <&gpio6_mod_ck>, <&uart3_mod_ck>, <&slimbus2_mod_ck>, + <&gpio3_mod_ck>, <&i2c2_mod_ck>, <&mmc4_mod_ck>, + <&elm_mod_ck>; + }; + + ivahd_clkdm: ivahd_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sl2if_mod_ck>, <&iva_mod_ck>; + }; + + l4_cfg_clkdm: l4_cfg_clkdm { + compatible = "ti,clockdomain"; + clocks = <&spinlock_mod_ck>, <&mailbox_mod_ck>, + <&l4_cfg_mod_ck>; + }; + + l3_instr_clkdm: l3_instr_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ocp_wp_noc_mod_ck>, <&l3_main_3_mod_ck>, + <&l3_instr_mod_ck>; + }; + + iss_clkdm: iss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&fdif_mod_ck>, <&iss_mod_ck>; + }; + + l3_emif_clkdm: l3_emif_clkdm { + compatible = "ti,clockdomain"; + clocks = <&emif2_mod_ck>, <&emif1_mod_ck>, <&dmm_mod_ck>; + }; + + ducati_clkdm: ducati_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ipu_mod_ck>, <&mmu_ipu_mod_ck>; + }; + + l3_dma_clkdm: l3_dma_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dma_system_mod_ck>; + }; + + l3_2_clkdm: l3_2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpmc_mod_ck>, <&l3_main_2_mod_ck>, + <&ocmc_ram_mod_ck>; + }; + + l3_dss_clkdm: l3_dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_venc_mod_ck>, <&dss_hdmi_mod_ck>, + <&dss_dsi2_mod_ck>, <&dss_core_mod_ck>, + <&dss_dsi1_mod_ck>, <&dss_rfbi_mod_ck>, + <&dss_dispc_mod_ck>; + }; + + l4_ao_clkdm: l4_ao_clkdm { + compatible = "ti,clockdomain"; + clocks = <&smartreflex_core_mod_ck>, <&smartreflex_mpu_mod_ck>, + <&smartreflex_iva_mod_ck>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&c2c_mod_ck>; + }; + + l3_1_clkdm: l3_1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&l3_main_1_mod_ck>; }; };
@@ -1641,3 +2328,24 @@ reg = <0x0224>; }; }; + +&cm1_clockdomains { + mpuss_clkdm: mpuss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mpu_mod_ck>; + }; + + tesla_clkdm: tesla_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmu_dsp_mod_ck>, <&dsp_mod_ck>; + }; + + abe_clkdm: abe_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mcpdm_mod_ck>, <&l4_abe_mod_ck>, <&wd_timer3_mod_ck>, + <&timer7_mod_ck>, <&timer5_mod_ck>, <&mcbsp3_mod_ck>, + <&mcbsp2_mod_ck>, <&timer6_mod_ck>, <&mcbsp1_mod_ck>, + <&timer8_mod_ck>, <&mcasp_mod_ck>, <&dmic_mod_ck>, + <&aess_mod_ck>, <&slimbus1_mod_ck>; + }; +};
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerRFC 7/9 ARM: dts: omap4: add hwmod module clocks
arch/arm/boot/dts/omap44xx-clocks.dtsi line 230
Quoted 13 lines · Tero Kristo
arch/arm/boot/dts/omap44xx-clocks.dtsi +13
-0+ mmu_dsp_mod_ck: mmu_dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + }; + + dsp_mod_ck: dsp_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x0420>; + clocks = <&dpll_iva_m4x2_ck>; + };
In general we should get rid of the overlapping reg entries for clocks. That's a separate patch series for sure.. But I think it can be done simply with something like this probably for all of them (totally untested):
mux_div_gate_ck: clk at 420 {
#clock-cells = <1>;
compatible = "ti,mux-divider-gate";
clock-indices = <0>, <1>;
clock-output-names = "mux", "div", "gate";
reg = <0x420 0x4>;
foo_mux_ck: clock at 0 {
reg = <0>;
compatible = "ti,mux-clock";
};
foo_div_ck: clock at 8 {
reg = <8>;
compatible = "ti,divider-clock";
ti,max-div = <31>;
};
foo_gate_ck: clock at 16 {
reg = <16>;
compatible = "ti,gate-clock";
clocks = <&mux_source_ck>;
};
};Then the output can be referenced with the standard clock binding index. For example to use the mux clock:
clocks = <&mux_div_gate_ck 0>;
Regards,
Tony
RFC 8/9 ARM: OMAP4: hwmod_data: use module clocks from DT
In reply to Tero KristoReplace the usage of prcm->clkstctrl with main_clk:s provided via DT. This is done in preparation to get rid of hwmod data from kernel.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 339 ++++++++-------------------- 1 file changed, 95 insertions(+), 244 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +95 -244
@@ -67,10 +67,10 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { .clkdm_name = "l3_emif_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, + .main_clk = "dmm_mod_ck", };/*
@@ -88,11 +88,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "l3_instr_mod_ck", };/* l3_main_1 */
@@ -102,10 +101,10 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .clkdm_name = "l3_1_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, }, }, + .main_clk = "l3_main_1_mod_ck", };/* l3_main_2 */
@@ -115,10 +114,10 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .clkdm_name = "l3_2_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, }, }, + .main_clk = "l3_main_2_mod_ck", };/* l3_main_3 */
@@ -128,11 +127,10 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "l3_main_3_mod_ck", };/*
@@ -150,12 +148,12 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .clkdm_name = "abe_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, }, }, + .main_clk = "l4_abe_mod_ck", };/* l4_cfg */
@@ -165,10 +163,10 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .clkdm_name = "l4_cfg_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, }, }, + .main_clk = "l4_cfg_mod_ck", };/* l4_per */
@@ -178,10 +176,10 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { .clkdm_name = "l4_per_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, }, }, + .main_clk = "l4_per_mod_ck", };/* l4_wkup */
@@ -191,10 +189,10 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .clkdm_name = "l4_wkup_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, }, }, + .main_clk = "l4_wkup_mod_ck", };/*
@@ -232,11 +230,10 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { .clkdm_name = "l3_instr_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "ocp_wp_noc_mod_ck", };/*
@@ -276,13 +273,11 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "aess_fclk", + .main_clk = "aess_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -304,10 +299,10 @@ static struct omap_hwmod omap44xx_c2c_hwmod = { .clkdm_name = "d2d_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, }, }, + .main_clk = "c2c_mod_ck", };/*
@@ -334,10 +329,9 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { .class = &omap44xx_counter_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "sys_32k_ck", + .main_clk = "counter_32k_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, }, },
@@ -425,10 +419,9 @@ static struct omap_hwmod omap44xx_debugss_hwmod = { .name = "debugss", .class = &omap44xx_debugss_hwmod_class, .clkdm_name = "emu_sys_clkdm", - .main_clk = "trace_clk_div_ck", + .main_clk = "debugss_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, }, },
@@ -480,10 +473,9 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { .clkdm_name = "l3_dma_clkdm", .mpu_irqs = omap44xx_dma_system_irqs, .xlate_irq = omap4_xlate_irq, - .main_clk = "l3_div_ck", + .main_clk = "dma_system_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, }, },
@@ -515,12 +507,10 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "func_dmic_abe_gfclk", + .main_clk = "dmic_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -545,13 +535,11 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .clkdm_name = "tesla_clkdm", .rst_lines = omap44xx_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), - .main_clk = "dpll_iva_m4x2_ck", + .main_clk = "dsp_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -585,12 +573,10 @@ static struct omap_hwmod omap44xx_dss_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap44xx_dss_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_dss_clk", + .main_clk = "dss_core_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = dss_opt_clks,
@@ -643,10 +629,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .mpu_irqs = omap44xx_dss_dispc_irqs, .xlate_irq = omap4_xlate_irq, .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, - .main_clk = "dss_dss_clk", + .main_clk = "dss_dispc_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -697,10 +682,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .mpu_irqs = omap44xx_dss_dsi1_irqs, .xlate_irq = omap4_xlate_irq, .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, - .main_clk = "dss_dss_clk", + .main_clk = "dss_dsi1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -731,10 +715,9 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .mpu_irqs = omap44xx_dss_dsi2_irqs, .xlate_irq = omap4_xlate_irq, .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, - .main_clk = "dss_dss_clk", + .main_clk = "dss_dsi2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -790,10 +773,9 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .mpu_irqs = omap44xx_dss_hdmi_irqs, .xlate_irq = omap4_xlate_irq, .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, - .main_clk = "dss_48mhz_clk", + .main_clk = "dss_hdmi_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -837,10 +819,9 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .class = &omap44xx_rfbi_hwmod_class, .clkdm_name = "l3_dss_clkdm", .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, - .main_clk = "dss_dss_clk", + .main_clk = "dss_rfbi_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -863,10 +844,9 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_tv_clk", + .main_clk = "dss_venc_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, },
@@ -901,10 +881,10 @@ static struct omap_hwmod omap44xx_elm_hwmod = { .clkdm_name = "l4_per_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, }, }, + .main_clk = "elm_mod_ck", };/*
@@ -927,12 +907,10 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "ddrphy_ck", + .main_clk = "emif1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -943,12 +921,10 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "ddrphy_ck", + .main_clk = "emif2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -987,12 +963,10 @@ static struct omap_hwmod omap44xx_fdif_hwmod = { .name = "fdif", .class = &omap44xx_fdif_hwmod_class, .clkdm_name = "iss_clkdm", - .main_clk = "fdif_fck", + .main_clk = "fdif_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1035,12 +1009,10 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .name = "gpio1", .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .main_clk = "l4_wkup_clk_mux_ck", + .main_clk = "gpio1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio1_opt_clks,
@@ -1058,12 +1030,10 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4_div_ck", + .main_clk = "gpio2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio2_opt_clks,
@@ -1081,12 +1051,10 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4_div_ck", + .main_clk = "gpio3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio3_opt_clks,
@@ -1104,12 +1072,10 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4_div_ck", + .main_clk = "gpio4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio4_opt_clks,
@@ -1127,12 +1093,10 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4_div_ck", + .main_clk = "gpio5_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio5_opt_clks,
@@ -1150,12 +1114,10 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4_div_ck", + .main_clk = "gpio6_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = gpio6_opt_clks,
@@ -1192,11 +1154,10 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "gpmc_mod_ck", };/*
@@ -1224,12 +1185,10 @@ static struct omap_hwmod omap44xx_gpu_hwmod = { .name = "gpu", .class = &omap44xx_gpu_hwmod_class, .clkdm_name = "l3_gfx_clkdm", - .main_clk = "sgx_clk_mux", + .main_clk = "gpu_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1259,12 +1218,10 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = { .class = &omap44xx_hdq1w_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ - .main_clk = "func_12m_fclk", + .main_clk = "hdq1w_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1298,12 +1255,10 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "hsi_fck", + .main_clk = "hsi_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -1342,12 +1297,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "func_96m_fclk", + .main_clk = "i2c1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &i2c_dev_attr,
@@ -1359,12 +1312,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "func_96m_fclk", + .main_clk = "i2c2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &i2c_dev_attr,
@@ -1376,12 +1327,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "func_96m_fclk", + .main_clk = "i2c3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &i2c_dev_attr,
@@ -1393,12 +1342,10 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "func_96m_fclk", + .main_clk = "i2c4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &i2c_dev_attr,
@@ -1425,13 +1372,11 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .clkdm_name = "ducati_clkdm", .rst_lines = omap44xx_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), - .main_clk = "ducati_clk_mux_ck", + .main_clk = "ipu_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -1475,12 +1420,10 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .name = "iss", .class = &omap44xx_iss_hwmod_class, .clkdm_name = "iss_clkdm", - .main_clk = "ducati_clk_mux_ck", + .main_clk = "iss_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = iss_opt_clks,
@@ -1509,13 +1452,11 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .clkdm_name = "ivahd_clkdm", .rst_lines = omap44xx_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), - .main_clk = "dpll_iva_m5x2_ck", + .main_clk = "iva_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -1547,12 +1488,10 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .main_clk = "sys_32k_ck", + .main_clk = "kbd_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1584,10 +1523,10 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { .clkdm_name = "l4_cfg_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, }, }, + .main_clk = "mailbox_mod_ck", };/*
@@ -1618,12 +1557,10 @@ static struct omap_hwmod omap44xx_mcasp_hwmod = { .name = "mcasp", .class = &omap44xx_mcasp_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "func_mcasp_abe_gfclk", + .main_clk = "mcasp_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1657,12 +1594,10 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "func_mcbsp1_gfclk", + .main_clk = "mcbsp1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = mcbsp1_opt_clks,
@@ -1679,12 +1614,10 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "func_mcbsp2_gfclk", + .main_clk = "mcbsp2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = mcbsp2_opt_clks,
@@ -1701,12 +1634,10 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "func_mcbsp3_gfclk", + .main_clk = "mcbsp3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = mcbsp3_opt_clks,
@@ -1723,12 +1654,10 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "l4_per_clkdm", - .main_clk = "per_mcbsp4_gfclk", + .main_clk = "mcbsp4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .opt_clks = mcbsp4_opt_clks,
@@ -1773,12 +1702,10 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {* results 'slow motion' audio playback. */ .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, - .main_clk = "pad_clks_ck", + .main_clk = "mcpdm_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -1828,12 +1755,10 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mcspi1_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mcspi1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &mcspi1_dev_attr,
@@ -1858,12 +1783,10 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mcspi2_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mcspi2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &mcspi2_dev_attr,
@@ -1888,12 +1811,10 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mcspi3_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mcspi3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &mcspi3_dev_attr,
@@ -1916,12 +1837,10 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mcspi4_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mcspi4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &mcspi4_dev_attr,
@@ -1966,12 +1885,10 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", .sdma_reqs = omap44xx_mmc1_sdma_reqs, - .main_clk = "hsmmc1_fclk", + .main_clk = "mmc1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &mmc1_dev_attr,
@@ -1989,12 +1906,10 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", .sdma_reqs = omap44xx_mmc2_sdma_reqs, - .main_clk = "hsmmc2_fclk", + .main_clk = "mmc2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2011,12 +1926,10 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mmc3_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mmc3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2033,12 +1946,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mmc4_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mmc4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2055,12 +1966,10 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .sdma_reqs = omap44xx_mmc5_sdma_reqs, - .main_clk = "func_48m_fclk", + .main_clk = "mmc5_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2121,13 +2030,11 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { .clkdm_name = "ducati_clkdm", .rst_lines = omap44xx_mmu_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), - .main_clk = "ducati_clk_mux_ck", + .main_clk = "mmu_ipu_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs =OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .dev_attr = &mmu_ipu_dev_attr,
@@ -2168,13 +2075,11 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { .clkdm_name = "tesla_clkdm", .rst_lines = omap44xx_mmu_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), - .main_clk = "dpll_iva_m4x2_ck", + .main_clk = "mmu_dsp_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs =OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .dev_attr = &mmu_dsp_dev_attr,
@@ -2195,10 +2100,9 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .class = &omap44xx_mpu_hwmod_class, .clkdm_name = "mpuss_clkdm", .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_mpu_m2_ck", + .main_clk = "mpu_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, }, },
@@ -2220,10 +2124,10 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { .clkdm_name = "l3_2_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, }, }, + .main_clk = "ocmc_ram_mod_ck", };/*
@@ -2262,12 +2166,10 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {* So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems * to be the best workaround. */ - .main_clk = "ocp2scp_usb_phy_phy_48m", + .main_clk = "ocp2scp_usb_phy_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -2369,11 +2271,10 @@ static struct omap_hwmod omap44xx_sl2if_hwmod = { .clkdm_name = "ivahd_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, + .main_clk = "sl2if_mod_ck", };/*
@@ -2411,13 +2312,12 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = { .clkdm_name = "abe_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, .opt_clks = slimbus1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), + .main_clk = "slimbus1_mod_ck", };/* slimbus2 */
@@ -2433,13 +2333,12 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = { .clkdm_name = "l4_per_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, .opt_clks = slimbus2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), + .main_clk = "slimbus2_mod_ck", };/*
@@ -2478,12 +2377,10 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .main_clk = "smartreflex_core_fck", + .main_clk = "smartreflex_core_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &smartreflex_core_dev_attr,
@@ -2498,12 +2395,10 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .name = "smartreflex_iva", .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .main_clk = "smartreflex_iva_fck", + .main_clk = "smartreflex_iva_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &smartreflex_iva_dev_attr,
@@ -2518,12 +2413,10 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .main_clk = "smartreflex_mpu_fck", + .main_clk = "smartreflex_mpu_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &smartreflex_mpu_dev_attr,
@@ -2558,10 +2451,10 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { .clkdm_name = "l4_cfg_clkdm", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, }, }, + .main_clk = "spinlock_mod_ck", };/*
@@ -2629,12 +2522,10 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "dmt1_clk_mux", + .main_clk = "timer1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_alwon_dev_attr,
@@ -2646,12 +2537,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "cm2_dm2_mux", + .main_clk = "timer2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2661,12 +2550,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm3_mux", + .main_clk = "timer3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2676,12 +2563,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm4_mux", + .main_clk = "timer4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2691,12 +2576,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .name = "timer5", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "timer5_sync_mux", + .main_clk = "timer5_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_dsp_dev_attr,
@@ -2707,12 +2590,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "timer6_sync_mux", + .main_clk = "timer6_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_dsp_dev_attr,
@@ -2723,12 +2604,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "timer7_sync_mux", + .main_clk = "timer7_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_dsp_dev_attr,
@@ -2739,12 +2618,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "timer8_sync_mux", + .main_clk = "timer8_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_dsp_pwm_dev_attr,
@@ -2755,12 +2632,10 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm9_mux", + .main_clk = "timer9_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_pwm_dev_attr,
@@ -2772,12 +2647,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "cm2_dm10_mux", + .main_clk = "timer10_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET , - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_pwm_dev_attr,
@@ -2788,12 +2661,10 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .main_clk = "cm2_dm11_mux", + .main_clk = "timer11_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, - .modulemode =MODULEMODE_SWCTRL , }, }, .dev_attr = &capability_pwm_dev_attr,
@@ -2827,12 +2698,10 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "func_48m_fclk", + .main_clk = "uart1_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2843,12 +2712,10 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "func_48m_fclk", + .main_clk = "uart2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2859,12 +2726,10 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "func_48m_fclk", + .main_clk = "uart3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2875,12 +2740,10 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "func_48m_fclk", + .main_clk = "uart4_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2917,12 +2780,10 @@ static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { .name = "usb_host_fs", .class = &omap44xx_usb_host_fs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_fs_fck", + .main_clk = "usb_host_fs_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -2954,12 +2815,10 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { .name = "usb_host_hs", .class = &omap44xx_usb_host_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", + .main_clk = "usb_host_hs_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, },
@@ -3037,12 +2896,10 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { .class = &omap44xx_usb_otg_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .main_clk = "usb_otg_hs_ick", + .main_clk = "usb_otg_hs_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, .context_offs =OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET , - .modulemode =MODULEMODE_HWCTRL , }, }, .opt_clks = usb_otg_hs_opt_clks,
@@ -3074,12 +2931,10 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { .name = "usb_tll_hs", .class = &omap44xx_usb_tll_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_tll_hs_ick", + .main_clk = "usb_tll_hs_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };
@@ -3113,12 +2968,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .main_clk = "sys_32k_ck", + .main_clk = "wd_timer2_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
@@ -3128,12 +2981,10 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .name = "wd_timer3", .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .main_clk = "sys_32k_ck", + .main_clk = "wd_timer3_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, }, }, };
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerRFC 8/9 ARM: OMAP4: hwmod_data: use module clocks from DT
Quoted 2 lines · Tero Kristo
Replace the usage of
prcm->clkstctrlwith main_clk:s provided via DT. This is done in preparation to get rid of hwmod data from kernel.
...
Quoted 4 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0
-0@@ -334,10 +329,9 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { .class = &omap44xx_counter_hwmod_class,
arch/arm/mach-omap2/omap_hwmod_44xx_data.c static struct omap_hwmod omap44xx_counter_32k_hwmod = { · line 337
Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +1
-2.clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "sys_32k_ck", + .main_clk = "counter_32k_mod_ck", .prcm = { .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, }, },
Care to describe why the main_clk now needs to be modified or added? Can that too come from dts now?
Regards,
Tony
RFC 9/9 clk: ti: omap4: update clock aliases to reflect new module clocks
In reply to Tero KristoThe clock data in DT has been updated, and the clock aliases must be updated to match.
Signed-off-by Tero Kristo <[email protected]>
--- drivers/clk/ti/clk-44xx.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)
drivers/clk/ti/clk-44xx.c +11 -11
@@ -164,17 +164,17 @@ static struct ti_dt_clk omap44xx_clks[] = {DT_CLK (NULL ,"smartreflex_core_fck" ,"smartreflex_core_fck" ),DT_CLK (NULL ,"smartreflex_iva_fck" ,"smartreflex_iva_fck" ),DT_CLK (NULL ,"smartreflex_mpu_fck" ,"smartreflex_mpu_fck" ), -DT_CLK (NULL ,"dmt1_clk_mux" ,"dmt1_clk_mux" ), -DT_CLK (NULL ,"cm2_dm10_mux" ,"cm2_dm10_mux" ), -DT_CLK (NULL ,"cm2_dm11_mux" ,"cm2_dm11_mux" ), -DT_CLK (NULL ,"cm2_dm2_mux" ,"cm2_dm2_mux" ), -DT_CLK (NULL ,"cm2_dm3_mux" ,"cm2_dm3_mux" ), -DT_CLK (NULL ,"cm2_dm4_mux" ,"cm2_dm4_mux" ), -DT_CLK (NULL ,"timer5_sync_mux" ,"timer5_sync_mux" ), -DT_CLK (NULL ,"timer6_sync_mux" ,"timer6_sync_mux" ), -DT_CLK (NULL ,"timer7_sync_mux" ,"timer7_sync_mux" ), -DT_CLK (NULL ,"timer8_sync_mux" ,"timer8_sync_mux" ), -DT_CLK (NULL ,"cm2_dm9_mux" ,"cm2_dm9_mux" ), +DT_CLK (NULL ,"timer1_mod_ck" ,"timer1_mod_ck" ), +DT_CLK (NULL ,"timer10_mod_ck" ,"timer10_mod_ck" ), +DT_CLK (NULL ,"timer11_mod_ck" ,"timer11_mod_ck" ), +DT_CLK (NULL ,"timer2_mod_ck" ,"timer2_mod_ck" ), +DT_CLK (NULL ,"timer3_mod_ck" ,"timer3_mod_ck" ), +DT_CLK (NULL ,"timer4_mod_ck" ,"timer4_mod_ck" ), +DT_CLK (NULL ,"timer5_mod_ck" ,"timer5_mod_ck" ), +DT_CLK (NULL ,"timer6_mod_ck" ,"timer6_mod_ck" ), +DT_CLK (NULL ,"timer7_mod_ck" ,"timer7_mod_ck" ), +DT_CLK (NULL ,"timer8_mod_ck" ,"timer8_mod_ck" ), +DT_CLK (NULL ,"timer9_mod_ck" ,"timer9_mod_ck" ),DT_CLK (NULL ,"usb_host_fs_fck" ,"usb_host_fs_fck" ),DT_CLK ("usbhs_omap" ,"fs_fck" ,"usb_host_fs_fck" ), DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
Signature · 1 line
1.7.9.5