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mx6cuboxi: Fix the delay for the AR8035 PHY

PATCH Superseded Fabio Estevam 3 participants 14 messages Jan 4, 2016

v1 of 2 Superseded Latest is v2 →

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Fabio Estevam

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#0 lore raw

PATCH 1/2 mx6cuboxi: Fix the delay for the AR8035 PHY

From: Fabio Estevam <[email protected]>

As per the AR8035 datasheet:

"For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied."

So do as suggested and keep the reset low for 10ms.

Signed-off-by Fabio Estevam <[email protected]>
---
 board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
board/solidrun/mx6cuboxi/mx6cuboxi.c +1 -1
index fc37f1e..20faffc 100644
@@ -143,7 +143,7 @@ static void setup_iomux_enet(void)
 	SETUP_IOMUX_PADS(enet_pads);
 
 	gpio_direction_output(ETH_PHY_RESET, 0);
-	mdelay(2);
+	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
 }
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

From: Fabio Estevam <[email protected]>

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional:

Booting from net ...
FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4

This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization.

Configure the AR8035 PHY in the same manner as done in mx6sabresd and wandboard, so that we can get a reliable Ethernet operation.

Signed-off-by Fabio Estevam <[email protected]>
---
 board/solidrun/mx6cuboxi/mx6cuboxi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
board/solidrun/mx6cuboxi/mx6cuboxi.c +25 -0
index 20faffc..3bb7573 100644
@@ -147,8 +147,33 @@ static void setup_iomux_enet(void)
 	gpio_set_value(ETH_PHY_RESET, 1);
 }
 
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
+	mx6_rgmii_rework(phydev);
+
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
Signature · 1 line
1.9.1
#2 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 12 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional:

Booting from net ...
FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4

Quoted 7 lines

This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization.

Configure the AR8035 PHY in the same manner as done in mx6sabresd and wandboard, so that we can get a reliable Ethernet operation.

Signed-off-by Fabio Estevam <[email protected]>

Note:

CPU:   Freescale i.MX6D rev1.5 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 14C
Reset cause: POR
Board: MX6 Hummingboard

...
=> setenv autoload no
=> dhcp
FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
DHCP client bound to address 192.168.0.219 (7901 ms)
=> tftp ramdisk-pm.gz
Using FEC device
TFTP from server 192.168.0.3; our IP address is 192.168.0.219 Filename 'ramdisk-pm.gz'.
Load address: 0x12000000
Loading: #################################################################

	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ######
	 1.4 MiB/s

done
Bytes transferred = 2022580 (1edcb4 hex)
=> crc32 $loadaddr $filesize
CRC32 for 12000000 ... 121edcb3 ==> 775dd44d
=>

CRC32 matches:

$ rhash -C /tftpboot/ramdisk-pm.gz
; Generated by RHash v1.2.8 on 2016-01-04 at 12:04.37
; Written by Aleksey (Akademgorodok) - http://rhash.sourceforge.net/
;
;      2022580  13:41.29 2013-06-25 /tftpboot/ramdisk-pm.gz
/tftpboot/ramdisk-pm.gz 775DD44D
Tested-by Tom Rini <[email protected]>
Signature · 8 lines
Tom
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#3 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

In reply to Fabio Estevam
Quoted 33 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional:

Booting from net ...
FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4

This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization.

Configure the AR8035 PHY in the same manner as done in mx6sabresd and wandboard, so that we can get a reliable Ethernet operation.

Signed-off-by Fabio Estevam <[email protected]>
---
 board/solidrun/mx6cuboxi/mx6cuboxi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
board/solidrun/mx6cuboxi/mx6cuboxi.c +2 -0
index 20faffc..3bb7573 100644
@@ -147,8 +147,33 @@ static void setup_iomux_enet(void)
 	gpio_set_value(ETH_PHY_RESET, 1);
 }
 
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{

board/solidrun/mx6cuboxi/mx6cuboxi.c static void setup_iomux_enet(void) · line 161

Quoted 10 lines
board/solidrun/mx6cuboxi/mx6cuboxi.c +10 -0
+	unsigned short val;
+
+	/* Enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;

Except for clearing bit 2 (which is undocumented), this looks just like the default implementation, which you are still calling below.

So, it looks like this subroutine can be replaced with an appropriate delay. If bit 2 does matter, perhaps the default ar8035_config should be changed instead.

Quoted 9 lines
board/solidrun/mx6cuboxi/mx6cuboxi.c +8 -0
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+

board/solidrun/mx6cuboxi/mx6cuboxi.c static void setup_iomux_enet(void) · line 179

Quoted 10 lines
board/solidrun/mx6cuboxi/mx6cuboxi.c +5 -0
+	return 0;
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
+	mx6_rgmii_rework(phydev);
+
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);

As a test perhaps you can call config twice instead of mx6_rgmii_rework

 if (phydev->drv->config) {
	phydev->drv->config(phydev);
	phydev->drv->config(phydev);

}

author
#4 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Hi Troy,

Quoted 5 lines · Troy Kisky

Except for clearing bit 2 (which is undocumented), this looks just like the default implementation, which you are still calling below.

So, it looks like this subroutine can be replaced with an appropriate delay. If bit 2 does matter, perhaps the default ar8035_config should be changed instead.

Just realized that ar8035_config() is never called in my case, so doing:

int board_phy_config(struct phy_device *phydev)

{
    mx6_rgmii_rework(phydev);

    return 0;
}

, is enough here.

Any idea as to why ar8035_config() is never called?

#5 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 20 lines · Fabio Estevam

Hi Troy,

Quoted 5 lines · Troy Kisky

Except for clearing bit 2 (which is undocumented), this looks just like the default implementation, which you are still calling below.

So, it looks like this subroutine can be replaced with an appropriate delay. If bit 2 does matter, perhaps the default ar8035_config should be changed instead.

Just realized that ar8035_config() is never called in my case, so doing:

int board_phy_config(struct phy_device *phydev)

{
    mx6_rgmii_rework(phydev);

    return 0;
}
Quoted 4 lines

, is enough here.

Any idea as to why ar8035_config() is never called?

=> mii read 6 2
004D
=> mii read 6 3
D072
=>

Do you get a different value?

author
#6 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 7 lines · Troy Kisky

=> mii read 6 2
004D
=> mii read 6 3
D072
=>

Do you get a different value?

Yes, I get all FFFF:

=> mii read 6 3
FFFF
=> mii read 6 2
FFFF

author
#7 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 9 lines · Fabio Estevam
Quoted 6 lines · Troy Kisky

=> mii read 6 2
004D
=> mii read 6 3
D072
=>

Quoted 8 lines
Quoted 1 line

Do you get a different value?

Yes, I get all FFFF:

=> mii read 6 3
FFFF
=> mii read 6 2
FFFF

Ops, in my case the PHY address is 0.

By adjust the address I get the same values as you reported:

=> mii read 0 2
004D
=> mii read 0 3
D072

#8 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 19 lines · Fabio Estevam
Quoted 9 lines · Fabio Estevam
Quoted 6 lines · Troy Kisky

=> mii read 6 2
004D
=> mii read 6 3
D072
=>

Quoted 8 lines
Quoted 1 line

Do you get a different value?

Yes, I get all FFFF:

=> mii read 6 3
FFFF
=> mii read 6 2
FFFF

Quoted 9 lines

Ops, in my case the PHY address is 0.

By adjust the address I get the same values as you reported:

=> mii read 0 2
004D
=> mii read 0 3
D072

Can you add

printf("%s at %d\n", phydev->drv->name, phydev->addr);

author
#9 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 3 lines · Troy Kisky

Can you add

printf("%s at %d\n", phydev->drv->name, phydev->addr);

It prints:

Generic PHY at 0

Not sure why it picks the Generic PHY driver instead of the Atheros PHY one.

#10 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 5 lines · Fabio Estevam
Quoted 2 lines · Troy Kisky

Can you add

Quoted 8 lines
Quoted 1 line

printf("%s at %d\n", phydev->drv->name, phydev->addr);

It prints:

Generic PHY at 0

Not sure why it picks the Generic PHY driver instead of the Atheros PHY one.

Try adding a delay after releasing reset

        mdelay(2);
        gpio_set_value(ETH_PHY_RESET, 1);
	udelay(100);

Perhaps the first time it didn't read 4dd072

author
#11 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

Quoted 7 lines · Troy Kisky

Try adding a delay after releasing reset

        mdelay(2);
        gpio_set_value(ETH_PHY_RESET, 1);
        udelay(100);

Perhaps the first time it didn't read 4dd072

That works :-)

Here is a minimal fix:

board/solidrun/mx6cuboxi/mx6cuboxi.c +2 -1
@@ -143,8 +143,9 @@ static void setup_iomux_enet(void)
     SETUP_IOMUX_PADS(enet_pads);
 
     gpio_direction_output(ETH_PHY_RESET, 0);
-    mdelay(2);
+    mdelay(10);
     gpio_set_value(ETH_PHY_RESET, 1);
+    udelay(100);
 }

Will send a formal patch shortly.

Thanks for your help, Troy!

#12 lore raw

PATCH 2/2 mx6cuboxi: Make Ethernet functional

In reply to Fabio Estevam
Quoted 11 lines · Fabio Estevam
Quoted 7 lines · Troy Kisky

=> mii read 6 2
004D
=> mii read 6 3
D072
=>

Do you get a different value?

Quoted 8 lines

Yes, I get all FFFF:

=> mii read 6 3
FFFF
=> mii read 6 2
FFFF
.

Sorry, your phy is not at 6, you can either print it out, or try 0 to 7

#13 lore raw

PATCH 1/2 mx6cuboxi: Fix the delay for the AR8035 PHY

In reply to Fabio Estevam
Quoted 11 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

As per the AR8035 datasheet:

"For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied."

So do as suggested and keep the reset low for 10ms.

Signed-off-by Fabio Estevam <[email protected]>
Tested-by Tom Rini <[email protected]>
Signature · 8 lines
Tom
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