Skip to contentSkip to conversation

amd64_edac: shift wrapping issue in f1x_get_norm_dct_addr()

PATCH In review Dan Carpenter 3 participants 3 messages Jan 20, 2016 – Jan 21, 2016

Subsystems (3)
Kernel janitors EDAC-core EDAC-AMD64
lore
Share & tools
lore

Dan Carpenter

author
#0 lore raw

PATCH 1/1 amd64_edac: shift wrapping issue in f1x_get_norm_dct_addr()

dct_sel_base_off is declared as a u64 but we're only using the lower 32 bits because of a shift wrapping bug.

Fixes c8e518d5673d ('amd64_edac: Sanitize f10_get_base_addr_offset')
Signed-off-by Dan Carpenter <[email protected]>

---
Static checker stuff. Not tested.

drivers/edac/amd64_edac.c +1 -1
index 9eee13e..d87a475 100644
@@ -1452,7 +1452,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
 	u64 chan_off;
 	u64 dram_base		= get_dram_base(pvt, range);
 	u64 hole_off		= f10_dhar_offset(pvt);
-	u64 dct_sel_base_off	= (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
+	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
 
 	if (hi_rng) {
 		/*
maintainer
#1 lore raw
Quoted 13 lines · Dan Carpenter

dct_sel_base_off is declared as a u64 but we're only using the lower 32 bits because of a shift wrapping bug.

Fixes c8e518d5673d ('amd64_edac: Sanitize f10_get_base_addr_offset')
Signed-off-by Dan Carpenter <[email protected]>

---
Static checker stuff. Not tested.

drivers/edac/amd64_edac.c +0 -0
index 9eee13e..d87a475 100644

drivers/edac/amd64_edac.c static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, · line 1455

Quoted 5 lines
drivers/edac/amd64_edac.c +1 -1
@@ -1452,7 +1452,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
 	u64 chan_off;
 	u64 dram_base		= get_dram_base(pvt, range);
 	u64 hole_off		= f10_dhar_offset(pvt);
-	u64 dct_sel_base_off	= (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
+	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;

Good catch.

So this could possibly give us the wrong channel address and thus not find the CS row. Hmm, so on my boxes, DctSelBaseOffset[47:26] is not big enough so that its high 16-bits are 0 and truncation doesn't hurt there.

@Aravind: do you have a box with

setpci -s 18.2 0x114.l

bits [31:16] not 0?

If so, you might want to run with and without this fix above as it should fix system address to CS row mapping.

Anyway, applied and tagged for stable.

Thanks.

Signature · 4 lines
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
#2 lore raw
Quoted 12 lines · Borislav Petkov

drivers/edac/amd64_edac.c static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, · line 1455

Quoted 1 line · Dan Carpenter
drivers/edac/amd64_edac.c +1 -0
+	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;

@Aravind: do you have a box with

setpci -s 18.2 0x114.l

bits [31:16] not 0?

Nope. I don't see it set on my Fam10h and Fam15h Model 00-0fh systems.

But yes, nice catch!

-Aravind.