rockchip: Add support for cros_ec keyboard

index 1e5584a..f5def35 100644
@@ -299,9 +299,11 @@ int device_probe_child(struct udevice *dev, void *parent_priv)
 
 	/*
 	 * Process pinctrl for everything except the root device, and
-	 * continue regardless of the result of pinctrl.
+	 * continue regardless of the result of pinctrl. Don't process pinctrl
+	 * settings for pinctrl devices since the device may not yet be
+	 * probed.
 	 */
-	if (dev->parent)
+	if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
 		pinctrl_select_state(dev, "default");
 
 	ret = uclass_pre_probe_device(dev);

index c42b312..1acbfaf 100644
@@ -15,6 +15,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int pinctrl_decode_pin_config(const void *blob, int node)
+{
+	int flags = 0;
+
+	if (fdtdec_get_bool(blob, node, "bias-pull-up"))
+		flags |= 1 << PIN_CONFIG_BIAS_PULL_UP;
+	else if (fdtdec_get_bool(blob, node, "bias-pull-down"))
+		flags |= 1 << PIN_CONFIG_BIAS_PULL_DOWN;
+
+	return flags;
+}
+
 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
 /**
  * pinctrl_config_one() - apply pinctrl settings for a single node

index f6025f6..5cd4503 100644
@@ -284,4 +284,17 @@ int pinctrl_request_noflags(struct udevice *dev, int func);
  */
 int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
 
+/**
+ * pinctrl_decode_pin_config() - decode pin configuration flags
+ *
+ * This decodes some of the PIN_CONFIG values into flags, with each value
+ * being (1 << pin_cfg). This does not support things with values like the
+ * slew rate.
+ *
+ * @blob:	Device tree blob
+ * @node:	Node containing the PIN_CONFIG values
+ * @return decoded flag value, or -ve on error
+ */
+int pinctrl_decode_pin_config(const void *blob, int node);
+
 #endif /* __PINCTRL_H */

index 793f08e..bfea6e0 100644
@@ -180,18 +180,13 @@ static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return CMD_RET_SUCCESS;
 }
 
-static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static void do_status_detail(struct udevice *dev,
+			     struct dm_regulator_uclass_platdata *uc_pdata)
 {
-	struct dm_regulator_uclass_platdata *uc_pdata;
-	int current, value, mode, ret;
-	const char *mode_name = NULL;
-	struct udevice *dev;
+	int current, value, mode;
+	const char *mode_name;
 	bool enabled;
 
-	ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
-	if (ret)
-		return ret;
-
 	printf("Regulator %s status:\n", uc_pdata->name);
 
 	enabled = regulator_get_enable(dev);

@@ -206,6 +201,57 @@ static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	mode = regulator_get_mode(dev);
 	mode_name = get_mode_name(uc_pdata->mode, uc_pdata->mode_count, mode);
 	constraint(" * mode id:", mode, mode_name);
+}
+
+static void do_status_line(struct udevice *dev)
+{
+	struct dm_regulator_uclass_platdata *pdata;
+	int current, value, mode;
+	const char *mode_name;
+	bool enabled;
+
+	pdata = dev_get_uclass_platdata(dev);
+	enabled = regulator_get_enable(dev);
+	value = regulator_get_value(dev);
+	current = regulator_get_current(dev);
+	mode = regulator_get_mode(dev);
+	mode_name = get_mode_name(pdata->mode, pdata->mode_count, mode);
+	printf("%-20s %-10s ", pdata->name, enabled ? "enabled" : "disabled");
+	if (value >= 0)
+		printf("%10d ", value);
+	else
+		printf("%10s ", "-");
+	if (current >= 0)
+		printf("%10d ", current);
+	else
+		printf("%10s ", "-");
+	if (mode >= 0)
+		printf("%-10s", mode_name);
+	else
+		printf("%-10s", "-");
+	printf("\n");
+}
+
+static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct dm_regulator_uclass_platdata *uc_pdata;
+	struct udevice *dev;
+	int ret;
+
+	if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) {
+		ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+		if (ret)
+			return CMD_RET_FAILURE;
+		do_status_detail(dev, uc_pdata);
+		return 0;
+	}
+
+	/* Show all of them in a list, probing them as needed */
+	printf("%-20s %-10s %10s %10s %-10s\n", "Name", "Enabled", "uV", "mA",
+	       "Mode");
+	for (ret = uclass_first_device(UCLASS_REGULATOR, &dev); dev;
+	     ret = uclass_next_device(&dev))
+		do_status_line(dev);
 
 	return CMD_RET_SUCCESS;
 }

@@ -400,7 +446,7 @@ U_BOOT_CMD(regulator, CONFIG_SYS_MAXARGS, 1, do_regulator,
 	"list             - list UCLASS regulator devices\n"
 	"regulator dev [regulator-name] - show/[set] operating regulator device\n"
 	"regulator info                 - print constraints info\n"
-	"regulator status               - print operating status\n"
+	"regulator status [-a]          - print operating status [for all]\n"
 	"regulator value [val] [-f]     - print/[set] voltage value [uV] (force)\n"
 	"regulator current [val]        - print/[set] current value [uA]\n"
 	"regulator mode [id]            - print/[set] operating mode id\n"

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new file mode 100644
index 0000000..8ed2ad4
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwrseq.h>
+
+int pwrseq_set_power(struct udevice *dev, bool enable)
+{
+	struct pwrseq_ops *ops = pwrseq_get_ops(dev);
+
+	if (!ops->set_power)
+		return -ENOSYS;
+
+	return ops->set_power(dev, enable);
+}
+
+UCLASS_DRIVER(pwrseq) = {
+	.id		= UCLASS_PWRSEQ,
+	.name		= "pwrseq",
+};

index a0a3a79..b5f43ae 100644
@@ -51,6 +51,7 @@ enum uclass_id {
 	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
 	UCLASS_PINCONFIG,	/* Pin configuration node device */
 	UCLASS_PMIC,		/* PMIC I/O device */
+	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_REGULATOR,	/* Regulator device */
 	UCLASS_RESET,		/* Reset device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */

new file mode 100644
index 0000000..b934f29
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __pwrseq_h
+#define __pwrseq_h
+
+struct pwrseq_ops {
+	int (*set_power)(struct udevice *dev, bool enable);
+};
+
+#define pwrseq_get_ops(dev)	((struct pwrseq_ops *)(dev)->driver->ops)
+
+int pwrseq_set_power(struct udevice *dev, bool enable);
+
+#endif

index 8199cad..b2c5729 100644
@@ -113,6 +113,7 @@ static void configure_l2ctlr(void)
 
 static int configure_emmc(struct udevice *pinctrl)
 {
+#ifdef CONFIG_SPL_MMC_SUPPORT
 	struct gpio_desc desc;
 	int ret;
 

@@ -142,6 +143,7 @@ static int configure_emmc(struct udevice *pinctrl)
 		debug("gpio value ret=%d\n", ret);
 		return ret;
 	}
+#endif
 
 	return 0;
 }

index 12fa685..081675e 100644
@@ -46,14 +46,18 @@ struct rk3288_pmu {
 	u32 gpio_op;
 
 	u32 gpio0_sel18;	/* 0x80 */
-	u32 gpio0a_iomux;
-	u32 gpio0b_iomux;
-	u32 gpio0c_iomux;
-	u32 gpio0d_iomux;
+	u32 gpio0_iomux[4];	/* a, b, c, d */
 	u32 sys_reg[4];
 };
 check_member(rk3288_pmu, sys_reg[3], 0x00a0);
 
+enum {
+	PMU_GPIO0_A	= 0,
+	PMU_GPIO0_B,
+	PMU_GPIO0_C,
+	PMU_GPIO0_D,
+};
+
 /* PMU_GPIO0_B_IOMUX */
 enum {
 	GPIO0_B7_SHIFT		= 14,

index c432a00..ec3c4fe 100644
@@ -56,10 +56,10 @@ static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 {
 	switch (i2c_id) {
 	case PERIPH_ID_I2C0:
-		clrsetbits_le32(&pmu->gpio0b_iomux,
+		clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 				GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 				GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
-		clrsetbits_le32(&pmu->gpio0b_iomux,
+		clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 				GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 				GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 		break;

index 9b4268e..080c831 100644
@@ -9,7 +9,9 @@
 #include <dm.h>
 #include <dwmmc.h>
 #include <errno.h>
+#include <pwrseq.h>
 #include <syscon.h>
+#include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/periph.h>
 #include <linux/err.h>

@@ -64,6 +66,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
+	struct udevice *pwr_dev __maybe_unused;
 	u32 minmax[2];
 	int ret;
 	int fifo_depth;

@@ -90,6 +93,16 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
 		host->fifo_mode = true;
 
+#ifdef CONFIG_PWRSEQ
+	/* Enable power if needed */
+	ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
+					   &pwr_dev);
+	if (!ret) {
+		ret = pwrseq_set_power(pwr_dev, true);
+		if (ret)
+			return ret;
+	}
+#endif
 	ret = add_dwmci(host, minmax[1], minmax[0]);
 	if (ret)
 		return ret;

@@ -112,3 +125,37 @@ U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 	.probe		= rockchip_dwmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
 };
+
+#ifdef CONFIG_PWRSEQ
+static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
+{
+	struct gpio_desc reset;
+	int ret;
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
+	if (ret)
+		return ret;
+	dm_gpio_set_value(&reset, 1);
+	udelay(1);
+	dm_gpio_set_value(&reset, 0);
+	udelay(200);
+
+	return 0;
+}
+
+static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
+	.set_power	= rockchip_dwmmc_pwrseq_set_power,
+};
+
+static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
+	{ .compatible = "mmc-pwrseq-emmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
+	.name		= "mmc_pwrseq_emmc",
+	.id		= UCLASS_PWRSEQ,
+	.of_match	= rockchip_dwmmc_pwrseq_ids,
+	.ops		= &rockchip_dwmmc_pwrseq_ops,
+};
+#endif

index 238711a..f47573b 100644
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT

index f650810..dfecc24 100644
@@ -13,8 +13,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3036.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
 #include <dm/lists.h>
+#include <dt-bindings/clock/rk3036-cru.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -233,19 +233,19 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
 }
 
 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
-				  enum periph_id periph)
+				  int periph)
 {
 	uint src_rate;
 	uint div, mux;
 	u32 con;
 
 	switch (periph) {
-	case PERIPH_ID_EMMC:
+	case HCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 		break;
-	case PERIPH_ID_SDCARD:
+	case HCLK_SDIO:
 		con = readl(&cru->cru_clksel_con[12]);
 		mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;

@@ -259,7 +259,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
-				  enum periph_id periph, uint freq)
+				  int periph, uint freq)
 {
 	int src_clk_div;
 	int mux;

@@ -277,14 +277,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
 	}
 
 	switch (periph) {
-	case PERIPH_ID_EMMC:
+	case HCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
 			     EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 			     mux << EMMC_PLL_SHIFT |
 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
 		break;
-	case PERIPH_ID_SDCARD:
+	case HCLK_SDIO:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
 			     MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,

@@ -320,7 +320,7 @@ static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 	ulong new_rate;
 
 	switch (periph) {
-	case PERIPH_ID_EMMC:
+	case HCLK_EMMC:
 		new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
 						periph, rate);
 		break;

164 lines not on this page · raw message

index 080c831..cb9e104 100644
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct rockchip_dwmmc_priv {
 	struct udevice *clk;
-	struct rk3288_grf *grf;
+	int periph;
 	struct dwmci_host host;
 };
 

@@ -30,8 +30,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = clk_set_periph_rate(priv->clk, PERIPH_ID_SDMMC0 + host->dev_index,
-				  freq);
+	ret = clk_set_periph_rate(priv->clk, priv->periph, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);
 		return ret;

@@ -71,12 +70,10 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	int ret;
 	int fifo_depth;
 
-	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	if (IS_ERR(priv->grf))
-		return PTR_ERR(priv->grf);
-	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk);
-	if (ret)
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
 		return ret;
+	priv->periph = ret;
 
 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
 				 "clock-freq-min-max", minmax, 2))

index e410e7d1..49c2bdf 100644
@@ -363,7 +363,7 @@ static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
 	return 0;
 }
 
-static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint clk_general_rate,
+static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int periph)
 {
 	uint src_rate;

@@ -390,18 +390,18 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint clk_general_rate,
 		return -EINVAL;
 	}
 
-	src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : clk_general_rate;
+	src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 	return DIV_TO_RATE(src_rate, div);
 }
 
-static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint clk_general_rate,
+static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int  periph, uint freq)
 {
 	int src_clk_div;
 	int mux;
 
-	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
-	src_clk_div = RATE_TO_DIV(clk_general_rate, freq);
+	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+	src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 
 	if (src_clk_div > 0x3f) {
 		src_clk_div = RATE_TO_DIV(OSC_HZ, freq);

@@ -439,10 +439,10 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint clk_general_rate,
 		return -EINVAL;
 	}
 
-	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+	return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 }
 
-static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint clk_general_rate,
+static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int periph)
 {
 	uint div, mux;

@@ -469,16 +469,16 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint clk_general_rate,
 	}
 	assert(mux == SPI0_PLL_SELECT_GENERAL);
 
-	return DIV_TO_RATE(clk_general_rate, div);
+	return DIV_TO_RATE(gclk_rate, div);
 }
 
-static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint clk_general_rate,
+static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int periph, uint freq)
 {
 	int src_clk_div;
 
-	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
-	src_clk_div = RATE_TO_DIV(clk_general_rate, freq);
+	debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
+	src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 	switch (periph) {
 	case SCLK_SPI0:
 		rk_clrsetreg(&cru->cru_clksel_con[25],

@@ -505,7 +505,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint clk_general_rate,
 		return -EINVAL;
 	}
 
-	return rockchip_spi_get_clk(cru, clk_general_rate, periph);
+	return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)

index 49c2bdf..df5c38c 100644
@@ -508,6 +508,42 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
+static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(dev);
+	struct udevice *gclk;
+	ulong new_rate, gclk_rate;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+	if (ret)
+		return ret;
+	gclk_rate = clk_get_rate(gclk);
+	switch (periph) {
+	case HCLK_EMMC:
+	case HCLK_SDIO0:
+	case HCLK_SDIO1:
+		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
+		break;
+	case SCLK_SPI0:
+	case SCLK_SPI1:
+	case SCLK_SPI2:
+		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
+		break;
+	case PCLK_I2C0:
+	case PCLK_I2C1:
+	case PCLK_I2C2:
+	case PCLK_I2C3:
+	case PCLK_I2C4:
+	case PCLK_I2C5:
+		return gclk_rate;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 {
 	struct rk3288_clk_priv *priv = dev_get_priv(dev);

@@ -543,6 +579,7 @@ static struct clk_ops rk3288_clk_ops = {
 	.get_rate	= rk3288_clk_get_rate,
 	.set_rate	= rk3288_clk_set_rate,
 	.set_periph_rate = rk3288_set_periph_rate,
+	.get_periph_rate = rk3288_get_periph_rate,
 };
 
 static int rk3288_clk_probe(struct udevice *dev)

index 8a0376c..a9ea268 100644
@@ -62,4 +62,16 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  */
 void *rockchip_get_cru(void);
 
+/**
+ * rkclk_get_clk() - get a pointer to a given clock
+ *
+ * This is an internal function - use outside the clock subsystem indicates
+ * that work is needed!
+ *
+ * @clk_id:	Clock requested
+ * @devp:	Returns a pointer to that clock
+ * @return 0 if OK, -ve on error
+ */
+int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
+
 #endif

index df5c38c..fdc5347 100644
@@ -15,7 +15,9 @@
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/hardware.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dm/device-internal.h>
 #include <dm/lists.h>
+#include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -139,6 +141,24 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
+int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
+{
+	struct udevice *dev;
+
+	for (uclass_find_first_device(UCLASS_CLK, &dev);
+	     dev;
+	     uclass_find_next_device(&dev)) {
+		struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+
+		if (plat->clk_id == clk_id) {
+			*devp = dev;
+			return device_probe(dev);
+		}
+	}
+
+	return -ENODEV;
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {

@@ -515,7 +535,7 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 	ulong new_rate, gclk_rate;
 	int ret;
 
-	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 	if (ret)
 		return ret;
 	gclk_rate = clk_get_rate(gclk);

@@ -551,7 +571,7 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 	ulong new_rate, gclk_rate;
 	int ret;
 
-	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 	if (ret)
 		return ret;
 	gclk_rate = clk_get_rate(gclk);

index ebdba35..3fceade 100644
@@ -30,10 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct rk_i2c {
 	struct udevice *clk;
-	struct udevice *pinctrl;
 	struct i2c_regs *regs;
 	unsigned int speed;
-	enum periph_id id;
+	int clk_id;
 };
 
 static inline void rk_i2c_get_div(int div, int *divh, int *divl)

@@ -56,7 +55,7 @@ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
 	int div, divl, divh;
 
 	/* First get i2c rate from pclk */
-	i2c_rate = clk_get_periph_rate(i2c->clk, i2c->id);
+	i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);
 
 	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
 	divh = 0;

@@ -352,23 +351,29 @@ int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 	return 0;
 }
 
-static int rockchip_i2c_probe(struct udevice *bus)
+static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
 {
-	struct rk_i2c *i2c = dev_get_priv(bus);
+	struct rk_i2c *priv = dev_get_priv(bus);
 	int ret;
 
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &i2c->pinctrl);
-	if (ret)
-		return ret;
-	ret = uclass_get_device(UCLASS_CLK, 0, &i2c->clk);
-	if (ret)
-		return ret;
-	ret = pinctrl_get_periph_id(i2c->pinctrl, bus);
-	if (ret < 0)
+	ret = clk_get_by_index(bus, 0, &priv->clk);
+	if (ret < 0) {
+		debug("%s: Could not get clock for %s: %d\n", __func__,
+		      bus->name, ret);
 		return ret;
-	i2c->id = ret;
-	i2c->regs = (void *)dev_get_addr(bus);
-	return pinctrl_request(i2c->pinctrl, i2c->id, 0);
+	}
+	priv->clk_id = ret;
+
+	return 0;
+}
+
+static int rockchip_i2c_probe(struct udevice *bus)
+{
+	struct rk_i2c *priv = dev_get_priv(bus);
+
+	priv->regs = (void *)dev_get_addr(bus);
+
+	return 0;
 }
 
 static const struct dm_i2c_ops rockchip_i2c_ops = {

@@ -385,6 +390,7 @@ U_BOOT_DRIVER(i2c_rockchip) = {
 	.name	= "i2c_rockchip",
 	.id	= UCLASS_I2C,
 	.of_match = rockchip_i2c_ids,
+	.ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
 	.probe	= rockchip_i2c_probe,
 	.priv_auto_alloc_size = sizeof(struct rk_i2c),
 	.ops	= &rockchip_i2c_ops,

index 242a83b..62434be 100644
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI	0
 
 struct rockchip_spi_platdata {
-	enum periph_id periph_id;
+	int periph_id;
 	struct udevice *pinctrl;
 	s32 frequency;		/* Default clock frequency, -1 for none */
 	fdt_addr_t base;

@@ -36,10 +36,10 @@ struct rockchip_spi_platdata {
 
 struct rockchip_spi_priv {
 	struct rockchip_spi *regs;
-	struct udevice *clk_gpll;
+	struct udevice *clk;
+	int clk_id;
 	unsigned int max_freq;
 	unsigned int mode;
-	enum periph_id periph_id;	/* Peripheral ID for this device */
 	ulong last_transaction_us;	/* Time of last transaction end */
 	u8 bits_per_word;		/* max 16 bits per word */
 	u8 n_bytes;

@@ -114,6 +114,7 @@ static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 {
 	struct rockchip_spi_platdata *plat = bus->platdata;
+	struct rockchip_spi_priv *priv = dev_get_priv(bus);
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
 	int ret;

@@ -127,16 +128,23 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 	if (ret < 0) {
 		debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
 		      bus->name, ret);
-		return -FDT_ERR_NOTFOUND;
+		return ret;
 	}
 	plat->periph_id = ret;
+	ret = clk_get_by_index(bus, 0, &priv->clk);
+	if (ret < 0) {
+		debug("%s: Could not get clock for %s: %d\n", __func__,
+		      bus->name, ret);
+		return ret;
+	}
+	priv->clk_id = ret;
 
 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-					50000000);
+					 50000000);
 	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
 					"spi-deactivate-delay", 0);
-	debug("%s: base=%lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
-	      __func__, plat->base, plat->periph_id, plat->frequency,
+	debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+	      __func__, (uint)plat->base, plat->periph_id, plat->frequency,
 	      plat->deactivate_delay_us);
 
 	return 0;

@@ -153,18 +161,12 @@ static int rockchip_spi_probe(struct udevice *bus)
 
 	priv->last_transaction_us = timer_get_us();
 	priv->max_freq = plat->frequency;
-	priv->periph_id = plat->periph_id;
-	ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk_gpll);
-	if (ret) {
-		debug("%s: Failed to find CLK_GENERAL: %d\n", __func__, ret);
-		return ret;
-	}
 
 	/*
 	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 	 * is the assumed speed for CLK_GENERAL.
 	 */
-	ret = clk_set_periph_rate(priv->clk_gpll, plat->periph_id, 99000000);
+	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
 	if (ret < 0) {
 		debug("%s: Failed to set clock: %d\n", __func__, ret);
 		return ret;

@@ -248,7 +250,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 
 	writel(ctrlr0, &regs->ctrlr0);
 
-	ret = pinctrl_request(plat->pinctrl, priv->periph_id, slave_plat->cs);
+	ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
 	if (ret) {
 		debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
 		return ret;

index 62434be..2b58393 100644
@@ -182,13 +182,15 @@ static int rockchip_spi_probe(struct udevice *bus)
 static int rockchip_spi_claim_bus(struct udevice *dev)
 {
 	struct udevice *bus = dev->parent;
-	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 	struct rockchip_spi_priv *priv = dev_get_priv(bus);
 	struct rockchip_spi *regs = priv->regs;
-	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	u8 spi_dfs, spi_tf;
 	uint ctrlr0;
+#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
+	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	int ret;
+#endif
 
 	/* Disable the SPI hardware */
 	rkspi_enable_chip(regs, 0);

@@ -249,12 +251,13 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 	ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 
 	writel(ctrlr0, &regs->ctrlr0);
-
+#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
 	ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
 	if (ret) {
 		debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
 		return ret;
 	}
+#endif
 
 	return 0;
 }

index fdc5347..d294788 100644
@@ -541,8 +541,8 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 	gclk_rate = clk_get_rate(gclk);
 	switch (periph) {
 	case HCLK_EMMC:
+	case HCLK_SDMMC:
 	case HCLK_SDIO0:
-	case HCLK_SDIO1:
 		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
 		break;
 	case SCLK_SPI0:

index ec3c4fe..0e7721e 100644
@@ -24,8 +24,103 @@ DECLARE_GLOBAL_DATA_PTR;
 struct rk3288_pinctrl_priv {
 	struct rk3288_grf *grf;
 	struct rk3288_pmu *pmu;
+	int num_banks;
 };
 
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLY		BIT(0)
+#define IOMUX_WIDTH_4BIT	BIT(1)
+#define IOMUX_SOURCE_PMU	BIT(2)
+#define IOMUX_UNROUTED		BIT(3)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ *	    an initial offset value the relevant source offset can be reset
+ *	    to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+	u8 type;
+	s16 offset;
+};
+
+/**
+ * @reg: register offset of the gpio bank
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @name: name of the bank
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+	u16 reg;
+	u8 nr_pins;
+	u8 bank_num;
+	char *name;
+	struct rockchip_iomux iomux[4];
+};
+
+#define PIN_BANK(id, pins, label)			\
+	{						\
+		.bank_num	= id,			\
+		.nr_pins	= pins,			\
+		.name		= label,		\
+		.iomux		= {			\
+			{ .offset = -1 },		\
+			{ .offset = -1 },		\
+			{ .offset = -1 },		\
+			{ .offset = -1 },		\
+		},					\
+	}
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)	\
+	{								\
+		.bank_num	= id,					\
+		.nr_pins	= pins,					\
+		.name		= label,				\
+		.iomux		= {					\
+			{ .type = iom0, .offset = -1 },			\
+			{ .type = iom1, .offset = -1 },			\
+			{ .type = iom2, .offset = -1 },			\
+			{ .type = iom3, .offset = -1 },			\
+		},							\
+	}
+
+#ifndef CONFIG_SPL_BUILD
+static struct rockchip_pin_bank rk3288_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_UNROUTED
+			    ),
+	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
+					     IOMUX_UNROUTED,
+					     IOMUX_UNROUTED,
+					     0
+			    ),
+	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
+	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
+	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+					     IOMUX_WIDTH_4BIT,
+					     0,
+					     0
+			    ),
+	PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
+					     0,
+					     0,
+					     IOMUX_UNROUTED
+			    ),
+	PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
+	PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
+					     0,
+					     IOMUX_WIDTH_4BIT,
+					     IOMUX_UNROUTED
+			    ),
+	PIN_BANK(8, 16, "gpio8"),
+};
+#endif
+
 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 {
 	switch (pwm_id) {

@@ -410,7 +505,106 @@ static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 	return rk3288_pinctrl_request(dev, func, 0);
 }
 
+#ifndef CONFIG_SPL_BUILD
+static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
+				   int muxval, int flags)
+{
+	struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+	struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
+	uint shift, muxnum, ind = index;
+	u32 *addr;
+
+	debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
+	for (muxnum = 0; muxnum < 4; muxnum++) {
+		struct rockchip_iomux *mux = &bank->iomux[muxnum];
+		uint mask;
+
+		if (ind >= 8) {
+			ind -= 8;
+			continue;
+		}
+
+		if (mux->type & IOMUX_SOURCE_PMU)
+			addr = priv->pmu->gpio0_iomux;
+		else
+			addr = (u32 *)priv->grf - 4;
+		addr += mux->offset;
+		shift = ind & 7;
+		if (mux->type & IOMUX_WIDTH_4BIT) {
+			mask = 0xf;
+			shift *= 4;
+			if (shift >= 16) {
+				shift -= 16;
+				addr++;
+			}
+		} else {
+			mask = 3;
+			shift *= 2;
+		}
+
+		debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
+		      mask, shift);
+		rk_clrsetreg(addr, mask << shift, muxval << shift);
+		break;
+	}
+	if (flags) {
+		uint val = 0;
+
+		if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
+			val = 1;
+		else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
+			val = 2;
+		shift = (index & 7) * 2;
+		ind = index >> 3;
+		if (banknum == 0)
+			addr = &priv->pmu->gpio0pull[ind];
+		else
+			addr = &priv->grf->gpio1_p[banknum - 1][ind];
+		debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
+		      shift);
+		rk_clrsetreg(addr, 3 << shift, val << shift);
+	}
+
+	return 0;
+}
+
+static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	const void *blob = gd->fdt_blob;
+	int pcfg_node, ret, flags, count, i;
+	u32 cell[40], *ptr;
+
+	debug("%s: %s %s\n", __func__, dev->name, config->name);
+	ret = fdtdec_get_int_array_count(blob, config->of_offset,
+					 "rockchip,pins", cell,
+					 ARRAY_SIZE(cell));
+	if (ret < 0) {
+		debug("%s: bad array %d\n", __func__, ret);
+		return -EINVAL;
+	}
+	count = ret;
+	for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
+		pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
+		if (pcfg_node < 0)
+			return -EINVAL;
+		flags = pinctrl_decode_pin_config(blob, pcfg_node);
+		if (flags < 0)
+			return flags;
+
+		ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
+					      flags);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
 static struct pinctrl_ops rk3288_pinctrl_ops = {
+#ifndef CONFIG_SPL_BUILD
+	.set_state	= rk3288_pinctrl_set_state,
+#endif
 	.set_state_simple	= rk3288_pinctrl_set_state_simple,
 	.request	= rk3288_pinctrl_request,
 	.get_periph_id	= rk3288_pinctrl_get_periph_id,

@@ -422,15 +616,49 @@ static int rk3288_pinctrl_bind(struct udevice *dev)
 	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
 }
 
+#ifndef CONFIG_SPL_BUILD
+static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
+				       struct rockchip_pin_bank *banks,
+				       int count)
+{
+	struct rockchip_pin_bank *bank;
+	uint reg, muxnum, banknum;
+
+	reg = 0;
+	for (banknum = 0; banknum < count; banknum++) {
+		bank = &banks[banknum];
+		bank->reg = reg;
+		debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
+		for (muxnum = 0; muxnum < 4; muxnum++) {
+			struct rockchip_iomux *mux = &bank->iomux[muxnum];
+
+			if (!(mux->type & IOMUX_UNROUTED))
+				mux->offset = reg;
+			if (mux->type & IOMUX_WIDTH_4BIT)
+				reg += 2;
+			else
+				reg += 1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
 static int rk3288_pinctrl_probe(struct udevice *dev)
 {
 	struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+	int ret = 0;
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 	debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
+#ifndef CONFIG_SPL_BUILD
+	ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
+					  ARRAY_SIZE(rk3288_pin_banks));
+#endif
 
-	return 0;
+	return ret;
 }
 
 static const struct udevice_id rk3288_pinctrl_ids[] = {

index e29d776..78c06af 100644
@@ -15,4 +15,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPI_FLASH_GIGADEVICE
 
+#undef CONFIG_SPL_GPIO_SUPPORT
+
 #endif

index 65d6df4..bb0f63a 100644
@@ -141,7 +141,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 	if (argc > 0)
 		str_gpio = *argv;
-	if (!strcmp(str_cmd, "status")) {
+	if (!strncmp(str_cmd, "status", 1)) {
 		/* Support deprecated gpio_status() */
 #ifdef gpio_status
 		gpio_status();

index a567414..8a60c72 100644
@@ -939,14 +939,10 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
+#ifdef CONFIG_DM_SPI_FLASH
 	fdt_addr_t addr;
 	fdt_size_t size;
-	int node;
-
-	/* If there is no node, do nothing */
-	node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
-	if (node < 0)
-		return 0;
+	int node = flash->dev->of_offset;
 
 	addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
 	if (addr == FDT_ADDR_T_NONE) {

@@ -959,6 +955,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 		return -1;
 	}
 	flash->memory_map = map_sysmem(addr, size);
+#endif
 
 	return 0;
 }

index 49709f3..8b19998 100644
@@ -18,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
 int pmic_bind_children(struct udevice *pmic, int offset,
 		       const struct pmic_child_info *child_info)
 {

@@ -84,6 +85,7 @@ int pmic_bind_children(struct udevice *pmic, int offset,
 	debug("Bound: %d childs for PMIC: '%s'\n", bind_count, pmic->name);
 	return bind_count;
 }
+#endif
 
 int pmic_get(const char *name, struct udevice **devp)
 {

index 1acbfaf..ccc5d30 100644
@@ -246,6 +246,16 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph)
 	return ops->get_periph_id(dev, periph);
 }
 
+int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index)
+{
+	struct pinctrl_ops *ops = pinctrl_get_ops(dev);
+
+	if (!ops->get_gpio_mux)
+		return -ENOSYS;
+
+	return ops->get_gpio_mux(dev, banknum, index);
+}
+
 /**
  * pinconfig_post-bind() - post binding for PINCTRL uclass
  * Recursively bind child nodes as pinconfig devices in case of full pinctrl.

index 5cd4503..0eb4b92 100644
@@ -114,6 +114,22 @@ struct pinctrl_ops {
 	* @return peripheral ID of @periph, or -ENOENT on error
 	*/
 	int (*get_periph_id)(struct udevice *dev, struct udevice *periph);
+
+	/**
+	 * get_gpio_mux() - get the mux value for a particular GPIO
+	 *
+	 * This allows the raw mux value for a GPIO to be obtained. It is
+	 * useful for displaying the function being used by that GPIO, such
+	 * as with the 'gpio' command. This function is internal to the GPIO
+	 * subsystem and should not be used by generic code. Typically it is
+	 * used by a GPIO driver with knowledge of the SoC pinctrl setup.
+	 *
+	* @dev:		Pinctrl device to use
+	* @banknum:	GPIO bank number
+	* @index:	GPIO index within the bank
+	* @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+	 */
+	int (*get_gpio_mux)(struct udevice *dev, int banknum, int index);
 };
 
 #define pinctrl_get_ops(dev)	((struct pinctrl_ops *)(dev)->driver->ops)

@@ -297,4 +313,20 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
  */
 int pinctrl_decode_pin_config(const void *blob, int node);
 
+/**
+ * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
+ *
+ * This allows the raw mux value for a GPIO to be obtained. It is
+ * useful for displaying the function being used by that GPIO, such
+ * as with the 'gpio' command. This function is internal to the GPIO
+ * subsystem and should not be used by generic code. Typically it is
+ * used by a GPIO driver with knowledge of the SoC pinctrl setup.
+ *
+ * @dev:	Pinctrl device to use
+ * @banknum:	GPIO bank number
+ * @index:	GPIO index within the bank
+ * @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+*/
+int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index);
+
 #endif /* __PINCTRL_H */

index e1acefe..12095e7 100644
@@ -254,8 +254,8 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
 	return -ENODEV;
 }
 
-static int uclass_find_device_by_of_offset(enum uclass_id id, int node,
-					   struct udevice **devp)
+int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+				    struct udevice **devp)
 {
 	struct uclass *uc;
 	struct udevice *dev;

index b51e1da..ad284b8 100644
@@ -99,6 +99,22 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
 			      bool find_req_seq, struct udevice **devp);
 
 /**
+ * uclass_find_device_by_of_offset() - Find a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+				    struct udevice **devp);
+
+/**
  * uclass_bind_device() - Associate device with a uclass
  *
  * Connect the device into uclass's list of devices.

index 8b19998..7211026 100644
@@ -133,8 +133,9 @@ int pmic_reg_read(struct udevice *dev, uint reg)
 	u8 byte;
 	int ret;
 
+	debug("%s: reg=%x", __func__, reg);
 	ret = pmic_read(dev, reg, &byte, 1);
-	debug("%s: reg=%x, value=%x\n", __func__, reg, byte);
+	debug(", value=%x, ret=%d\n", byte, ret);
 
 	return ret ? ret : byte;
 }

@@ -142,9 +143,13 @@ int pmic_reg_read(struct udevice *dev, uint reg)
 int pmic_reg_write(struct udevice *dev, uint reg, uint value)
 {
 	u8 byte = value;
+	int ret;
+
+	debug("%s: reg=%x, value=%x", __func__, reg, value);
+	ret = pmic_write(dev, reg, &byte, 1);
+	debug(", ret=%d\n", ret);
 
-	debug("%s: reg=%x, value=%x\n", __func__, reg, value);
-	return pmic_write(dev, reg, &byte, 1);
+	return ret;
 }
 
 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)

index 11d5f07..770f471 100644
@@ -30,9 +30,12 @@ static int rk808_reg_count(struct udevice *dev)
 static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
 			  int len)
 {
-	if (dm_i2c_write(dev, reg, buff, len)) {
+	int ret;
+
+	ret = dm_i2c_write(dev, reg, buff, len);
+	if (ret) {
 		debug("write error to device: %p register: %#x!", dev, reg);
-		return -EIO;
+		return ret;
 	}
 
 	return 0;

@@ -40,9 +43,12 @@ static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
 
 static int rk808_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
 {
-	if (dm_i2c_read(dev, reg, buff, len)) {
+	int ret;
+
+	ret = dm_i2c_read(dev, reg, buff, len);
+	if (ret) {
 		debug("read error from device: %p register: %#x!", dev, reg);
-		return -EIO;
+		return ret;
 	}
 
 	return 0;

index 4241a4c..fec2886 100644
@@ -178,7 +178,7 @@ static void regulator_show(struct udevice *dev, int ret)
 		printf("; set %d uA", uc_pdata->min_uA);
 	printf("; enabling");
 	if (ret)
-		printf(" (ret: %d)\n", ret);
+		printf(" (ret: %d)", ret);
 	printf("\n");
 }
 

index fec2886..9fe07f2 100644
@@ -334,6 +334,8 @@ int regulators_enable_boot_on(bool verbose)
 		}
 		if (verbose)
 			regulator_show(dev, ret);
+		if (ret == -ENOSYS)
+			ret = 0;
 	}
 
 	return ret;

index 8a4c568..b483c1e 100644
@@ -67,8 +67,23 @@ ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
 {
-	struct fdtdec_phandle_args args;
 	int ret;
+#ifdef CONFIG_SPL_BUILD
+	u32 cell[2];
+
+	if (index != 0)
+		return -ENOSYS;
+	assert(*clk_devp);
+	ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
+	if (ret)
+		return ret;
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
+				   cell, 2);
+	if (ret)
+		return ret;
+	return cell[1];
+#else
+	struct fdtdec_phandle_args args;
 
 	assert(*clk_devp);
 	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,

@@ -87,6 +102,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
 		return ret;
 	}
 	return args.args_count > 0 ? args.args[0] : 0;
+#endif
 }
 #endif
 

index 09017cc..5da04b9 100644
@@ -400,7 +400,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
 
 	if (n == 1) {
 		setbits_le32(&pctl->ppcfg, 1);
-		writel(RK_SETBITS(1 << (8 + channel)), &grf->soc_con0);
+		rk_setreg(&grf->soc_con0, 1 << (8 + channel));
 		setbits_le32(&msch->ddrtiming, 1 << 31);
 		/* Data Byte disable*/
 		clrbits_le32(&publ->datx8[2].dxgcr, 1);

@@ -410,7 +410,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
 		setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 	} else {
 		clrbits_le32(&pctl->ppcfg, 1);
-		writel(RK_CLRBITS(1 << (8 + channel)), &grf->soc_con0);
+		rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
 		clrbits_le32(&msch->ddrtiming, 1 << 31);
 		/* Data Byte enable*/
 		setbits_le32(&publ->datx8[2].dxgcr, 1);

@@ -571,8 +571,7 @@ static void dram_all_config(const struct dram_info *dram,
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
 	writel(sys_reg, &dram->pmu->sys_reg[2]);
-	writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride),
-	       &dram->sgrf->soc_con2);
+	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
 
 static int sdram_init(const struct dram_info *dram,

index 7affd11..bf7540a 100644
@@ -22,11 +22,11 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type)
 		return PTR_ERR(cru);
 	switch (type) {
 	case RESET_WARM:
-		writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
+		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xeca8, &cru->cru_glb_srst_snd_value);
 		break;
 	case RESET_COLD:
-		writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
+		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
 		break;
 	default:

index 2b58393..aaf139d 100644
@@ -44,6 +44,7 @@ struct rockchip_spi_priv {
 	u8 bits_per_word;		/* max 16 bits per word */
 	u8 n_bytes;
 	unsigned int speed_hz;
+	unsigned int last_speed_hz;
 	unsigned int tmode;
 	uint input_rate;
 };

@@ -82,6 +83,7 @@ static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
 	debug("spi speed %u, div %u\n", speed, clk_div);
 
 	writel(clk_div, &priv->regs->baudr);
+	priv->last_speed_hz = speed;
 }
 
 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)

@@ -212,7 +214,8 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 		return -EPROTONOSUPPORT;
 	}
 
-	rkspi_set_clk(priv, priv->speed_hz);
+	if (priv->speed_hz != priv->last_speed_hz)
+		rkspi_set_clk(priv, priv->speed_hz);
 
 	/* Operation Mode */
 	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

index aaf139d..3418f9b 100644
@@ -221,7 +221,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
 
 	/* Data Frame Size */
-	ctrlr0 |= spi_dfs & DFS_MASK << DFS_SHIFT;
+	ctrlr0 |= spi_dfs << DFS_SHIFT;
 
 	/* set SPI mode 0..3 */
 	if (priv->mode & SPI_CPOL)

@@ -242,7 +242,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
 	ctrlr0 |= FBM_MSB << FBM_SHIFT;
 
 	/* Byte and Halfword Transform */
-	ctrlr0 |= (spi_tf & HALF_WORD_MASK) << HALF_WORD_TX_SHIFT;
+	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
 
 	/* Rxd Sample Delay */
 	ctrlr0 |= 0 << RXDSD_SHIFT;

deleted file mode 100644
index fc7ac72..0000000
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <linux/err.h>
-
-void *rockchip_get_cru(void)
-{
-	struct udevice *dev;
-	fdt_addr_t addr;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
-	if (ret)
-		return ERR_PTR(ret);
-
-	addr = dev_get_addr(dev);
-	if (addr == FDT_ADDR_T_NONE)
-		return ERR_PTR(-EINVAL);
-
-	return (void *)addr;
-}

index dfecc24..bd5f22a 100644
@@ -57,6 +57,23 @@ static inline unsigned int log2(unsigned int value)
 	return fls(value) - 1;
 }
 
+void *rockchip_get_cru(void)
+{
+	struct udevice *dev;
+	fdt_addr_t addr;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return ERR_PTR(-EINVAL);
+
+	return (void *)addr;
+}
+
 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {

index d294788..5a8f175 100644
@@ -159,6 +159,19 @@ int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
 	return -ENODEV;
 }
 
+void *rockchip_get_cru(void)
+{
+	struct rk3288_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rkclk_get_clk(CLK_GENERAL, &dev);
+	if (ret)
+		return ERR_PTR(ret);
+	priv = dev_get_priv(dev);
+	return priv->cru;
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {