arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
Subsystems (3)
PATCH v2 1/1 arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
Instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A57 compatibility.
---
Changes in v2: Drop the not yet merged Cortex A53 part.
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -2
@@ -247,8 +247,8 @@ power-domains = <&cpg>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
Signature · 1 line
2.7.0
PATCH v2 1/1 arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
Quoted 16 lines · Dirk Behme
Instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A57 compatibility.
Signed-off-by Dirk Behme <[email protected]>---
Changes in v2: Drop the not yet merged Cortex A53 part.arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm64/boot/dts/renesas/r8a7795.dtsi +0
-0
arch/arm64/boot/dts/renesas/r8a7795.dtsi line 254
Quoted 10 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2
-2@@ -247,8 +247,8 @@ power-domains = <&cpg>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
Any further comments to this? If not, could this be applied?
Best regards
Dirk
PATCH v2 1/1 arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
[CC shiny new linux-renesas-soc ML]
Quoted 19 lines · Dirk Behme
Quoted 18 lines · Dirk Behme
Instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A57 compatibility.
Signed-off-by Dirk Behme <[email protected]>---
Changes in v2: Drop the not yet merged Cortex A53 part.arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm64/boot/dts/renesas/r8a7795.dtsi +0
-0@@ -247,8 +247,8 @@ power-domains = <&cpg>; };
Quoted 11 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi line 254
Quoted 8 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2
-2- pmu { - compatible = "arm,armv8-pmuv3"; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,Any further comments to this? If not, could this be applied?
Hi Dirk,
I apologise for loosing track of this one.
Does this change work? I saw some discussion about using arm,cortex-a57-pmu not working correctly on the r8a7795 in an earlier thread.
PATCH v2 1/1 arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
Quoted 1 line · Simon Horman
[CC shiny new linux-renesas-soc ML]
Yes, thanks. I've to learn and remember this, too :)
Quoted 32 lines · Dirk Behme
Quoted 19 lines · Dirk Behme
Quoted 18 lines
Instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A57 compatibility.
Signed-off-by Dirk Behme <[email protected]>---
Changes in v2: Drop the not yet merged Cortex A53 part.arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm64/boot/dts/renesas/r8a7795.dtsi +0
-0@@ -247,8 +247,8 @@ power-domains = <&cpg>; };Quoted 11 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi line 254
Quoted 8 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2
-2- pmu { - compatible = "arm,armv8-pmuv3"; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,Any further comments to this? If not, could this be applied?
Quoted 6 lines
Hi Dirk,
I apologise for loosing track of this one.
Does this change work? I saw some discussion about using arm,cortex-a57-pmu not working correctly on the r8a7795 in an earlier thread.
Yes, the A57 PMU probe is successful.
What's not working with the latest Renesas BSP is the A53, because these cores are disabled in the firmware coming with that BSP. But that's not a PMU issue, it's just because the cores are disabled. Using an older BSP firmware enabling all cores makes the A53 PMU probe fine, too.
Best regards
Dirk
PATCH v2 1/1 arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
Quoted 46 lines · Dirk Behme
Quoted 1 line · Simon Horman
[CC shiny new linux-renesas-soc ML]
Yes, thanks. I've to learn and remember this, too :)
Quoted 32 lines · Dirk Behme
Quoted 19 lines · Dirk Behme
Quoted 18 lines
Instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A57 compatibility.
Signed-off-by Dirk Behme <[email protected]>---
Changes in v2: Drop the not yet merged Cortex A53 part.arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm64/boot/dts/renesas/r8a7795.dtsi +0
-0@@ -247,8 +247,8 @@ power-domains = <&cpg>; };Quoted 11 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi line 254
Quoted 8 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2
-2- pmu { - compatible = "arm,armv8-pmuv3"; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,Any further comments to this? If not, could this be applied?
Quoted 6 lines
Hi Dirk,
I apologise for loosing track of this one.
Does this change work? I saw some discussion about using arm,cortex-a57-pmu not working correctly on the r8a7795 in an earlier thread.
Quoted 6 lines
Yes, the A57 PMU probe is successful.
What's not working with the latest Renesas BSP is the A53, because these cores are disabled in the firmware coming with that BSP. But that's not a PMU issue, it's just because the cores are disabled. Using an older BSP firmware enabling all cores makes the A53 PMU probe fine, too.
Thanks for the explanation. I have queued up this patch.