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ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB

PATCH New codekipper at gmail.com 2 participants 3 messages Feb 8, 2016

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codekipper at gmail.com

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#0 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB

From: Marcus Cooper <[email protected]>

Enable the otg/drc usb controller on the Olimex A20 EVB.

Signed-off-by Marcus Cooper <[email protected]>
---
 arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +24 -0
index c3c626b..93bbf26 100644
@@ -198,6 +198,10 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &pio {
 	ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin at 1 {
 		allwinner,pins = "PC3";

@@ -219,6 +223,13 @@
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin at 0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
 };
 
 &reg_ahci_5v {

@@ -254,6 +265,10 @@
 	regulator-name = "avcc";
 };
 
+&reg_usb0_vbus {
+	status = "okay";
+};
+
 &reg_usb1_vbus {
 	status = "okay";
 };

@@ -268,7 +283,16 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
Signature · 1 line
2.7.1
#1 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB

Hi,

Quoted 3 lines · codekipper at gmail.com

From: Marcus Cooper <[email protected]>

Enable the otg/drc usb controller on the Olimex A20 EVB.

Does the A20 EVB not have some form of Vbus detect for the OTG port hooked up ? That does not sound right. Please double check.

Regards,

Hans

Quoted 64 lines
Signed-off-by Marcus Cooper <[email protected]>
---
  arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 24 ++++++++++++++++++++++++
  1 file changed, 24 insertions(+)
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +24 -0
index c3c626b..93bbf26 100644
@@ -198,6 +198,10 @@
  	status = "okay";
  };
 
+&otg_sram {
+	status = "okay";
+};
+
  &pio {
  	ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin at 1 {
  		allwinner,pins = "PC3";

@@ -219,6 +223,13 @@
  		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin at 0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
  };
 
  &reg_ahci_5v {

@@ -254,6 +265,10 @@
  	regulator-name = "avcc";
  };
 
+&reg_usb0_vbus {
+	status = "okay";
+};
+
  &reg_usb1_vbus {
  	status = "okay";
  };

@@ -268,7 +283,16 @@
  	status = "okay";
  };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
  &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
  	usb1_vbus-supply = <&reg_usb1_vbus>;
  	usb2_vbus-supply = <&reg_usb2_vbus>;
  	status = "okay";
author
#2 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on Olimex A20 EVB

Quoted 11 lines · Hans de Goede

Hi,

Quoted 4 lines · codekipper at gmail.com

From: Marcus Cooper <[email protected]>

Enable the otg/drc usb controller on the Olimex A20 EVB.

Does the A20 EVB not have some form of Vbus detect for the OTG port hooked up ? That does not sound right. Please double check.

Yeah...looks like it does...PH5. I'll add that and test. CK

Quoted 74 lines

Regards,

Hans

Quoted 66 lines
Signed-off-by Marcus Cooper <[email protected]>
---
  arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 24
++++++++++++++++++++++++
  1 file changed, 24 insertions(+)
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +24 -0
index c3c626b..93bbf26 100644
@@ -198,6 +198,10 @@
        status = "okay";
  };
 
+&otg_sram {
+       status = "okay";
+};
+
  &pio {
        ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin at 1 {
                allwinner,pins = "PC3";

@@ -219,6 +223,13 @@
                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
        };
+
+       usb0_id_detect_pin: usb0_id_detect_pin at 0 {
+               allwinner,pins = "PH4";
+               allwinner,function = "gpio_in";
+               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+       };
  };
 
  &reg_ahci_5v {

@@ -254,6 +265,10 @@
        regulator-name = "avcc";
  };
 
+&reg_usb0_vbus {
+       status = "okay";
+};
+
  &reg_usb1_vbus {
        status = "okay";
  };

@@ -268,7 +283,16 @@
        status = "okay";
  };
 
+&usb_otg {
+       dr_mode = "otg";
+       status = "okay";
+};
+
  &usbphy {
+       pinctrl-names = "default";
+       pinctrl-0 = <&usb0_id_detect_pin>;
+       usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
+       usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        status = "okay";