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irqchip/gic-v3-its: Fix double EOIR write for LPI in EOImode==1

PATCH New Ashok Kumar 2 participants 2 messages Feb 11, 2016

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irqchip drivers Arm generic interrupt controller drivers
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Ashok Kumar

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#0 lore raw

PATCH 1/1 irqchip/gic-v3-its: Fix double EOIR write for LPI in EOImode==1

CPU receives SError exception EOI1_NO_INTS_ACTIVE when EOIR is written twice in gic_handle_irq and in its_eoi_irq for a single LPI in EOImode == 1.

Now irq_eoi of its_irq_chip calls parent irqchip's(gic_eoimode1_chip/gic_chip) irq_eoi handler which handles EOImode 0 and 1 separately.

This is introduced by
commit 0b996fd35957a ("irqchip/GICv3: Convert to EOImode == 1")

Signed-off-by Ashok Kumar <[email protected]>
---
 drivers/irqchip/irq-gic-v3-its.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
drivers/irqchip/irq-gic-v3-its.c +1 -6
index e23d1d1..a159529f 100644
@@ -597,11 +597,6 @@ static void its_unmask_irq(struct irq_data *d)
 	lpi_set_config(d, true);
 }
 
-static void its_eoi_irq(struct irq_data *d)
-{
-	gic_write_eoir(d->hwirq);
-}
-
 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 			    bool force)
 {

@@ -638,7 +633,7 @@ static struct irq_chip its_irq_chip = {
 	.name			= "ITS",
 	.irq_mask		= its_mask_irq,
 	.irq_unmask		= its_unmask_irq,
-	.irq_eoi		= its_eoi_irq,
+	.irq_eoi		= irq_chip_eoi_parent,
 	.irq_set_affinity	= its_set_affinity,
 	.irq_compose_msi_msg	= its_irq_compose_msi_msg,
 };
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2.1.0
#1 lore raw

PATCH 1/1 irqchip/gic-v3-its: Fix double EOIR write for LPI in EOImode==1

Quoted 11 lines · Ashok Kumar

CPU receives SError exception EOI1_NO_INTS_ACTIVE when EOIR is written twice in gic_handle_irq and in its_eoi_irq for a single LPI in EOImode == 1.

Now irq_eoi of its_irq_chip calls parent irqchip's(gic_eoimode1_chip/gic_chip) irq_eoi handler which handles EOImode 0 and 1 separately.

This is introduced by
commit 0b996fd35957a ("irqchip/GICv3: Convert to EOImode == 1")

Signed-off-by Ashok Kumar <[email protected]>

Ah, really good catch!

Acked-by Marc Zyngier <[email protected]>

I'll try to queue that for -rc4, but it is more likely that it will land in -rc5...

Thanks,

	M.
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