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ARM: imx: Do L2 errata only if the L2 cache isn't enabled

PATCH Superseded Dirk Behme 4 participants 6 messages Feb 12, 2016 – Feb 18, 2016

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape

v1 of 2 Superseded Latest is v2 →

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Dirk Behme

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#0 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

Signed-off-by Marcel Grosshans <[email protected]>
Signed-off-by Dirk Behme <[email protected]>
---
 arch/arm/mach-imx/system.c | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/mach-imx/system.c +4 -0
index 51c3501..a600bd7 100644
@@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
 		goto out;
 	}
 
+	if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
+		goto skip_if_enabled;
+
 	/* Configure the L2 PREFETCH and POWER registers */
 	val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
 	val |= 0x70800000;

@@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
 		val &= ~(1 << 30 | 1 << 23);
 	writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
 
+skip_if_enabled:
 	iounmap(l2x0_base);
 	of_node_put(np);
Signature · 1 line
2.5.0
#1 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

Quoted 6 lines · Dirk Behme

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

What's the reasoning behind this? The prefetch register is writable while the L2 cache is enabled, unlike the auxiliary control register.

Signature · 3 lines
RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/
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#2 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

Quoted 10 lines · Russell King - ARM Linux
Quoted 6 lines · Dirk Behme

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

What's the reasoning behind this? The prefetch register is writable while the L2 cache is enabled, unlike the auxiliary control register.

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an imprecise
external abort. If Linux runs from normal world the cache controller is already
enabled and thus no configuration is needed by Linux.

Best regards

Dirk

#3 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

Quoted 12 lines · Dirk Behme
Quoted 10 lines · Russell King - ARM Linux
Quoted 6 lines · Dirk Behme

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

What's the reasoning behind this? The prefetch register is writable while the L2 cache is enabled, unlike the auxiliary control register.

Quoted 7 lines

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an imprecise
external abort. If Linux runs from normal world the cache controller is already
enabled and thus no configuration is needed by Linux.

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in non-secure world?

Shawn

#4 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

Quoted 21 lines · Shawn Guo
Quoted 12 lines · Dirk Behme
Quoted 10 lines · Russell King - ARM Linux
Quoted 6 lines · Dirk Behme

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

What's the reasoning behind this? The prefetch register is writable while the L2 cache is enabled, unlike the auxiliary control register.

Quoted 7 lines

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an imprecise
external abort. If Linux runs from normal world the cache controller is already
enabled and thus no configuration is needed by Linux.

Quoted 4 lines

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in non-secure world?

Yes, in a scenario where one of the cores runs a RTOS.

Best regards

Dirk

#5 lore raw

PATCH 1/1 ARM: imx: Do L2 errata only if the L2 cache isn't enabled

Quoted 22 lines · Dirk Behme
Quoted 21 lines · Shawn Guo
Quoted 19 lines · Dirk Behme
Quoted 10 lines · Russell King - ARM Linux
Quoted 6 lines · Dirk Behme

All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped.

For the i.MX6 specific L2 cache handling we missed this check. Add it.

What's the reasoning behind this? The prefetch register is writable while the L2 cache is enabled, unlike the auxiliary control register.

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an imprecise
external abort. If Linux runs from normal world the cache controller is already
enabled and thus no configuration is needed by Linux.

Quoted 7 lines
Quoted 4 lines

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in non-secure world?

Yes, in a scenario where one of the cores runs a RTOS.

Can you please reword the commit log to have the above non-secure world user story mentioned in there?

Shawn