ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

Add the missing "cache-unified" and "cache-level" properties to the Cortex-A57 cache-controller node.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes", after dropping the "arm,data-latency" and "arm,tag-latency" properties.

---
  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
  1 file changed, 2 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index b5e46e4ff72ad003..c07f4e83b988ba42 100644

Quoted 19 lines · Geert Uytterhoeven

Add the missing "cache-unified" and "cache-level" properties to the Cortex-A57 cache-controller node.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes", after dropping the "arm,data-latency" and "arm,tag-latency" properties.

---
  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
  1 file changed, 2 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index b5e46e4ff72ad003..c07f4e83b988ba42 100644

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 72

Quoted 5 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -0

@@ -68,6 +68,8 @@
 
      L2_CA57: cache-controller at 0 {
          compatible = "cache";
+        cache-unified;
+        cache-level = <2>;

As this is completely unused on ARMv8 I don't think that we want to have these unused entries in the DT.

Sudeep: What do you think?

Quoted 30 lines · Dirk Behme

Quoted 19 lines · Geert Uytterhoeven

Add the missing "cache-unified" and "cache-level" properties to the Cortex-A57 cache-controller node.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes", after dropping the "arm,data-latency" and "arm,tag-latency" properties.

---
  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
  1 file changed, 2 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index b5e46e4ff72ad003..c07f4e83b988ba42 100644

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 72

Quoted 5 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -0

@@ -68,6 +68,8 @@
 
      L2_CA57: cache-controller at 0 {
          compatible = "cache";
+        cache-unified;
+        cache-level = <2>;

As this is completely unused on ARMv8 I don't think that we want to have these unused entries in the DT.

Quoted 2 lines

Sudeep: What do you think?

I am fine with that, I don't see any issue having them as they are static values and highly unlikely to change and hence no threat to backward compatibility.

The main concern I had with latency values is that it's currently not used anywhere but if we decide to use say in secure software, having the untested/early values in DT might cause compatibility issues in future as they were added much before the actual understanding of it's usage. So I prefer to defer them until then.

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes".

---
  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
  1 file changed, 6 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index c07f4e83b988ba42..c572527afec3403a 100644

Quoted 23 lines · Geert Uytterhoeven

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes".

---
  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
  1 file changed, 6 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index c07f4e83b988ba42..c572527afec3403a 100644
@@ -72,6 +72,12 @@
                cache-level = <2>;
        };
 

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 80

Quoted 6 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi +6 -0

+       L2_CA53: cache-controller at 1 {
+               compatible = "cache";
+               cache-unified;
+               cache-level = <2>;
+       };
+

As we don't have any CA53 in the device tree yet, and it was rejected to add it, I'd think that we don't want these unused entries at the moment.

I'd propose to add the CA53 entries, first. And then add their L2 cache entries.

Based on the outcome of the discussion for the CA57 we have to see if we want to add the unused cache-unified and cache-level, then, too.

Hi Dirk,

Quoted 24 lines · Dirk Behme

Quoted 23 lines · Geert Uytterhoeven

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes".

---
   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
   1 file changed, 6 insertions(+)

arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0

index c07f4e83b988ba42..c572527afec3403a 100644
@@ -72,6 +72,12 @@
                 cache-level = <2>;
         };
 

Quoted 9 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 80

Quoted 6 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi +6 -0

+       L2_CA53: cache-controller at 1 {
+               compatible = "cache";
+               cache-unified;
+               cache-level = <2>;
+       };
+

As we don't have any CA53 in the device tree yet, and it was rejected to add it, I'd think that we don't want these unused entries at the moment.

This is a preparatory step for adding the SYSC PM Domains.

Quoted 5 lines

I'd propose to add the CA53 entries, first. And then add their L2 cache entries.

Based on the outcome of the discussion for the CA57 we have to see if we want to add the unused cache-unified and cache-level, then, too.

These are specified by ePAPR, as I said before.
Remember, DT describes the hardware, not what Linux (or any other OS) is using.

Hi Dirk,

On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <[email protected]> wrote:

Quoted 3 lines

As we don't have any CA53 in the device tree yet, and it was rejected to add it, I'd think that we don't want these unused entries at the moment.

This is a preparatory step for adding the SYSC PM Domains.

Quoted 3 lines

I'd propose to add the CA53 entries, first. And then add their L2 cache entries.

Quoted 2 lines

Based on the outcome of the discussion for the CA57 we have to see if we want to add the unused cache-unified and cache-level, then, too.

These are specified by ePAPR, as I said before.
Remember, DT describes the hardware, not what Linux (or any other OS) is using.

Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the DTSes for various Renesas ARM-based SoCs, or completes the existing nodes, and links the CPU nodes to them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to the respective (already existing) SYSC Power Domains. Fortunately these Power Domains were never powered down, as they are parents of the Power Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for adding SYSC Power Domain support later.

Changes compared to v2:
- Dropped "arm,data-latency" and "arm,tag-latency" properties, as they may not be valid when using virtualization,
- Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
r8a7795: Add L2 cache-controller nodes",
- Changed one-line summary prefix to match current arm-soc practices.

This series is against renesas-devel-20160215-v4.5-rc4.
It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and r8a7795/salvator-x.

For your convenience, I've also pushed this series to
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3

Thanks for applying!

Geert Uytterhoeven (7):
ARM: dts: r8a73a4: Add L2 cache-controller nodes
ARM: dts: r8a7790: Add L2 cache-controller nodes
ARM: dts: r8a7791: Add L2 cache-controller node
ARM: dts: r8a7793: Add L2 cache-controller node
ARM: dts: r8a7794: Add L2 cache-controller node
arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
arm64: dts: r8a7795: Add CA53 L2 cache-controller node