Add support for 96boards Dragonboard410C board

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by

Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string

 doc/device-tree-bindings/gpio/gpio-msm.txt |  22 +++++
 drivers/gpio/Kconfig                       |  14 +++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/msm_gpio.c                    | 135 +++++++++++++++++++++++++++++
 4 files changed, 172 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
 create mode 100644 drivers/gpio/msm_gpio.c

doc/device-tree-bindings/gpio/gpio-msm.txt new file +6 -0

new file mode 100644
index 0000000..966ce0a
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+       This controller is called "Top Level Mode Multiplexing" in

doc/device-tree-bindings/gpio/gpio-msm.txt new file +6 -0

+       reg = <0x1000000 0x300000>;
+       gpio-controller;
+       gpio-count = <122>;
+       gpio-bank-name="soc";
+       #gpio-cells = <1>;
+};

drivers/gpio/Kconfig +14 -0

index 845dc72..a5e8182 100644
@@ -46,6 +46,20 @@ config LPC32XX_GPIO
        help
          Support for the LPC32XX GPIO driver.
 
+config MSM_GPIO
+       bool "Qualcomm GPIO driver"
+       depends on DM_GPIO
+       default n
+       help
+         Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+         This controller have single bank (default name "soc"), every
+         gpio has it's own set of registers.
+         Only simple GPIO operations are supported (get/set, change of
+         direction and checking pin function).
+         Supported devices:
+         - APQ8016
+         - MSM8916
+
 config ROCKCHIP_GPIO
        bool "Rockchip GPIO driver"
        depends on DM_GPIO

drivers/gpio/Makefile +1 -0

index 845a6d4..6083c4a 100644
@@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO)               += zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)      += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)       += hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)       += pic32_gpio.o
+obj-$(CONFIG_MSM_GPIO)         += msm_gpio.o

drivers/gpio/msm_gpio.c new file +135 -1

new file mode 100644
index 0000000..950f309
@@ -0,0 +1,135 @@
+/*
+ * Qualcomm GPIO driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define GPIO_CONFIG_OFF(no)         ((no) * 0x1000)
+#define GPIO_IN_OUT_OFF(no)         ((no) * 0x1000 + 0x4)
+
+/* OE */
+#define GPIO_OE_DISABLE  (0x0 << 9)
+#define GPIO_OE_ENABLE   (0x1 << 9)
+#define GPIO_OE_MASK     (0x1 << 9)
+
+/* GPIO_IN_OUT register shifts. */
+#define GPIO_IN          0
+#define GPIO_OUT         1
+
+struct msm_gpio_bank {
+       phys_addr_t base;
+};
+
+static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+       phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+       /* Disable OE bit */
+       clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+
+       return 0;
+}
+
+static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       value = !!value;
+       /* set value */
+       writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+
+       return 0;
+}
+
+static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+                                    int value)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+       phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
+
+       value = !!value;
+       /* set value */
+       writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+       /* switch direction */
+       clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
+
+       return 0;
+}
+
+static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
+}
+
+static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
+               return GPIOF_OUTPUT;
+
+       return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_msm_ops = {
+       .direction_input        = msm_gpio_direction_input,
+       .direction_output       = msm_gpio_direction_output,
+       .get_value              = msm_gpio_get_value,
+       .set_value              = msm_gpio_set_value,
+       .get_function           = msm_gpio_get_function,
+};
+
+static int msm_gpio_probe(struct udevice *dev)
+{
+       struct msm_gpio_bank *priv = dev_get_priv(dev);
+
+       priv->base = dev_get_addr(dev);
+
+       return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static int msm_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+                                            "gpio-count", 0);
+       uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+                                        "gpio-bank-name", NULL);
+       if (uc_priv->bank_name == NULL)
+               uc_priv->bank_name = "soc";
+
+       return 0;
+}
+
+static const struct udevice_id msm_gpio_ids[] = {
+       { .compatible = "qcom,msm8916-pinctrl" },
+       { .compatible = "qcom,apq8016-pinctrl" },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_msm) = {
+       .name   = "gpio_msm",
+       .id     = UCLASS_GPIO,
+       .of_match = msm_gpio_ids,
+       .ofdata_to_platdata = msm_gpio_ofdata_to_platdata,
+       .probe  = msm_gpio_probe,
+       .ops    = &gpio_msm_ops,
+       .priv_auto_alloc_size = sizeof(struct msm_gpio_bank),
+};
+
+
--

2.5.0

_______________________________________________
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Quoted 51 lines · Mateusz Kulikowski

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by

Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string

 doc/device-tree-bindings/gpio/gpio-msm.txt |  22 +++++
 drivers/gpio/Kconfig                       |  14 +++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/msm_gpio.c                    | 135 +++++++++++++++++++++++++++++
 4 files changed, 172 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
 create mode 100644 drivers/gpio/msm_gpio.c

doc/device-tree-bindings/gpio/gpio-msm.txt new file +13 -0

new file mode 100644
index 0000000..966ce0a
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+       This controller is called "Top Level Mode Multiplexing" in
+       Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:

doc/device-tree-bindings/gpio/gpio-msm.txt line 16

Quoted 3 lines

doc/device-tree-bindings/gpio/gpio-msm.txt new file +3 -0

+
+soc_gpios: pinctrl at 1000000 {
+       compatible = "qcom,msm8916-pinctrl";

Can't this driver goes into pinctrl (I mean gpio handling pincontrol), because Linux handle these gpio msm8916-pinctrl through pinctrl subsystem as per as I know, let me know in case if I miss anything here.

Hi,

Quoted 2 lines · Jagan Teki

On 8 February 2016 at 02:27, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 12 lines

Quoted 12 lines

doc/device-tree-bindings/gpio/gpio-msm.txt new file +12 -0

+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+       This controller is called "Top Level Mode Multiplexing" in
+       Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:

Quoted 8 lines

doc/device-tree-bindings/gpio/gpio-msm.txt line 16

Quoted 3 lines

doc/device-tree-bindings/gpio/gpio-msm.txt new file +3 -0

+
+soc_gpios: pinctrl at 1000000 {
+       compatible = "qcom,msm8916-pinctrl";

Can't this driver goes into pinctrl (I mean gpio handling pincontrol), because Linux handle these gpio msm8916-pinctrl through pinctrl subsystem as per as I know, let me know in case if I miss anything here.

I think Mateusz is planning to add this later. It would be good to get this in as a starting point for this platform.

Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add reviewed-by

Changes in v1:
- Added commit message
- Added DT binding documentation
- Added Kconfig help
- Reordered includes
- Dropped redundant fields from msm_sdhc
- Cleaned up clock init code (+ added error handling)
- Dropped mdelay - use wait_for_bit instead in reset code
- Added missing newline after declarations
- Added error handling if "reg" is missing
- Converted base address to pointer

 doc/device-tree-bindings/mmc/msm_sdhci.txt |  25 ++++
 drivers/mmc/Kconfig                        |   9 ++
 drivers/mmc/Makefile                       |   1 +
 drivers/mmc/msm_sdhci.c                    | 180 +++++++++++++++++++++++++++++
 4 files changed, 215 insertions(+)
 create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt
 create mode 100644 drivers/mmc/msm_sdhci.c

doc/device-tree-bindings/mmc/msm_sdhci.txt new file +25 -0

new file mode 100644
index 0000000..08a290c
@@ -0,0 +1,25 @@
+Qualcomm Snapdragon SDHCI controller
+
+Required properties:
+- compatible : "qcom,sdhci-msm-v4"
+- reg: Base address and length of registers:
+       - Host controller registers (SDHCI)
+       - SD Core registers
+- clock: interface clock (must accept SD bus clock as a frequency)
+
+Optional properties:
+- index: If there is more than one controller - controller index (required
+       by generic SDHCI code).
+- bus_width: Width of SD/eMMC bus (default 4)
+- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
+
+Example:
+
+sdhci at 07864000 {
+       compatible = "qcom,sdhci-msm-v4";
+       reg = <0x7864900 0x11c 0x7864000 0x800>;
+       index = <0x1>;
+       bus-width = <0x4>;
+       clock = <&clkc 1>;
+       clock-frequency = <200000000>;
+};

drivers/mmc/Kconfig +9 -0

index 9f4b766..e178935 100644
@@ -16,6 +16,15 @@ config DM_MMC
          appear as block devices in U-Boot and can support filesystems such
          as EXT4 and FAT.
 
+config MSM_SDHCI
+       bool "Qualcomm SDHCI controller"
+       depends on DM_MMC
+       help
+         Enables support for SDHCI 2.0 controller present on some Qualcomm
+          Snapdragon devices. This device is compatible with eMMC v4.5 and
+          SD 3.0 specifications. Both SD and eMMC devices are supported.
+         Card-detect gpios are not supported.
+
 config ROCKCHIP_DWMMC
        bool "Rockchip SD/MMC controller support"
        depends on DM_MMC && OF_CONTROL

drivers/mmc/Makefile +1 -0

index c9c3e3e..3df92f6 100644
@@ -49,3 +49,4 @@ else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
 obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o

drivers/mmc/msm_sdhci.c new file +27 -0

new file mode 100644
index 0000000..1e2a29b
@@ -0,0 +1,180 @@
+/*
+ * Qualcomm SDHCI driver - SD/eMMC controller
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Based on Linux driver
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <sdhci.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Non-standard registers needed for SDHCI startup */
+#define SDCC_MCI_POWER   0x0
+#define SDCC_MCI_POWER_SW_RST BIT(7)
+
+/* This is undocumented register */
+#define SDCC_MCI_VERSION             0x50
+#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
+#define SDCC_MCI_VERSION_MAJOR_MASK  (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
+#define SDCC_MCI_VERSION_MINOR_MASK  0xff

drivers/mmc/msm_sdhci.c new file +125 -0

+
+struct msm_sdhc {
+       struct sdhci_host host;
+       void *base;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_sdc_clk_init(struct udevice *dev)
+{
+       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+                                       "clock-frequency", 400000);
+       uint clkd[2]; /* clk_id and clk_no */
+       int clk_offset;
+       struct udevice *clk;
+       int ret;
+
+       ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
+                                  2);
+       if (ret)
+               return ret;
+
+       clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
+       if (clk_offset < 0)
+               return clk_offset;
+
+       ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+       if (ret)
+               return ret;
+
+       ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+
+static int msm_sdc_probe(struct udevice *dev)
+{
+       struct msm_sdhc *prv = dev_get_priv(dev);
+       struct sdhci_host *host = &prv->host;
+       u32 core_version, core_minor, core_major;
+       int ret;
+
+       host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+
+       /* Init clocks */
+       ret = msm_sdc_clk_init(dev);
+       if (ret)
+               return ret;
+
+       /* Reset the core and Enable SDHC mode */
+       writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
+              prv->base + SDCC_MCI_POWER);
+
+
+       /* Wait for reset to be written to register */
+       if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2,
+                        SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
+               printf("msm_sdhci: reset request failed\n");
+               return -EIO;
+       }
+
+       /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
+       if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER,
+                        SDCC_MCI_POWER_SW_RST, false, 2, false)) {
+               printf("msm_sdhci: stuck in reset\n");
+               return -ETIMEDOUT;
+       }
+
+       /* Enable host-controller mode */
+       writel(1, prv->base + SDCC_MCI_HC_MODE);
+
+       core_version = readl(prv->base + SDCC_MCI_VERSION);
+
+       core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
+       core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+
+       core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+
+       /*
+        * Support for some capabilities is not advertised by newer
+        * controller versions and must be explicitly enabled.
+        */
+       if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
+               u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+               caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
+               writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
+       }
+
+       /* Set host controller version */
+       host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+       /* automatically detect max and min speed */
+       return add_sdhci(host, 0, 0);
+}
+
+static int msm_sdc_remove(struct udevice *dev)
+{
+       struct msm_sdhc *priv = dev_get_priv(dev);
+
+        /* Disable host-controller mode */
+       writel(0, priv->base + SDCC_MCI_HC_MODE);
+
+       return 0;
+}
+
+static int msm_ofdata_to_platdata(struct udevice *dev)
+{
+       struct udevice *parent = dev->parent;
+       struct msm_sdhc *priv = dev_get_priv(dev);
+       struct sdhci_host *host = &priv->host;
+
+       host->name = strdup(dev->name);
+       host->ioaddr = (void *)dev_get_addr(dev);
+       host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+                                        "bus-width", 4);
+       host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+       priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+                                                             parent->of_offset,
+                                                             dev->of_offset,
+                                                             "reg", 1, NULL);
+       if (priv->base == (void *)FDT_ADDR_T_NONE ||
+           host->ioaddr == (void *)FDT_ADDR_T_NONE)
+               return -EINVAL;

drivers/mmc/msm_sdhci.c new file +8 -1

+       .name           = "msm_sdc",
+       .id             = UCLASS_MMC,
+       .of_match       = msm_mmc_ids,
+       .ofdata_to_platdata = msm_ofdata_to_platdata,
+       .probe          = msm_sdc_probe,
+       .remove         = msm_sdc_remove,
+       .priv_auto_alloc_size = sizeof(struct msm_sdhc),
+};
--

2.5.0

On 8 February 2016 at 02:27, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 14 lines

drivers/mmc/msm_sdhci.c new file +14 -0

+/* Non-standard registers needed for SDHCI startup */
+#define SDCC_MCI_POWER   0x0
+#define SDCC_MCI_POWER_SW_RST BIT(7)
+
+/* This is undocumented register */
+#define SDCC_MCI_VERSION             0x50
+#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
+#define SDCC_MCI_VERSION_MAJOR_MASK  (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
+#define SDCC_MCI_VERSION_MINOR_MASK  0xff
+
+#define SDCC_MCI_STATUS2 0x6C
+#define SDCC_MCI_STATUS2_MCI_ACT 0x1
+#define SDCC_MCI_HC_MODE 0x78
+

drivers/mmc/msm_sdhci.c line 37

Quoted 5 lines

drivers/mmc/msm_sdhci.c new file +5 -0

+/* Offset to SDHCI registers */
+#define SDCC_SDHCI_OFFSET 0x900
+
+/* Non standard (?) SDHCI register */
+#define SDHCI_VENDOR_SPEC_CAPABILITIES0  0x11c

IMHO, since this is based on Linux please use similar macro's to make easy changes in future.

drivers/mmc/msm_sdhci.c line 172

Quoted 7 lines

drivers/mmc/msm_sdhci.c new file +7 -0

+
+static const struct udevice_id msm_mmc_ids[] = {
+       { .compatible = "qcom,sdhci-msm-v4" },
+       { }
+};
+
+U_BOOT_DRIVER(msm_sdc_drv) = {

Same as above - msm_sdhci_drv looks more readable and with below driver attributes as well.

The following options can be now enabled via defconfig:
- CONFIG_USB_ULPI
- CONFIG_USB_ULPI_VIEWPORT
- CONFIG_USB_ULPI_VIEWPORT_OMAP

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly.

Affected boards:
colibri_t20, harmony, mcx, mt_ventoux, twister,
zynq_(picozed, zc702, zc706, zed, zybo)

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs).

Signed-off-by Mateusz Kulikowski <[email protected]>

Acked-by Marek Vasut <[email protected]>

Tested-by Simon Glass <[email protected]>

Support SPMI arbiter on Qualcomm Snapdragon devices.

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Rename p -> priv (in write/read)
- Fix header ordering (again)
- Add reviewed-by

Changes in v1:
- add binding documentation and better Kconfig help
- Changed a bit mapping
- Change include order
- Use clrsetbits* where possible
- Add one more supported dts id
- Handle missing fields in dt properly

 doc/device-tree-bindings/spmi/spmi-msm.txt |  26 ++++
 drivers/spmi/Kconfig                       |   7 +-
 drivers/spmi/Makefile                      |   1 +
 drivers/spmi/spmi-msm.c                    | 189

 4 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 doc/device-tree-bindings/spmi/spmi-msm.txt
 create mode 100644 drivers/spmi/spmi-msm.c

doc/device-tree-bindings/spmi/spmi-msm.txt new file +26 -0

new file mode 100644
index 0000000..ae47673
@@ -0,0 +1,26 @@
+Qualcomm SPMI arbiter/bus driver
+
+This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
+
+Required properties:
+- compatible: "qcom,spmi-pmic-arb"
+- reg: Register block adresses and sizes for various parts of device:
+   1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
+   2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
+   3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
+
+Optional properties (if not set by parent):
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+All PMICs should be placed as a child nodes of bus arbiter.
+Automatic detection of childs is currently not supported.
+
+Example:
+
+spmi at 200f000 {
+       compatible = "qcom,spmi-pmic-arb";
+       reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
+       #address-cells = <0x1>;
+       #size-cells = <0x1>;
+};

drivers/spmi/Kconfig +6 -1

index c70d675..8d25b45 100644
@@ -8,11 +8,16 @@ config SPMI
          SPMI (System Power Management Interface) bus is used
          to connect PMIC devices on various SoCs.
 
+config SPMI_MSM
+       boolean "Support Qualcomm SPMI bus"
+       depends on SPMI
+       ---help---
+         Support SPMI bus implementation found on Qualcomm Snapdragon SoCs.
+
 config SPMI_SANDBOX
        boolean "Support for Sandbox SPMI bus"
        depends on SPMI
        ---help---
          Demo SPMI bus implementation. Emulates part of PM8916 as single
           slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
-
 endmenu

drivers/spmi/Makefile +1 -0

index 4ca65a9..c0b1220 100644
@@ -5,4 +5,5 @@
 #
 
 obj-$(CONFIG_SPMI)  += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
 obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o

drivers/spmi/spmi-msm.c new file +189 -1

new file mode 100644
index 0000000..0cef505
@@ -0,0 +1,189 @@
+/*
+ * Qualcomm SPMI bus driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Loosely based on Little Kernel driver
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <spmi/spmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARB_CHANNEL_OFFSET(n)          (0x4 * (n))
+#define SPMI_CH_OFFSET(chnl)           ((chnl) * 0x8000)
+
+#define SPMI_REG_CMD0                  0x0
+#define SPMI_REG_CONFIG                        0x4
+#define SPMI_REG_STATUS                        0x8
+#define SPMI_REG_WDATA                 0x10
+#define SPMI_REG_RDATA                 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT          27
+#define SPMI_CMD_SLAVE_ID_SHIFT                20
+#define SPMI_CMD_ADDR_SHIFT            12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT     4
+#define SPMI_CMD_BYTE_CNT_SHIFT                0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG    0x00
+#define SPMI_CMD_EXT_REG_READ_LONG     0x01
+
+#define SPMI_STATUS_DONE               0x1
+
+#define SPMI_MAX_CHANNELS      128
+#define SPMI_MAX_SLAVES                16
+#define SPMI_MAX_PERIPH                256
+
+struct msm_spmi_priv {
+       phys_addr_t arb_chnl; /* ARB channel mapping base */
+       phys_addr_t spmi_core; /* SPMI core */
+       phys_addr_t spmi_obs; /* SPMI observer */
+       /* SPMI channel map */
+       uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+};
+
+static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
+                         uint8_t val)
+{
+       struct msm_spmi_priv *priv = dev_get_priv(dev);
+       unsigned channel;
+       uint32_t reg = 0;
+
+       if (usid >= SPMI_MAX_SLAVES)
+               return -EIO;
+       if (pid >= SPMI_MAX_PERIPH)
+               return -EIO;
+
+       channel = priv->channel_map[usid][pid];
+
+       /* Disable IRQ mode for the current channel*/
+       writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
+              SPMI_REG_CONFIG);
+
+       /* Write single byte */
+       writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+
+       /* Prepare write command */
+       reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
+       reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+       reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+       reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+       reg |= 1; /* byte count */
+
+       /* Send write command */
+       writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+       /* Wait till CMD DONE status */
+       reg = 0;
+       while (!reg) {
+               reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+                           SPMI_REG_STATUS);
+       }
+
+       if (reg ^ SPMI_STATUS_DONE) {
+               printf("SPMI write failure.\n");
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+       struct msm_spmi_priv *priv = dev_get_priv(dev);
+       unsigned channel;
+       uint32_t reg = 0;
+
+       if (usid >= SPMI_MAX_SLAVES)
+               return -EIO;
+       if (pid >= SPMI_MAX_PERIPH)
+               return -EIO;
+
+       channel = priv->channel_map[usid][pid];
+
+       /* Disable IRQ mode for the current channel*/
+       writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+
+       /* Prepare read command */
+       reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
+       reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+       reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+       reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+       reg |= 1; /* byte count */
+
+       /* Request read */
+       writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+       /* Wait till CMD DONE status */
+       reg = 0;
+       while (!reg) {
+               reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+                           SPMI_REG_STATUS);
+       }
+
+       if (reg ^ SPMI_STATUS_DONE) {
+               printf("SPMI read failure.\n");
+               return -EIO;
+       }
+
+       /* Read the data */
+       return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
+                    SPMI_REG_RDATA) & 0xFF;
+}
+
+static struct dm_spmi_ops msm_spmi_ops = {
+       .read = msm_spmi_read,
+       .write = msm_spmi_write,
+};
+
+static int msm_spmi_probe(struct udevice *dev)
+{
+       struct udevice *parent = dev->parent;
+       struct msm_spmi_priv *priv = dev_get_priv(dev);
+       int i;
+
+       priv->arb_chnl = dev_get_addr(dev);
+       priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+                                                          parent->of_offset,
+                                                          dev->of_offset,
+                                                          "reg", 1, NULL);
+       priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+                                                         parent->of_offset,
+                                                         dev->of_offset, "reg",
+                                                         2, NULL);
+       if (priv->arb_chnl == FDT_ADDR_T_NONE ||
+           priv->spmi_core == FDT_ADDR_T_NONE ||
+           priv->spmi_obs == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       /* Scan peripherals connected to each SPMI channel */
+       for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
+               uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
+               uint8_t slave_id = (periph & 0xf0000) >> 16;
+               uint8_t pid = (periph & 0xff00) >> 8;
+
+               priv->channel_map[slave_id][pid] = i;
+       }
+       return 0;
+}
+
+static const struct udevice_id msm_spmi_ids[] = {
+       { .compatible = "qcom,spmi-pmic-arb" },
+       { }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+       .name = "msm_spmi",
+       .id = UCLASS_SPMI,
+       .of_match = msm_spmi_ids,
+       .ops = &msm_spmi_ops,
+       .probe = msm_spmi_probe,
+       .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
+};
--

2.5.0

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

On 8 February 2016 at 02:27, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 4 lines

 doc/device-tree-bindings/spmi/spmi-msm.txt |  26 ++++
 drivers/spmi/Kconfig                       |   7 +-
 drivers/spmi/Makefile                      |   1 +
 drivers/spmi/spmi-msm.c                    | 189

spmi-pmic-arb.c looks fine along with binding file name as well.

This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add Reviewed-by

Changes in v1:
- Add binding doc
- Fixed inlcude ordering
- Merged direction_input and direction_output functions
- gpio_get: use switch instead of stacked if
- use pmic_clrsetbits
- add possibility to change prwkey bank name
- Handle invalid bindings
- Sanity HW check (i.e. check type/subtype registers)

 doc/device-tree-bindings/gpio/pm8916_gpio.txt |  48 ++++
 drivers/gpio/Kconfig                          |  10 +
 drivers/gpio/Makefile                         |   1 +

drivers/gpio/pm8916_gpio.c

 4 files changed, 361 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/pm8916_gpio.txt
 create mode 100644 drivers/gpio/pm8916_gpio.c

doc/device-tree-bindings/gpio/pm8916_gpio.txt new file +48 -0

new file mode 100644
index 0000000..58185b8
@@ -0,0 +1,48 @@
+Driver for part of pm8916 PMIC - gpio and power/reset keys
+
+This device should be child of SPMI pmic.
+
+1) GPIO driver
+
+Required properties:
+- compatible: "qcom,pm8916-gpio"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- gpio-count: number of GPIOs
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916" is used)
+
+Example:
+
+pmic_gpios: gpios at c000 {
+       compatible = "qcom,pm8916-gpio";
+       reg = <0xc000 0x400>;
+       gpio-controller;
+       gpio-count = <4>;
+       #gpio-cells = <2>;
+       gpio-bank-name="pmic";
+};
+
+
+2) Power/Reset key driver
+
+Required properties:
+- compatible: "qcom,pm8916-pwrkey"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916_key" is used)
+
+
+Example:
+
+pmic_pon: pon at 800 {
+       compatible = "qcom,pm8916-pwrkey";
+       reg = <0x800 0x96>;
+       #gpio-cells = <2>;
+       gpio-controller;
+};

drivers/gpio/Kconfig +10 -0

index a5e8182..bbafc63 100644
@@ -60,6 +60,16 @@ config MSM_GPIO
          - APQ8016
          - MSM8916
 
+config PM8916_GPIO
+       bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
+       depends on DM_GPIO && PMIC_PM8916
+       help
+         Support for GPIO pins and power/reset buttons found on
+         Qualcomm PM8916 PMIC.
+         Default name for GPIO bank is "pm8916".
+         Power and reset buttons are placed in "pm8916_key" bank and
+          have gpio numbers 0 and 1 respectively.
+
 config ROCKCHIP_GPIO
        bool "Rockchip GPIO driver"
        depends on DM_GPIO

drivers/gpio/Makefile +1 -0

index 6083c4a..8e880bd 100644
@@ -48,3 +48,4 @@ obj-$(CONFIG_VYBRID_GPIO)     += vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)       += hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)       += pic32_gpio.o
 obj-$(CONFIG_MSM_GPIO)         += msm_gpio.o
+obj-$(CONFIG_PM8916_GPIO)      += pm8916_gpio.o

drivers/gpio/pm8916_gpio.c new file +302 -1

new file mode 100644
index 0000000..1abab7f
@@ -0,0 +1,302 @@
+/*
+ * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <spmi/spmi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offset for each gpio */
+#define REG_OFFSET(x)          ((x) * 0x100)
+
+/* Register maps */
+
+/* Type and subtype are shared for all pm8916 peripherals */
+#define REG_TYPE               0x4
+#define REG_SUBTYPE            0x5
+
+#define REG_STATUS             0x08
+#define REG_STATUS_VAL_MASK    0x1
+
+/* MODE_CTL */
+#define REG_CTL           0x40
+#define REG_CTL_MODE_MASK       0x70
+#define REG_CTL_MODE_INPUT      0x00
+#define REG_CTL_MODE_INOUT      0x20
+#define REG_CTL_MODE_OUTPUT     0x10
+#define REG_CTL_OUTPUT_MASK     0x0F
+
+#define REG_DIG_VIN_CTL        0x41
+#define REG_DIG_VIN_VIN0       0
+
+#define REG_DIG_PULL_CTL       0x42
+#define REG_DIG_PULL_NO_PU     0x5
+
+#define REG_DIG_OUT_CTL        0x45
+#define REG_DIG_OUT_CTL_CMOS   (0x0 << 4)
+#define REG_DIG_OUT_CTL_DRIVE_L 0x1
+
+#define REG_EN_CTL             0x46
+#define REG_EN_CTL_ENABLE      (1 << 7)
+
+struct pm8916_gpio_bank {
+       uint16_t pid; /* Peripheral ID on SPMI bus */
+};
+
+static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
+                                    bool input, int value)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+       int ret;
+
+       /* Disable the GPIO */
+       ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
+                             REG_EN_CTL_ENABLE, 0);
+       if (ret < 0)
+               return ret;
+
+       /* Select the mode */
+       if (input)
+               ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
+                                    REG_CTL_MODE_INPUT);
+       else
+               ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
+                                    REG_CTL_MODE_INOUT | (value ? 1 : 0));
+       if (ret < 0)
+               return ret;
+
+       /* Set the right pull (no pull) */
+       ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+                            REG_DIG_PULL_NO_PU);
+       if (ret < 0)
+               return ret;
+
+       /* Configure output pin drivers if needed */
+       if (!input) {
+               /* Select the VIN - VIN0, pin is input so it doesn't matter */
+               ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+                                    REG_DIG_VIN_VIN0);
+               if (ret < 0)
+                       return ret;
+
+               /* Set the right dig out control */
+               ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
+                                    REG_DIG_OUT_CTL_CMOS |
+                                    REG_DIG_OUT_CTL_DRIVE_L);
+               if (ret < 0)
+                       return ret;
+       }
+
+       /* Enable the GPIO */
+       return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
+                              REG_EN_CTL_ENABLE);
+}
+
+static int pm8916_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+       return pm8916_gpio_set_direction(dev, offset, true, 0);
+}
+
+static int pm8916_gpio_direction_output(struct udevice *dev, unsigned offset,
+                                       int value)
+{
+       return pm8916_gpio_set_direction(dev, offset, false, value);
+}
+
+static int pm8916_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+       int reg;
+
+       /* Set the output value of the gpio */
+       reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
+       if (reg < 0)
+               return reg;
+
+       switch (reg & REG_CTL_MODE_MASK) {
+       case REG_CTL_MODE_INPUT:
+               return GPIOF_INPUT;
+       case REG_CTL_MODE_INOUT: /* Fallthrough */
+       case REG_CTL_MODE_OUTPUT:
+               return GPIOF_OUTPUT;
+       default:
+               return GPIOF_UNKNOWN;
+       }
+}
+
+static int pm8916_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+       int reg;
+
+       reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
+       if (reg < 0)
+               return reg;
+
+       return !!(reg & REG_STATUS_VAL_MASK);
+}
+
+static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset,
+                                int value)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
+
+       /* Set the output value of the gpio */
+       return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
+                              REG_CTL_OUTPUT_MASK, !!value);
+}
+
+static const struct dm_gpio_ops pm8916_gpio_ops = {
+       .direction_input        = pm8916_gpio_direction_input,
+       .direction_output       = pm8916_gpio_direction_output,
+       .get_value              = pm8916_gpio_get_value,
+       .set_value              = pm8916_gpio_set_value,
+       .get_function           = pm8916_gpio_get_function,
+};
+
+static int pm8916_gpio_probe(struct udevice *dev)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       int reg;
+
+       priv->pid = dev_get_addr(dev);
+       if (priv->pid == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       /* Do a sanity check */
+       reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
+       if (reg != 0x10)
+               return -ENODEV;
+
+       reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
+       if (reg != 0x5)
+               return -ENODEV;
+
+       return 0;
+}
+
+static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+                                            "gpio-count", 0);
+       uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+                                        "gpio-bank-name", NULL);
+       if (uc_priv->bank_name == NULL)
+               uc_priv->bank_name = "pm8916";
+
+       return 0;
+}
+
+static const struct udevice_id pm8916_gpio_ids[] = {
+       { .compatible = "qcom,pm8916-gpio" },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_pm8916) = {
+       .name   = "gpio_pm8916",
+       .id     = UCLASS_GPIO,
+       .of_match = pm8916_gpio_ids,
+       .ofdata_to_platdata = pm8916_gpio_ofdata_to_platdata,
+       .probe  = pm8916_gpio_probe,
+       .ops    = &pm8916_gpio_ops,
+       .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
+
+
+/* Add pmic buttons as GPIO as well - there is no generic way for now */
+#define PON_INT_RT_STS                        0x10
+#define KPDPWR_ON_INT_BIT                     0
+#define RESIN_ON_INT_BIT                      1
+
+static int pm8941_pwrkey_get_function(struct udevice *dev, unsigned offset)
+{
+       return GPIOF_INPUT;
+}
+
+static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+
+       int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
+
+       if (reg < 0)
+               return 0;
+
+       switch (offset) {
+       case 0: /* Power button */
+               return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
+               break;
+       case 1: /* Reset button */
+       default:
+               return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
+               break;
+       }
+}
+
+static const struct dm_gpio_ops pm8941_pwrkey_ops = {
+       .get_value              = pm8941_pwrkey_get_value,
+       .get_function           = pm8941_pwrkey_get_function,
+};
+
+static int pm8941_pwrkey_probe(struct udevice *dev)
+{
+       struct pm8916_gpio_bank *priv = dev_get_priv(dev);
+       int reg;
+
+       priv->pid = dev_get_addr(dev);
+       if (priv->pid == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       /* Do a sanity check */
+       reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
+       if (reg != 0x1)
+               return -ENODEV;
+
+       reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
+       if (reg != 0x1)
+               return -ENODEV;
+
+       return 0;
+}
+
+static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->gpio_count = 2;
+       if (uc_priv->bank_name == NULL)
+               uc_priv->bank_name = "pm8916_key";
+
+       return 0;
+}
+
+static const struct udevice_id pm8941_pwrkey_ids[] = {
+       { .compatible = "qcom,pm8916-pwrkey" },
+       { }
+};
+
+U_BOOT_DRIVER(pwrkey_pm8941) = {
+       .name   = "pwrkey_pm8916",
+       .id     = UCLASS_GPIO,
+       .of_match = pm8941_pwrkey_ids,
+       .ofdata_to_platdata = pm8941_pwrkey_ofdata_to_platdata,
+       .probe  = pm8941_pwrkey_probe,
+       .ops    = &pm8941_pwrkey_ops,
+       .priv_auto_alloc_size = sizeof(struct pm8916_gpio_bank),
+};
--

2.5.0

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

On 8 February 2016 at 02:27, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 6 lines

- Sanity HW check (i.e. check type/subtype registers)

 doc/device-tree-bindings/gpio/pm8916_gpio.txt |  48 ++++
 drivers/gpio/Kconfig                          |  10 +
 drivers/gpio/Makefile                         |   1 +

drivers/gpio/pm8916_gpio.c

               | 302 ++++++++++++++++++++++++++

4 GPIO's pin design, I think this is also comes under pincontrol.

First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

---

Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Make MND divider comments more compact :)
- p -> priv
- Add reviewed-by
- Reordered Kconfig to keep alphabetical order
- Renamed reset_sandbox -> msm_reset (typo in reset.c)

Changes in v1:
- Fix include order
- Cleanup defines (added spaces for readibility)
- Base address is integer to avoid casting
- Use setbits_* family where possible
- Drop unneded comments, added newlines where needed
- Check return value of dev_get_addr
- Add binding for apq8016
- Cleaned up divider calculation
- Drop most of gpio.h (only empty file is needed)

 arch/arm/Kconfig                                   |  12 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/mach-snapdragon/Kconfig                   |   6 +
 arch/arm/mach-snapdragon/Makefile                  |   8 +
 arch/arm/mach-snapdragon/clock-apq8016.c           | 262 +++++++++++++++++++++
 arch/arm/mach-snapdragon/include/mach/gpio.h       |   9 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  14 ++
 arch/arm/mach-snapdragon/reset.c                   |  40 ++++
 8 files changed, 352 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/Kconfig
 create mode 100644 arch/arm/mach-snapdragon/Makefile
 create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
 create mode 100644 arch/arm/mach-snapdragon/reset.c

arch/arm/Kconfig +12 -0

index d2dbb1a..f16d0d9 100644
@@ -504,6 +504,16 @@ config RMOBILE
        bool "Renesas ARM SoCs"
        select CPU_V7
 
+config ARCH_SNAPDRAGON
+       bool "Qualcomm Snapdragon SoCs"
+       select ARM64
+       select DM
+       select DM_GPIO
+       select DM_SERIAL
+       select SPMI
+       select OF_CONTROL
+       select OF_SEPARATE
+
 config ARCH_SOCFPGA
        bool "Altera SOCFPGA family"
        select CPU_V7

@@ -760,6 +770,8 @@ source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
 
+source "arch/arm/mach-snapdragon/Kconfig"
+
 source "arch/arm/mach-socfpga/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"

arch/arm/Makefile +1 -0

index cd7d880..661de56 100644
@@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_MVEBU)          += mvebu
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)              += orion5x
 machine-$(CONFIG_ARCH_S5PC1XX)         += s5pc1xx
+machine-$(CONFIG_ARCH_SNAPDRAGON)      += snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)         += socfpga
 machine-$(CONFIG_ARCH_ROCKCHIP)                += rockchip
 machine-$(CONFIG_STM32)                        += stm32

arch/arm/mach-snapdragon/Kconfig new file +6 -0

new file mode 100644
index 0000000..156e733
@@ -0,0 +1,6 @@
+if ARCH_SNAPDRAGON
+
+config SYS_SOC
+       default "snapdragon"
+
+endif

arch/arm/mach-snapdragon/Makefile new file +8 -0

new file mode 100644
index 0000000..8e84705
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += clock-apq8016.o
+obj-y += reset.o

arch/arm/mach-snapdragon/clock-apq8016.c new file +262 -0

new file mode 100644
index 0000000..d548d75
@@ -0,0 +1,262 @@
+/*
+ * Clock drivers for Qualcomm APQ8016
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * Based on Little Kernel driver, simplified
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS        0x2101C
+#define GPLL0_STATUS_ACTIVE BIT(17)
+
+#define APCS_GPLL_ENA_VOTE  0x45000
+#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
+
+/* vote reg for blsp1 clock */
+#define APCS_CLOCK_BRANCH_ENA_VOTE  0x45004
+#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
+
+/* SDC(n) clock control registers; n=1,2 */
+
+/* block control register */
+#define SDCC_BCR(n)                 ((n * 0x1000) + 0x41000)
+/* cmd */
+#define SDCC_CMD_RCGR(n)            ((n * 0x1000) + 0x41004)
+/* cfg */
+#define SDCC_CFG_RCGR(n)            ((n * 0x1000) + 0x41008)
+/* m */
+#define SDCC_M(n)                   ((n * 0x1000) + 0x4100C)
+/* n */
+#define SDCC_N(n)                   ((n * 0x1000) + 0x41010)
+/* d */
+#define SDCC_D(n)                   ((n * 0x1000) + 0x41014)
+/* branch control */
+#define SDCC_APPS_CBCR(n)           ((n * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n)            ((n * 0x1000) + 0x4101C)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR              0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR             0x3028
+#define BLSP1_UART2_APPS_CBCR       0x302C
+#define BLSP1_UART2_APPS_CMD_RCGR   0x3034
+#define BLSP1_UART2_APPS_CFG_RCGR   0x3038
+#define BLSP1_UART2_APPS_M          0x303C
+#define BLSP1_UART2_APPS_N          0x3040
+#define BLSP1_UART2_APPS_D          0x3044
+
+/* CBCR register fields */
+#define CBCR_BRANCH_ENABLE_BIT  BIT(0)
+#define CBCR_BRANCH_OFF_BIT     BIT(31)
+
+struct msm_clk_priv {
+       phys_addr_t base;
+};
+
+/* Enable clock controlled by CBC soft macro */
+static void clk_enable_cbc(phys_addr_t cbcr)
+{
+       setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
+
+       while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
+               ;
+}
+
+/* clock has 800MHz */
+static void clk_enable_gpll0(phys_addr_t base)
+{
+       if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
+               return; /* clock already enabled */
+
+       setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
+
+       while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
+               ;
+}
+
+#define APPS_CMD_RGCR_UPDATE BIT(0)
+
+/* Update clock command via CMD_RGCR */
+static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
+{
+       setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
+
+       /* Wait for frequency to be updated. */
+       while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
+               ;
+}
+
+struct bcr_regs {
+       uintptr_t cfg_rcgr;
+       uintptr_t cmd_rcgr;
+       uintptr_t M;
+       uintptr_t N;
+       uintptr_t D;
+};
+
+/* RCGR_CFG register fields */
+#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
+
+/* sources */
+#define CFG_CLK_SRC_CXO   (0 << 8)
+#define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_MASK  (7 << 8)
+
+/* Mask for supported fields */
+#define CFG_MASK 0x3FFF
+
+#define CFG_DIVIDER_MASK 0x1F
+
+/* root set rate for clocks with half integer and MND divider */
+static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+                                int div, int m, int n, int source)
+{
+       uint32_t cfg;
+       /* M value for MND divider. */
+       uint32_t m_val = m;
+       /* NOT(N-M) value for MND divider. */
+       uint32_t n_val = ~((n)-(m)) * !!(n);
+       /* NOT 2D value for MND divider. */
+       uint32_t d_val = ~(n);
+
+       /* Program MND values */
+       writel(m_val, base + regs->M);
+       writel(n_val, base + regs->N);
+       writel(d_val, base + regs->D);
+
+       /* setup src select and divider */
+       cfg  = readl(base + regs->cfg_rcgr);
+       cfg &= ~CFG_MASK;
+       cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
+
+       /* Set the divider; HW permits fraction dividers (+0.5), but
+          for simplicity, we will support integers only */
+       if (div)
+               cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
+
+       if (n_val)
+               cfg |= CFG_MODE_DUAL_EDGE;
+
+       writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+       /* Inform h/w to start using the new config. */
+       clk_bcr_update(base + regs->cmd_rcgr);
+}
+
+static const struct bcr_regs sdc_regs[] = {
+       {
+       .cfg_rcgr = SDCC_CFG_RCGR(1),
+       .cmd_rcgr = SDCC_CMD_RCGR(1),
+       .M = SDCC_M(1),
+       .N = SDCC_N(1),
+       .D = SDCC_D(1),
+       },
+       {
+       .cfg_rcgr = SDCC_CFG_RCGR(2),
+       .cmd_rcgr = SDCC_CMD_RCGR(2),
+       .M = SDCC_M(2),
+       .N = SDCC_N(2),
+       .D = SDCC_D(2),
+       }
+};
+
+/* Init clock for SDHCI controller */
+static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+{
+       int div = 8; /* 100MHz default */
+
+       if (rate == 200000000)
+               div = 4;
+
+       clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
+       /* 800Mhz/div, gpll0 */
+       clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
+                            CFG_CLK_SRC_GPLL0);
+       clk_enable_gpll0(priv->base);
+       clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
+
+       return rate;
+}
+
+static const struct bcr_regs uart2_regs = {
+       .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
+       .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
+       .M = BLSP1_UART2_APPS_M,
+       .N = BLSP1_UART2_APPS_N,
+       .D = BLSP1_UART2_APPS_D,
+};
+
+/* Init UART clock, 115200 */
+static int clk_init_uart(struct msm_clk_priv *priv)
+{
+       /* Enable iface clk */
+       clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+       /* 7372800 uart block clock @ GPLL0 */
+       clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
+                            CFG_CLK_SRC_GPLL0);
+       clk_enable_gpll0(priv->base);
+       /* Enable core clk */
+       clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+
+       return 0;
+}
+
+ulong msm_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+{
+       struct msm_clk_priv *priv = dev_get_priv(dev);
+
+       switch (periph) {
+       case 0: /* SDC1 */
+               return clk_init_sdc(priv, 0, rate);
+               break;
+       case 1: /* SDC2 */
+               return clk_init_sdc(priv, 1, rate);
+               break;
+       case 4: /* UART2 */
+               return clk_init_uart(priv);
+               break;
+       default:
+               return 0;
+       }
+}
+
+static int msm_clk_probe(struct udevice *dev)
+{
+       struct msm_clk_priv *priv = dev_get_priv(dev);
+
+       priv->base = dev_get_addr(dev);
+       if (priv->base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       return 0;
+}
+
+static struct clk_ops msm_clk_ops = {
+       .set_periph_rate = msm_set_periph_rate,
+};
+
+static const struct udevice_id msm_clk_ids[] = {
+       { .compatible = "qcom,gcc-msm8916" },
+       { .compatible = "qcom,gcc-apq8016" },
+       { }
+};
+
+U_BOOT_DRIVER(clk_msm) = {
+       .name           = "clk_msm",
+       .id             = UCLASS_CLK,
+       .of_match       = msm_clk_ids,
+       .ops            = &msm_clk_ops,
+       .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+       .probe          = msm_clk_probe,
+};

arch/arm/mach-snapdragon/include/mach/gpio.h new file +9 -0

new file mode 100644
index 0000000..ff949b2
@@ -0,0 +1,9 @@
+/*
+ * Empty gpio.h
+ *
+ * This file must stay as arch/arm/include/asm/gpio.h requires it.
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */

arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h new file +14 -0

new file mode 100644
index 0000000..cdbfad0
@@ -0,0 +1,14 @@
+/*
+ * Qualcomm APQ8916 sysmap
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8016_H
+#define _MACH_SYSMAP_APQ8016_H
+
+#define GICD_BASE 0x0b000000
+#define GICC_BASE 0x0a20c000
+
+#endif

arch/arm/mach-snapdragon/reset.c new file +40 -1

new file mode 100644
index 0000000..2627eec
@@ -0,0 +1,40 @@
+/*
+ * Qualcomm APQ8016 reset controller driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_reset_request(struct udevice *dev, enum reset_t type)
+{
+       phys_addr_t addr = dev_get_addr(dev);
+       if (!addr)
+               return -EINVAL;
+       writel(0, addr);
+       return -EINPROGRESS;
+}
+
+static struct reset_ops msm_reset_ops = {
+       .request        = msm_reset_request,
+};
+
+static const struct udevice_id msm_reset_ids[] = {
+       { .compatible = "qcom,pshold" },
+       { }
+};
+
+U_BOOT_DRIVER(msm_reset) = {
+       .name           = "msm_reset",
+       .id             = UCLASS_RESET,
+       .of_match       = msm_reset_ids,
+       .ops            = &msm_reset_ops,
+};
--

2.5.0

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

On 8 February 2016 at 02:27, Mateusz Kulikowski
<[email protected]> wrote:

Quoted 7 lines

 8 files changed, 352 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/Kconfig
 create mode 100644 arch/arm/mach-snapdragon/Makefile
 create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
 create mode 100644 arch/arm/mach-snapdragon/reset.c

I think mach-qcom looks readable, I understand snapdragon is an soc name but why can't we place all qcom soc code to mach-qcom (I think Linux also doing the same)?

U-Boot boots chained with fastboot in 64-bit mode.

board/qualcomm/dragonboard410c/head.S new file +18 -0

@@ -0,0 +1,28 @@
+/*
+ * Little-Kernel/Fastboot header for proper chain-loading
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.global _fastboot_header
+_fastboot_header:
+	b _start
+	add     x13, x18, #0x16
+	/* Image load offset from start of RAM, little-endian */
+	.quad   CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1
+	/* Effective size of kernel image, little-endian */
+	.quad   0 /* 0x60000 */

+6) generate qualcomm device tree, use dtbTool to generate it
+$ dtbTool -o dt.img arch/arm/dts
+
+7) generate image with mkbootimg:
+$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline=""

On Sun, Feb 07, 2016 at 09:57:37PM +0100, Mateusz Kulikowski wrote:

Quoted 17 lines

+.global _fastboot_header

board/qualcomm/dragonboard410c/head.S new file +16 -0

+_fastboot_header:
+	b _start
+	add     x13, x18, #0x16
+	/* Image load offset from start of RAM, little-endian */
+	.quad   CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1
+	/* Effective size of kernel image, little-endian */
+	.quad   0 /* 0x60000 */
+	/* Informative flags, little-endian */
+	.quad   0
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.byte   0x41                            /* Magic number, "ARM\x64" */
+	.byte   0x52
+	.byte   0x4d
+	.byte   0x64

board/qualcomm/dragonboard410c/head.S line 28

Quoted 1 line

board/qualcomm/dragonboard410c/head.S new file +1 -0

+	.word   0                               /* reserved */

I don't think fastboot is the correct term to use here. The structure in head.S is the ARM64 Linux kernel header described in section 4 of this
document: https://www.kernel.org/doc/Documentation/arm64/booting.txt
Fastboot is AFAIK a USB protocol spoken by bootloaders used on Android devices. Little Kernel can do fastboot, but it doesn't do it to run this image.

It is also confusing to have the "add" instruction in there without an explanation, especially because having it at offset 4 instead of 0 defeats its original purpose (MZ EXE signature for EFI).

Quoted 6 lines

+6) generate qualcomm device tree, use dtbTool to generate it
+$ dtbTool -o dt.img arch/arm/dts
+
+7) generate image with mkbootimg:
+$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline=""

I would have liked a bit more text about what is done with the device trees here. Little Kernel refuses to run the "kernel" unless it can find a device tree matching the hardware it is running on. It adds some information to the device tree and passes it to the kernel in the x0 register. U-Boot discards the contents of the x0 register and uses the device tree appended to its image. So there is no need to point dtbTool to the same dtb file used by U-Boot. A smaller one containing only the IDs checked by Little Kernel would be enough. And dtbTool does not generate a device tree, it generates the Qualcomm device tree table containing all dtb files in the directory.

I know the goal is to eventually replace Little Kernel, but how about using the device tree passed by it? We could add some code to head.S that saves x0 in sp_el0 and abuse CONFIG_OF_HOSTFILE to retrieve it.

Quoted 3 lines · Daniel Gl?ckner

It is also confusing to have the "add" instruction in there without an explanation, especially because having it at offset 4 instead of 0 defeats its original purpose (MZ EXE signature for EFI).

My bad, I should have put it the other way around:
add x13, x18, #0x16,
b _start

Will do that for v3

Quoted 3 lines

I know the goal is to eventually replace Little Kernel, but how about using the device tree passed by it? We could add some code to head.S that saves x0 in sp_el0 and abuse CONFIG_OF_HOSTFILE to retrieve it.

I prefer not to (at least for now) - It will not give us significant benefits (image will be a bit smaller and boot slightly faster, but it's not an issue as U-Boot replaces huge kernel image) and will just confuse people that already are using it. Is it fine with you?