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arm64: hip05: update

PATCH New Kefeng Wang 2 participants 9 messages Jan 29, 2016 – Feb 27, 2016

Subsystems (2)
Device tree bindings Arm/HiSilicon SoC support
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Kefeng Wang

author
#0 lore raw

cover arm64: hip05: update

Enable more feature in hip05 d02 board.

Kefeng Wang (6):
arm64: dts: hip05: Add L2 cache topology
arm64: dts: hip05: Use Cortex specific device node for pmu
arm64: dts: hip05: Append all gicv3 ITS entries
arm64: dts: hip05: Append gpio nodes
arm64: dts: hip05: Append power button node for D02 board
arm64: defconfig: Enable DesignWare APB GPIO controller

 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    | 92 ++++++++++++++++++++++++++++-
 arch/arm64/configs/defconfig                |  1 +
 3 files changed, 109 insertions(+), 2 deletions(-)
Signature · 1 line
2.6.0.GIT
author
#1 lore raw

PATCH 1/6 arm64: dts: hip05: Add L2 cache topology

The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus share one L2 cache, add them to the dtsi file so that the cache hierarchy can be probed.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
arch/arm64/boot/dts/hisilicon/hip05.dtsi +32 -0
index c1ea999..db2039d 100644
@@ -90,6 +90,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20000>;
 			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu1: cpu at 20001 {

@@ -97,6 +98,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20001>;
 			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu2: cpu at 20002 {

@@ -104,6 +106,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20002>;
 			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu3: cpu at 20003 {

@@ -111,6 +114,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20003>;
 			enable-method = "psci";
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu4: cpu at 20100 {

@@ -118,6 +122,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20100>;
 			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu5: cpu at 20101 {

@@ -125,6 +130,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20101>;
 			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu6: cpu at 20102 {

@@ -132,6 +138,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20102>;
 			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu7: cpu at 20103 {

@@ -139,6 +146,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20103>;
 			enable-method = "psci";
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu8: cpu at 20200 {

@@ -146,6 +154,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20200>;
 			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu9: cpu at 20201 {

@@ -153,6 +162,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20201>;
 			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu10: cpu at 20202 {

@@ -160,6 +170,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20202>;
 			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu11: cpu at 20203 {

@@ -167,6 +178,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20203>;
 			enable-method = "psci";
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu12: cpu at 20300 {

@@ -174,6 +186,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20300>;
 			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
 		};
 
 		cpu13: cpu at 20301 {

@@ -181,6 +194,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20301>;
 			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
 		};
 
 		cpu14: cpu at 20302 {

@@ -188,6 +202,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20302>;
 			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
 		};
 
 		cpu15: cpu at 20303 {

@@ -195,6 +210,23 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x20303>;
 			enable-method = "psci";
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
 		};
 	};
Signature · 1 line
2.6.0.GIT
author
#2 lore raw

PATCH 2/6 arm64: dts: hip05: Use Cortex specific device node for pmu

In reply to Kefeng Wang

Instead of using the generic armv8-pmuv3 compatibility, use the more specific Cortex A57 compatibility.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/hisilicon/hip05.dtsi +1 -1
index db2039d..ed31f19 100644
@@ -262,7 +262,7 @@
 	};
 
 	pmu {
-		compatible = "arm,armv8-pmuv3";
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 	};
Signature · 1 line
2.6.0.GIT
author
#3 lore raw

PATCH 3/6 arm64: dts: hip05: Append all gicv3 ITS entries

In reply to Kefeng Wang

There are four subsystems in hip05 soc, peri/m3/pcie/dsa, each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/hisilicon/hip05.dtsi +19 -1
index ed31f19..c1b1a32 100644
@@ -246,11 +246,29 @@
 		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-		its_totems: interrupt-controller at 8c000000 {
+		its_peri: interrupt-controller at 8c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			reg = <0x0 0x8c000000 0x0 0x40000>;
 		};
+
+		its_m3: interrupt-controller at a3000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xa3000000 0x0 0x40000>;
+		};
+
+		its_pcie: interrupt-controller at b7000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xb7000000 0x0 0x40000>;
+		};
+
+		its_dsa: interrupt-controller at c6000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xc6000000 0x0 0x40000>;
+		};
 	};
 
 	timer {
Signature · 1 line
2.6.0.GIT
author
#4 lore raw

PATCH 4/6 arm64: dts: hip05: Append gpio nodes

In reply to Kefeng Wang

There are two dw GPIO controllers in hip05 peri sub, this patch adds the corresponding device tree nodes.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 38 ++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
arch/arm64/boot/dts/hisilicon/hip05.dtsi +38 -0
index c1b1a32..6319ff3 100644
@@ -322,5 +322,43 @@
 			reg-io-width = <4>;
 			status = "disabled";
 		};
+
+		peri_gpio0: gpio at 802e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x802e0000 0x0 0x10000>;
+			status = "disabled";
+
+			porta: gpio-controller at 0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		peri_gpio1: gpio at 802f0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x802f0000 0x0 0x10000>;
+			status = "disabled";
+
+			portb: gpio-controller at 0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
 	};
 };
Signature · 1 line
2.6.0.GIT
author
#5 lore raw

PATCH 5/6 arm64: dts: hip05: Append power button node for D02 board

In reply to Kefeng Wang

This patch adds poweroff button device node to support poweroff feature on hip05 d02 board.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/hisilicon/hip05-d02.dts +18 -0
index ae34e25..e9436c0 100644
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "hip05.dtsi"
 
 / {

@@ -29,8 +30,25 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pwrbutton {
+			label = "Power Button";
+			gpios = <&porta 8 GPIO_ACTIVE_LOW>;
+			linux,code = <116>;
+			debounce-interval = <0>;
+		};
+	};
 };
 
 &uart0 {
 	status = "ok";
 };
+
+&peri_gpio0 {
+	status = "ok";
+};
Signature · 1 line
2.6.0.GIT
author
#6 lore raw

PATCH 6/6 arm64: defconfig: Enable DesignWare APB GPIO controller

In reply to Kefeng Wang

The Synopsys DesignWare APB GPIO controller is used by several vender's socs, like apm/marvell/altera/hisilicon, enable it by default.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
index 86581f7..3380a04 100644
@@ -145,6 +145,7 @@ CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_QUP=y
 CONFIG_PINCTRL_MSM8916=y
+CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_PL061=y
 CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_XGENE=y
Signature · 1 line
2.6.0.GIT
author
#7 lore raw

cover arm64: hip05: update

In reply to Kefeng Wang

Ping, any comments, thanks.

Quoted 15 lines · Kefeng Wang

Enable more feature in hip05 d02 board.

Kefeng Wang (6):
arm64: dts: hip05: Add L2 cache topology
arm64: dts: hip05: Use Cortex specific device node for pmu
arm64: dts: hip05: Append all gicv3 ITS entries
arm64: dts: hip05: Append gpio nodes
arm64: dts: hip05: Append power button node for D02 board
arm64: defconfig: Enable DesignWare APB GPIO controller

 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    | 92 ++++++++++++++++++++++++++++-
 arch/arm64/configs/defconfig                |  1 +
 3 files changed, 109 insertions(+), 2 deletions(-)
maintainer Applied
#8 lore raw

cover arm64: hip05: update

In reply to Kefeng Wang

Hi Kefeng,

Quoted 10 lines · Kefeng Wang

Enable more feature in hip05 d02 board.

Kefeng Wang (6):
arm64: dts: hip05: Add L2 cache topology
arm64: dts: hip05: Use Cortex specific device node for pmu
arm64: dts: hip05: Append all gicv3 ITS entries
arm64: dts: hip05: Append gpio nodes
arm64: dts: hip05: Append power button node for D02 board
arm64: defconfig: Enable DesignWare APB GPIO controller

Quoted 5 lines
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    | 92 ++++++++++++++++++++++++++++-
 arch/arm64/configs/defconfig                |  1 +
 3 files changed, 109 insertions(+), 2 deletions(-)

Applied all the patches into the hisilicon soc tree. Thanks!

Best Regards,
Wei