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iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

PATCH Superseded Tirumalesh Chalamarla 2 participants 4 messages Mar 4, 2016

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Tirumalesh Chalamarla

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#0 lore raw

PATCH v4 1/1 iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3.

This patch make sures ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
- Removed redundent variable.

changes from V2:
- removed *_base from DT, and replaced with compatible string

changes from V1:
- rebased on top of 16 bit VMID patch
- removed redundent options from DT
- insted of transform, DT now supplies starting ASID/VMID

Signed-off-by Tirumalesh Chalamarla <[email protected]>
Signed-off-by Akula Geethasowjanya <[email protected]>
---
 Documentation/arm64/silicon-errata.txt             |  1 +
 .../devicetree/bindings/iommu/arm,smmu.txt         |  1 +
 drivers/iommu/arm-smmu.c                           | 43 ++++++++++++++++------
 3 files changed, 34 insertions(+), 11 deletions(-)
Documentation/arm64/silicon-errata.txt +1 -0
index 58b71dd..3747a4b 100644
@@ -56,3 +56,4 @@ stable kernels.
 |                |                 |                 |                         |
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
+| Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1 -0
index 7180745..19fe6f2 100644
@@ -16,6 +16,7 @@ conditions.
                         "arm,mmu-400"
                         "arm,mmu-401"
                         "arm,mmu-500"
+                        "cavium,smmu-v2"
 
                   depending on the particular implementation and/or the
                   version of the architecture implemented.
drivers/iommu/arm-smmu.c +32 -11

121 lines not on this page · raw message

--
2.1.0

#1 lore raw

PATCH v4 1/1 iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

Quoted 8 lines · Tirumalesh Chalamarla

Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3.

This patch make sures ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
- Removed redundent variable.

[...]

Quoted 28 lines
drivers/iommu/arm-smmu.c +7 -2
index 247a469..bfe38f3 100644
@@ -326,6 +326,11 @@ struct arm_smmu_device {
 
 	struct list_head		list;
 	struct rb_root			masters;
+	/*
+	 *The following fields are specific to Cavium, Thunder
+	 */
+	u32				cavium_id_base;
+
 };
 
 struct arm_smmu_cfg {

@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
 };
 #define INVALID_IRPTNDX			0xff
 
-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
 
 enum arm_smmu_domain_stage {
 	ARM_SMMU_DOMAIN_S1 = 0,

drivers/iommu/arm-smmu.c struct arm_smmu_option_prop { · line 372

Quoted 4 lines
drivers/iommu/arm-smmu.c +1 -0
@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
 	const char *prop;
 };
 
+static u32 cavium_smmu_context_count;

I thought you were going to make this an atomic_t?

Will

author
#2 lore raw

PATCH v4 1/1 iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

Quoted 43 lines · Will Deacon
Quoted 8 lines · Tirumalesh Chalamarla

Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3.

This patch make sures ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
- Removed redundent variable.

[...]

Quoted 31 lines
drivers/iommu/arm-smmu.c +7 -2
index 247a469..bfe38f3 100644
@@ -326,6 +326,11 @@ struct arm_smmu_device {
 
  	struct list_head		list;
  	struct rb_root			masters;
+	/*
+	 *The following fields are specific to Cavium, Thunder
+	 */
+	u32				cavium_id_base;
+
  };
 
  struct arm_smmu_cfg {

@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
  };
  #define INVALID_IRPTNDX			0xff
 
-#define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
 
  enum arm_smmu_domain_stage {
  	ARM_SMMU_DOMAIN_S1 = 0,

@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
  	const char *prop;
  };
Quoted 3 lines

drivers/iommu/arm-smmu.c struct arm_smmu_option_prop { · line 372

Quoted 1 line
drivers/iommu/arm-smmu.c +1 -0
+static u32 cavium_smmu_context_count;

I thought you were going to make this an atomic_t?

well i moved variable handling inside atomic context. with atomic_t i still needed 2 operations like read and add it seems atomic_add_return is not sufficient.

in any case i thought why not use the atomic context that is already there. if you feel the use of atomic_t is more natural, i will resend again.

Thanks,
Tirumalesh.

Quoted 3 lines

Will

author
#3 lore raw

PATCH v4 1/1 iommu/arm-smmu-v2: Workaround for ThunderX errata#27704

Quoted 49 lines · Tirumalesh Chalamarla
Quoted 46 lines · Will Deacon
Quoted 9 lines · Tirumalesh Chalamarla

Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID namespaces; specifically within a given node SMMU0 and SMMU1 share, as does SMMU2 and SMMU3.

This patch make sures ASID and VMID space is unique across cavium SMMUv2.

changes from V3:
- Removed redundent variable.

[...]

Quoted 33 lines
drivers/iommu/arm-smmu.c +7 -2
index 247a469..bfe38f3 100644
@@ -326,6 +326,11 @@ struct arm_smmu_device {
 
      struct list_head        list;
      struct rb_root            masters;
+    /*
+     *The following fields are specific to Cavium, Thunder
+     */
+    u32                cavium_id_base;
+
  };
 
  struct arm_smmu_cfg {

@@ -335,8 +340,8 @@ struct arm_smmu_cfg {
  };
  #define INVALID_IRPTNDX            0xff
 
-#define ARM_SMMU_CB_ASID(cfg)        ((cfg)->cbndx)
-#define ARM_SMMU_CB_VMID(cfg)        ((cfg)->cbndx + 1)
+#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base +
 (cfg)->cbndx)
+#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base +
 (cfg)->cbndx + 1)
 

  enum arm_smmu_domain_stage {
      ARM_SMMU_DOMAIN_S1 = 0,
drivers/iommu/arm-smmu.c +0 -0
@@ -364,6 +369,8 @@ struct arm_smmu_option_prop {
      const char *prop;
  };
Quoted 7 lines
Quoted 3 lines

drivers/iommu/arm-smmu.c struct arm_smmu_option_prop { · line 372

Quoted 1 line
drivers/iommu/arm-smmu.c +1 -0
+static u32 cavium_smmu_context_count;

I thought you were going to make this an atomic_t?

well i moved variable handling inside atomic context. with atomic_t i still needed 2 operations like read and add it seems atomic_add_return is not sufficient.

ignore this, will send with atomic_t if that feels more natural.

Quoted 14 lines

in any case i thought why not use the atomic context that is already there. if you feel the use of atomic_t is more natural, i will resend again.

Thanks,
Tirumalesh.

Quoted 3 lines

Will

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