net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
Subsystems (3)
PATCH 1/1 net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports starting at offset 0. So replace the 2 functions with a single function that takes this key value/mask to program both source and dest ports.
Remove the incorrect check for mask in ixgbe_configure_clsu32()
Tested with the following filters:
#tc qdisc add dev p4p1 ingress
#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop
#tc filter del dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action drop
--- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 3 +-- drivers/net/ethernet/intel/ixgbe/ixgbe_model.h | 17 ++++------------- 2 files changed, 5 insertions(+), 15 deletions(-)
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +1 -2
@@ -8348,8 +8348,7 @@ static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,int j;for (j =0 ; field_ptr[j].val; j++) { -if (field_ptr[j].off == off && - field_ptr[j].mask == m) { +if (field_ptr[j].off == off) { field_ptr[j].val (input, &mask, val, m); input->filter.formatted.flow_type |= field_ptr[j].type;
drivers/net/ethernet/intel/ixgbe/ixgbe_model.h +4 -13
@@ -65,28 +65,19 @@ static struct ixgbe_mat_field ixgbe_ipv4_fields[] = { { .val = NULL } /* terminal node */ }; -static inline int ixgbe_mat_prgm_sport (struct ixgbe_fdir_filter *input, +static inline int ixgbe_mat_prgm_ports (struct ixgbe_fdir_filter *input,union ixgbe_atr_input *mask,u32 val,u32 m) { input->filter.formatted.src_port = val &0xffff ; mask->formatted.src_port = m &0xffff ; -return 0 ; -}; - -static inline int ixgbe_mat_prgm_dport (struct ixgbe_fdir_filter *input, -union ixgbe_atr_input *mask, -u32 val,u32 m) -{ - input->filter.formatted.dst_port = val &0xffff ; - mask->formatted.dst_port = m &0xffff ; + input->filter.formatted.dst_port = val >>16 ; + mask->formatted.dst_port = m >>16 ;return 0 ; };static struct ixgbe_mat_field ixgbe_tcp_fields[] = { - {.off =0 , .mask =0xffff , .val = ixgbe_mat_prgm_sport, - .type =IXGBE_ATR_FLOW_TYPE_TCPV4 }, - {.off =2 , .mask =0xffff , .val = ixgbe_mat_prgm_dport, + {.off =0 , .mask =0xffffffff , .val = ixgbe_mat_prgm_ports, .type =IXGBE_ATR_FLOW_TYPE_TCPV4 }, { .val =NULL }/* terminal node */ };
Signature · 1 line
2.1.0
Quoted 25 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports starting at offset 0. So replace the 2 functions with a single function that takes this key value/mask to program both source and dest ports.
Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress
#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop#tc filter del dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action drop
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port. Do we actually need three signatures to match? Something like,
static struct ixgbe_mat_field ixgbe_tcp_fields[] = {
{.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports,
.type = IXGBE_ATR_FLOW_TYPE_TCPV4},
{.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport,
.type = IXGBE_ATR_FLOW_TYPE_TCPV4},
{.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4},
{ .val = NULL } /* terminal node */
};
Also just a reminder if we get multiple fields in a ixgbe_mat_field struct we need to abort out of the for loop in the cls_u32 configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.
Thanks,
John
Quoted 26 lines · John Fastabend
Quoted 25 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports starting at offset 0. So replace the 2 functions with a single function that takes this key value/mask to program both source and dest ports.
Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress
#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop#tc filter del dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action drop
Quoted 3 lines
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port.
No. This will not break specifying only src or dst port. The value/mask for the unspecified port will be set to zero. So it should be fine.
For ex:
match tcp src 1024 ffff match tcp dst 80 ffff => match 04000050/ffffffff at nexthdr+0 match tcp src 1024 ffff => match 04000000/ffff0000 at nexthdr+0 match tcp dst 80 ffff => match 00000050/0000ffff at nexthdr+0
Quoted 20 lines
Do we
actually need three signatures to match? Something like,static struct ixgbe_mat_field ixgbe_tcp_fields[] = { {.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, { .val = NULL } /* terminal node */ };Also just a reminder if we get multiple fields in a
ixgbe_mat_fieldstruct we need to abort out of the for loop in thecls_u32configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.Thanks,
John
PATCH 1/1 net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
Quoted 35 lines · Sridhar
Quoted 26 lines · John Fastabend
Quoted 25 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports starting at offset 0. So replace the 2 functions with a single function that takes this key value/mask to program both source and dest ports.
Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop #tc filter del dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action dropQuoted 3 lines
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port.
No. This will not break specifying only src or dst port. The value/mask for the
unspecified port will be set to zero. So it should be fine.
Quoted 30 lines
For ex:
match tcp src 1024 ffff match tcp dst 80 ffff
=> match 04000050/ffffffff at nexthdr+0
match tcp src 1024 ffff
=> match 04000000/ffff0000 at nexthdr+0
match tcp dst 80 ffff
=> match 00000050/0000ffff at nexthdr+0Quoted 20 lines
Do we
actually need three signatures to match? Something like,static struct ixgbe_mat_field ixgbe_tcp_fields[] = { {.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, { .val = NULL } /* terminal node */ };Also just a reminder if we get multiple fields in a
ixgbe_mat_fieldstruct we need to abort out of the for loop in thecls_u32configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.Thanks,
John
Dropped netdev no reason to push mail to netdev that has to do with our driver internals.
OK I see so you dropped the .mask check in fact you actually put it there in the commit message I just missed the detail/implication.
I think this is fine and it allows supporting mask entries now which I blocked in the initial submission. But with this is there any reason to have a mask field in ixgbe_mat_field? We could probably do this with two patches, one to drop the 'mask' field and check and another to fix the ixgbe_tcp_fields patch?
Thanks,
John
Samudrala
PATCH 1/1 net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
Quoted 67 lines · John Fastabend
Quoted 34 lines · Sridhar
Quoted 26 lines · John Fastabend
Quoted 25 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports starting at offset 0. So replace the 2 functions with a single function that takes this key value/mask to program both source and dest ports.
Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop #tc filter del dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action dropQuoted 3 lines
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port.
No. This will not break specifying only src or dst port. The value/mask for the
unspecified port will be set to zero. So it should be fine.Quoted 29 lines
For ex:
match tcp src 1024 ffff match tcp dst 80 ffff
=> match 04000050/ffffffff at nexthdr+0
match tcp src 1024 ffff
=> match 04000000/ffff0000 at nexthdr+0
match tcp dst 80 ffff
=> match 00000050/0000ffff at nexthdr+0Quoted 20 lines
Do we
actually need three signatures to match? Something like,static struct ixgbe_mat_field ixgbe_tcp_fields[] = { {.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, { .val = NULL } /* terminal node */ };Also just a reminder if we get multiple fields in a
ixgbe_mat_fieldstruct we need to abort out of the for loop in thecls_u32configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.Thanks,
JohnDropped netdev no reason to push mail to netdev that has to do with our driver internals.
Quoted 8 lines
OK I see so you dropped the .mask check in fact you actually put it there in the commit message I just missed the detail/implication.
I think this is fine and it allows supporting mask entries now which I blocked in the initial submission. But with this is there any reason to have a mask field in
ixgbe_mat_field? We could probably do this with two patches, one to drop the 'mask' field and check and another to fix theixgbe_tcp_fieldspatch?
OK. will remove the 'mask' field and resubmit as 2 patches.
Thanks
Sridhar
PATCH 1/1 net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
Quoted 81 lines · Sridhar
Quoted 69 lines · John Fastabend
Quoted 36 lines · Sridhar
Quoted 28 lines · John Fastabend
Quoted 27 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports
starting at offset 0. So replace the 2 functions with a single function
that takes this key value/mask to program both source and dest ports.Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop #tc filter del dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action dropQuoted 3 lines
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port.
No. This will not break specifying only src or dst port. The value/mask for the
unspecified port will be set to zero. So it should be fine.Quoted 29 lines
For ex:
match tcp src 1024 ffff match tcp dst 80 ffff
=> match 04000050/ffffffff at nexthdr+0
match tcp src 1024 ffff
=> match 04000000/ffff0000 at nexthdr+0
match tcp dst 80 ffff
=> match 00000050/0000ffff at nexthdr+0Quoted 20 lines
Do we
actually need three signatures to match? Something like,static struct ixgbe_mat_field ixgbe_tcp_fields[] = { {.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, { .val = NULL } /* terminal node */ };Also just a reminder if we get multiple fields in a
ixgbe_mat_fieldstruct we need to abort out of the for loop in thecls_u32configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.Thanks,
JohnDropped netdev no reason to push mail to netdev that has to do with our driver internals.
Quoted 8 lines
OK I see so you dropped the .mask check in fact you actually put it there in the commit message I just missed the detail/implication.
I think this is fine and it allows supporting mask entries now which I blocked in the initial submission. But with this is there any reason to have a mask field in
ixgbe_mat_field? We could probably do this with two patches, one to drop the 'mask' field and check and another to fix theixgbe_tcp_fieldspatch?
Quoted 4 lines
OK. will remove the 'mask' field and resubmit as 2 patches.
Thanks
Sridhar
Great thanks nice catch / improvements.
PATCH 1/1 net: ixgbe: Fix cls_u32 offload support for ports and fields with masks.
In reply to SamudralaQuoted 81 lines · Sridhar
Quoted 69 lines · John Fastabend
Quoted 36 lines · Sridhar
Quoted 28 lines · John Fastabend
Quoted 27 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports
starting at offset 0. So replace the 2 functions with a single function
that takes this key value/mask to program both source and dest ports.Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop #tc filter del dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1: u32 divisor 1 #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:10 u32 ht 800: link 1: \ offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 1:0:10 u32 ht 1: \ match tcp src 1024 ffff match tcp dst 80 ffff action dropQuoted 3 lines
Quoted 2 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
But this will break setting only dst port or only src port.
No. This will not break specifying only src or dst port. The value/mask for the
unspecified port will be set to zero. So it should be fine.Quoted 29 lines
For ex:
match tcp src 1024 ffff match tcp dst 80 ffff
=> match 04000050/ffffffff at nexthdr+0
match tcp src 1024 ffff
=> match 04000000/ffff0000 at nexthdr+0
match tcp dst 80 ffff
=> match 00000050/0000ffff at nexthdr+0Quoted 20 lines
Do we
actually need three signatures to match? Something like,static struct ixgbe_mat_field ixgbe_tcp_fields[] = { {.off = 0, .mask = 0xffffffff, .val = ixgbe_mat_prgm_ports, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0xffff0000, .val = ixgbe_mat_prgm_dport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, {.off = 0, .mask = 0x0000ffff, .val = ixgbe_mat_prgm_sport, .type = IXGBE_ATR_FLOW_TYPE_TCPV4}, { .val = NULL } /* terminal node */ };Also just a reminder if we get multiple fields in a
ixgbe_mat_fieldstruct we need to abort out of the for loop in thecls_u32configure function. Actually we can probably just push that as its own patch to make the core function more versatile/usable.Thanks,
JohnDropped netdev no reason to push mail to netdev that has to do with our driver internals.
Quoted 8 lines
OK I see so you dropped the .mask check in fact you actually put it there in the commit message I just missed the detail/implication.
I think this is fine and it allows supporting mask entries now which I blocked in the initial submission. But with this is there any reason to have a mask field in
ixgbe_mat_field? We could probably do this with two patches, one to drop the 'mask' field and check and another to fix theixgbe_tcp_fieldspatch?
Quoted 4 lines
OK. will remove the 'mask' field and resubmit as 2 patches.
Thanks
Sridhar
Great nice catch / improvements. By the way my goal here is to get to the point where we can share this across drivers and just change the *model.h file.
.John
Quoted 28 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports
starting at offset 0. So replace the 2 functions with a single function
that takes this key value/mask to program both source and dest ports.Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
?#tc qdisc add dev p4p1 ingress
?#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
????????handle 800:0:1 u32 ht 800: \
????????match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop?#tc filter del dev p4p1 parent ffff: protocol ip prio 99 \
????????handle 800:0:1 u32
?#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
????????handle 1: u32 divisor 1
?#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
????????handle 800:0:10 u32 ht 800: link 1: \
????????offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6 ff
?#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
????????handle 1:0:10 u32 ht 1: \
????????match tcp src 1024 ffff match tcp dst 80 ffff action drop
Quoted 6 lines
Signed-off-by Sridhar Samudrala <[email protected]>---
?drivers/net/ethernet/intel/ixgbe/ixgbe_main.c? |? 3 +-- ?drivers/net/ethernet/intel/ixgbe/ixgbe_model.h | 17 ++++----------
---
?2 files changed, 5 insertions(+), 15 deletions(-)
Is this v2? ?If not, why are you re-sending a patch that is already in
my queue? ?If so, where is the changelog so we know what changed in
this updated v2 of the patch?
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Quoted 35 lines · Jeff Kirsher
Quoted 28 lines · Sridhar Samudrala
Fix support for 16 bit source/dest port matches in ixgbe model. u32 uses a single 32-bit key value for both source and destination ports
starting at offset 0. So replace the 2 functions with a single function
that takes this key value/mask to program both source and dest ports.Remove the incorrect check for mask in
ixgbe_configure_clsu32()Tested with the following filters:
#tc qdisc add dev p4p1 ingress #tc filter add dev p4p1 parent ffff: protocol ip prio 99 \ handle 800:0:1 u32 ht 800: \ match ip dst 11.0.0.1/24 match ip src 11.0.0.2/24 action drop#tc filter del dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:1 u32#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
handle 1: u32 divisor 1
#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
handle 800:0:10 u32 ht 800: link 1: \
offset at 0 mask 0f00 shift 6 plus 0 eat match ip protocol 6
ff
#tc filter add dev p4p1 parent ffff: protocol ip prio 99 \
handle 1:0:10 u32 ht 1: \
match tcp src 1024 ffff match tcp dst 80 ffff action dropQuoted 6 lines
Signed-off-by Sridhar Samudrala <[email protected]>--- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 3 +-- drivers/net/ethernet/intel/ixgbe/ixgbe_model.h | 17 ++++---------- --- 2 files changed, 5 insertions(+), 15 deletions(-)
Quoted 3 lines
Is this v2? If not, why are you re-sending a patch that is already in my queue? If so, where is the changelog so we know what changed in this updated v2 of the patch?
No. This is another patch that fixes other issues on top of the previous one.
Thanks
Sridhar