ARM: DRA7: emif: Miscellaneous bug fixes

PATCH New Lokesh Vutla 3 participants 16 messages Mar 5, 2016 – Mar 15, 2016 Arm (32-bit)

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Lokesh Vutla

author

2016-03-05 12:02 UTC #0 lore raw

cover ARM: DRA7: emif: Miscellaneous bug fixes

This series fixes miscellaneous bugs for the emif driver.

Lokesh Vutla (4):
ARM: DRA7: emif: Fix updating of refresh ctrl shadow
ARM: DRA7: emif: Fix DDR init sequence during warm reset
ARM: DRA7: emif: Check for enable bits before updating leveling output
ARM: DRA7: emif: Enable interleaving for higher address space

 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
 arch/arm/include/asm/emif.h                  |  9 +++++
 3 files changed, 67 insertions(+), 26 deletions(-)

Signature · 1 line

2.1.4

Lokesh Vutla

author

2016-03-05 12:02 UTC #1 lore raw

PATCH 1/4 ARM: DRA7: emif: Fix updating of refresh ctrl shadow

On DRA7, refresh ctrl shadow should be updated with the final value.

Signed-off-by Lokesh Vutla <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/omap-common/emif-common.c +5 -1

index bf7bf26..90c241a 100644
@@ -163,7 +163,11 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	if (!is_dra7xx())
+		writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	else
+		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
+
 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);

Signature · 1 line

2.1.4

Tom Rini

2016-03-07 23:35 UTC #2 lore raw

PATCH 1/4 ARM: DRA7: emif: Fix updating of refresh ctrl shadow

Quoted 4 lines · Lokesh Vutla

On DRA7, refresh ctrl shadow should be updated with the final value.
Signed-off-by Lokesh Vutla <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Tom Rini

2016-03-15 11:59 UTC #3 lore raw

PATCH 1/4 ARM: DRA7: emif: Fix updating of refresh ctrl shadow

In reply to Lokesh Vutla

Quoted 5 lines · Lokesh Vutla

On DRA7, refresh ctrl shadow should be updated with the final value.
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Lokesh Vutla

author

2016-03-05 12:02 UTC #4 lore raw

PATCH 2/4 ARM: DRA7: emif: Fix DDR init sequence during warm reset

In reply to Lokesh Vutla

Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset.

Signed-off-by Lokesh Vutla <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/omap-common/emif-common.c +3 -1

index 90c241a..6b33b45 100644
@@ -327,8 +327,10 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	if (warm_reset())
+	if (warm_reset()) {
 		emif_reset_phy(base);
+		writel(0x0, &emif->emif_pwr_mgmt_ctrl);
+	}
 	do_ext_phy_settings(base, regs);
 
 	writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,

Signature · 1 line

2.1.4

Tom Rini

2016-03-07 23:35 UTC #5 lore raw

PATCH 2/4 ARM: DRA7: emif: Fix DDR init sequence during warm reset

Quoted 9 lines · Lokesh Vutla

Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset.
Signed-off-by Lokesh Vutla <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Tom Rini

2016-03-15 11:59 UTC #6 lore raw

PATCH 2/4 ARM: DRA7: emif: Fix DDR init sequence during warm reset

In reply to Lokesh Vutla

Quoted 10 lines · Lokesh Vutla

Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset.
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Lokesh Vutla

author

2016-03-05 12:02 UTC #7 lore raw

PATCH 3/4 ARM: DRA7: emif: Check for enable bits before updating leveling output

In reply to Lokesh Vutla

Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling.

Signed-off-by Lokesh Vutla <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 38 ++++++++++++++++------------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 +++++++++++++++++++------
 arch/arm/include/asm/emif.h                  |  6 +++++
 3 files changed, 54 insertions(+), 24 deletions(-)

arch/arm/cpu/armv7/omap-common/emif-common.c +22 ~~-16~~

index 6b33b45..3673884 100644
@@ -250,33 +250,39 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
-	u32 reg, i;
+	u32 reg, i, phy;
 
 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+	phy = readl(&emif->emif_ddr_phy_ctrl_1);
 
 	/* Update PHY_REG_RDDQS_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
-	for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+		for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
-	for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+		for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
-	for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+		for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Disable Leveling */
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);

arch/arm/cpu/armv7/omap5/sdram.c +26 -8

index a8d63c2..c386e64 100644
@@ -643,11 +643,12 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 	u32 *emif_ext_phy_ctrl_base = 0;
 	u32 emif_nr;
 	const u32 *ext_phy_ctrl_const_regs;
-	u32 i, hw_leveling, size;
+	u32 i, hw_leveling, size, phy;
 
 	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
 	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+	phy = regs->emif_ddr_phy_ctlr_1_init;
 
 	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);

@@ -657,18 +658,35 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 
-	if (!hw_leveling) {
-		/*
-		 * Copy the predefined PHY register values
-		 * in case of sw leveling
-		 */
-		for (i = 1; i < 25; i++) {
+	/*
+	 * Copy the predefined PHY register values
+	 * if leveling is disabled.
+	 */
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
+		for (i = 1; i < 6; i++) {
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2]);
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
 		}
-	} else {
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
+		for (i = 6; i < 11; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
+		for (i = 11; i < 25; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (hw_leveling) {
 		/*
 		 * Write the init value for HW levling to occur
 		 */

arch/arm/include/asm/emif.h +6 -0

index 7986e6e..b03cf5a 100644
@@ -478,6 +478,12 @@
 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT		25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK		(1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT	26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK		(1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT		27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK		(1 << 27)
 
 /* DDR_PHY_CTRL_2 */
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0

Signature · 1 line

2.1.4

Tom Rini

2016-03-07 23:35 UTC #8 lore raw

PATCH 3/4 ARM: DRA7: emif: Check for enable bits before updating leveling output

Quoted 5 lines · Lokesh Vutla

Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling.
Signed-off-by Lokesh Vutla <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Tom Rini

2016-03-15 11:59 UTC #9 lore raw

PATCH 3/4 ARM: DRA7: emif: Check for enable bits before updating leveling output

In reply to Lokesh Vutla

Quoted 6 lines · Lokesh Vutla

Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling.
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Lokesh Vutla

author

2016-03-05 12:02 UTC #10 lore raw

PATCH 4/4 ARM: DRA7: emif: Enable interleaving for higher address space

In reply to Lokesh Vutla

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance.

Signed-off-by Lokesh Vutla <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/emif-common.c | 2 ++
 arch/arm/include/asm/emif.h                  | 3 +++
 2 files changed, 5 insertions(+)

arch/arm/cpu/armv7/omap-common/emif-common.c +2 -0

index 3673884..697d6e0 100644
@@ -1329,6 +1329,8 @@ void dmm_init(u32 base)
 			&hw_lisa_map_regs->dmm_lisa_map_1);
 		writel(lisa_map_regs->dmm_lisa_map_0,
 			&hw_lisa_map_regs->dmm_lisa_map_0);
+
+		setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
 	}
 
 	/*

arch/arm/include/asm/emif.h +3 -0

index b03cf5a..3183130 100644
@@ -545,6 +545,9 @@
 
 /* Memory Adapter */
 #define MA_BASE				0x482AF040
+#define MA_PRIORITY			0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT	8
+#define MA_HIMEM_INTERLEAVE_UN_MASK	(1 << 8)
 
 /* DMM_LISA_MAP */
 #define EMIF_SYS_ADDR_SHIFT		24

Signature · 1 line

2.1.4

Tom Rini

2016-03-07 23:36 UTC #11 lore raw

PATCH 4/4 ARM: DRA7: emif: Enable interleaving for higher address space

Quoted 4 lines · Lokesh Vutla

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance.
Signed-off-by Lokesh Vutla <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Tom Rini

2016-03-15 11:59 UTC #12 lore raw

PATCH 4/4 ARM: DRA7: emif: Enable interleaving for higher address space

In reply to Lokesh Vutla

Quoted 5 lines · Lokesh Vutla

Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance.
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Tom Rini

2016-03-07 23:36 UTC #13 lore raw

cover ARM: DRA7: emif: Miscellaneous bug fixes

In reply to Lokesh Vutla

Quoted 8 lines · Lokesh Vutla

This series fixes miscellaneous bugs for the emif driver.
Lokesh Vutla (4):
ARM: DRA7: emif: Fix updating of refresh ctrl shadow
ARM: DRA7: emif: Fix DDR init sequence during warm reset
ARM: DRA7: emif: Check for enable bits before updating leveling output
ARM: DRA7: emif: Enable interleaving for higher address space

Quoted 4 lines

 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
 arch/arm/include/asm/emif.h                  |  9 +++++
 3 files changed, 67 insertions(+), 26 deletions(-)

Note that my board is still unable to boot from mainline with these applied but still works with the TI vendor tree.

Signature · 8 lines

Tom
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Lokesh Vutla

2016-03-08 03:37 UTC #14 lore raw

cover ARM: DRA7: emif: Miscellaneous bug fixes

Quoted 10 lines · Tom Rini

Quoted 8 lines · Lokesh Vutla
This series fixes miscellaneous bugs for the emif driver.
Lokesh Vutla (4):
ARM: DRA7: emif: Fix updating of refresh ctrl shadow
ARM: DRA7: emif: Fix DDR init sequence during warm reset
ARM: DRA7: emif: Check for enable bits before updating leveling output
ARM: DRA7: emif: Enable interleaving for higher address space

Quoted 7 lines

Quoted 4 lines
 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
 arch/arm/include/asm/emif.h                  |  9 +++++
 3 files changed, 67 insertions(+), 26 deletions(-)
Note that my board is still unable to boot from mainline with these applied but still works with the TI vendor tree.

Hmm..I guess you are talking about DRA72-evm. SPL even doesn't come up or U-boot is failing. Can I see the logs? And what switch settings are you using?(Ill try to reproduce in my place)

Thanks and regards,
Lokesh

Quoted 1 line

Tom Rini

2016-03-08 11:58 UTC #15 lore raw

cover ARM: DRA7: emif: Miscellaneous bug fixes

Quoted 16 lines · Lokesh Vutla

Quoted 15 lines · Tom Rini
Quoted 12 lines · Lokesh Vutla
This series fixes miscellaneous bugs for the emif driver.
Lokesh Vutla (4):
ARM: DRA7: emif: Fix updating of refresh ctrl shadow
ARM: DRA7: emif: Fix DDR init sequence during warm reset
ARM: DRA7: emif: Check for enable bits before updating leveling output
ARM: DRA7: emif: Enable interleaving for higher address space
 arch/arm/cpu/armv7/omap-common/emif-common.c | 50 ++++++++++++++++++----------
 arch/arm/cpu/armv7/omap5/sdram.c             | 34 ++++++++++++++-----
 arch/arm/include/asm/emif.h                  |  9 +++++
 3 files changed, 67 insertions(+), 26 deletions(-)

Quoted 6 lines

Quoted 2 lines
Note that my board is still unable to boot from mainline with these applied but still works with the TI vendor tree.
Hmm..I guess you are talking about DRA72-evm. SPL even doesn't come up or U-boot is failing. Can I see the logs? And what switch settings are you using?(Ill try to reproduce in my place)

SPL doesn't even come up so no output. SD card boot settings. I can send you SW2/SW3/SW5 off-list in a bit.

Signature · 8 lines

Tom
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