Add support for 96boards Dragonboard410C board

---

Changes in v2:
- Added newline before return... (globally)
- Renamed p to priv (priv data) - it required some rewrapping
- Added Reviewed-by

 doc/device-tree-bindings/serial/msm-serial.txt |   6 +
 drivers/serial/Kconfig                         |   8 +
 drivers/serial/Makefile                        |   1 +
 drivers/serial/serial_msm.c                    | 217 +++++++++++++++++++++++++
 4 files changed, 232 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt
 create mode 100644 drivers/serial/serial_msm.c

doc/device-tree-bindings/serial/msm-serial.txt new file +6 -0

new file mode 100644
index 0000000..48b8428
@@ -0,0 +1,6 @@
+Qualcomm UART (Data Mover mode)
+
+Required properties:
+- compatible: must be "qcom,msm-uartdm-v1.4"
+- reg: start address and size of the registers
+- clock: interface clock (must accept baudrate as a frequency)

drivers/serial/Kconfig +8 -0

index 92d4212..e748663 100644
@@ -311,4 +311,12 @@ config XILINX_UARTLITE
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
 
+config MSM_SERIAL
+	bool "Qualcomm on-chip UART"
+	depends on DM_SERIAL
+	help
+	  Support Data Mover UART used on Qualcomm Snapdragon SoCs.
+	  It should support all Qualcomm devices with UARTDM version 1.4,
+	  for example APQ8016 and MSM8916.
+	  Single baudrate is supported in current implementation (115200).
 endmenu

drivers/serial/Makefile +1 -0

index 05bdf56..462dba1 100644
@@ -38,6 +38,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o

drivers/serial/serial_msm.c new file +217 -0

217 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #2 lore raw

PATCH v3 2/21 gpio: Add support for Qualcomm gpio controller

Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Reordered includes (again)
- Added newlines between returns
- Fixed error handling in msm_gpio_probe
- Added reviewed-by

Changes in v1:
- Added dt binding documentation
- Added help to KConfig
- Use clrsetbits() to switch direction
- Fixed include order
- Added #defines for registers/register fields
- Added secondary compatible string

 doc/device-tree-bindings/gpio/gpio-msm.txt |  22 +++++
 drivers/gpio/Kconfig                       |  14 +++
 drivers/gpio/Makefile                      |   1 +
 drivers/gpio/msm_gpio.c                    | 135 +++++++++++++++++++++++++++++
 4 files changed, 172 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt
 create mode 100644 drivers/gpio/msm_gpio.c

doc/device-tree-bindings/gpio/gpio-msm.txt new file +22 -0

new file mode 100644
index 0000000..966ce0a
@@ -0,0 +1,22 @@
+Qualcomm Snapdragon GPIO controller
+
+Required properties:
+- compatible : "qcom,msm8916-pinctrl" or "qcom,apq8016-pinctrl"
+- reg : Physical base address and length of the controller's registers.
+	This controller is called "Top Level Mode Multiplexing" in
+	Qualcomm documentation.
+- #gpio-cells : Should be one (pin number).
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bank-name: (optional) name of gpio bank. As default "soc" is used.
+
+Example:
+
+soc_gpios: pinctrl at 1000000 {
+	compatible = "qcom,msm8916-pinctrl";
+	reg = <0x1000000 0x300000>;
+	gpio-controller;
+	gpio-count = <122>;
+	gpio-bank-name="soc";
+	#gpio-cells = <1>;
+};

drivers/gpio/Kconfig +14 -0

index 94fabb9..befb4af 100644
@@ -46,6 +46,20 @@ config LPC32XX_GPIO
 	help
 	  Support for the LPC32XX GPIO driver.
 
+config MSM_GPIO
+	bool "Qualcomm GPIO driver"
+	depends on DM_GPIO
+	default n
+	help
+	  Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
+	  This controller have single bank (default name "soc"), every
+	  gpio has it's own set of registers.
+	  Only simple GPIO operations are supported (get/set, change of
+	  direction and checking pin function).
+	  Supported devices:
+	  - APQ8016
+	  - MSM8916
+
 config ROCKCHIP_GPIO
 	bool "Rockchip GPIO driver"
 	depends on DM_GPIO

drivers/gpio/Makefile +1 -0

index ca8c487..830d7a6 100644
@@ -48,3 +48,4 @@ obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)	+= hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)	+= pic32_gpio.o
+obj-$(CONFIG_MSM_GPIO)		+= msm_gpio.o

drivers/gpio/msm_gpio.c new file +135 -0

135 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #3 lore raw

PATCH v3 3/21 mmc: Add support for Qualcomm SDHCI controller

Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add reviewed-by

Changes in v1:
- Added commit message
- Added DT binding documentation
- Added Kconfig help
- Reordered includes
- Dropped redundant fields from msm_sdhc
- Cleaned up clock init code (+ added error handling)
- Dropped mdelay - use wait_for_bit instead in reset code
- Added missing newline after declarations
- Added error handling if "reg" is missing
- Converted base address to pointer

 doc/device-tree-bindings/mmc/msm_sdhci.txt |  25 ++++
 drivers/mmc/Kconfig                        |   9 ++
 drivers/mmc/Makefile                       |   1 +
 drivers/mmc/msm_sdhci.c                    | 180 +++++++++++++++++++++++++++++
 4 files changed, 215 insertions(+)
 create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt
 create mode 100644 drivers/mmc/msm_sdhci.c

doc/device-tree-bindings/mmc/msm_sdhci.txt new file +25 -0

new file mode 100644
index 0000000..08a290c
@@ -0,0 +1,25 @@
+Qualcomm Snapdragon SDHCI controller
+
+Required properties:
+- compatible : "qcom,sdhci-msm-v4"
+- reg: Base address and length of registers:
+	- Host controller registers (SDHCI)
+	- SD Core registers
+- clock: interface clock (must accept SD bus clock as a frequency)
+
+Optional properties:
+- index: If there is more than one controller - controller index (required
+	by generic SDHCI code).
+- bus_width: Width of SD/eMMC bus (default 4)
+- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
+
+Example:
+
+sdhci at 07864000 {
+	compatible = "qcom,sdhci-msm-v4";
+	reg = <0x7864900 0x11c 0x7864000 0x800>;
+	index = <0x1>;
+	bus-width = <0x4>;
+	clock = <&clkc 1>;
+	clock-frequency = <200000000>;
+};

drivers/mmc/Kconfig +9 -0

index dc8532f..4d3df11 100644
@@ -16,6 +16,15 @@ config DM_MMC
 	  appear as block devices in U-Boot and can support filesystems such
 	  as EXT4 and FAT.
 
+config MSM_SDHCI
+	bool "Qualcomm SDHCI controller"
+	depends on DM_MMC
+	help
+	  Enables support for SDHCI 2.0 controller present on some Qualcomm
+          Snapdragon devices. This device is compatible with eMMC v4.5 and
+          SD 3.0 specifications. Both SD and eMMC devices are supported.
+	  Card-detect gpios are not supported.
+
 config ROCKCHIP_DWMMC
 	bool "Rockchip SD/MMC controller support"
 	depends on DM_MMC && OF_CONTROL

drivers/mmc/Makefile +1 -0

index b85e4bf..585aaf3 100644
@@ -50,3 +50,4 @@ else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
 obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
+obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o

drivers/mmc/msm_sdhci.c new file +180 -0

180 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #4 lore raw

PATCH v3 4/21 ehci-hcd: Add init_after_reset

Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm.

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Tom Rini <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add Reviewed-by (sjg)

Changes in v1:
- No changes, just added Acked-by, Reviewed-by

 drivers/usb/host/ehci-hcd.c | 6 ++++++
 drivers/usb/host/ehci.h     | 1 +
 2 files changed, 7 insertions(+)

drivers/usb/host/ehci-hcd.c +6 -0

index 0113c6c..598f444 100644
@@ -1615,6 +1615,12 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
 	if (ret)
 		goto err;
 
+	if (ops->init_after_reset) {
+		ret = ops->init_after_reset(ctrl);
+		if (ret)
+			goto err;
+	}
+
 	ret = ehci_common_init(ctrl, tweaks);
 	if (ret)
 		goto err;

drivers/usb/host/ehci.h +1 -0

index 826b3fe..734d7f0 100644
@@ -240,6 +240,7 @@ struct ehci_ops {
 	void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
 			      uint32_t *reg);
 	uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
+	int (*init_after_reset)(struct ehci_ctrl *ctrl);
 };
 
 struct ehci_ctrl {

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #5 lore raw

PATCH v3 5/21 usb: ulpi: Add Kconfig options for ULPI

The following options can be now enabled via defconfig:
- CONFIG_USB_ULPI
- CONFIG_USB_ULPI_VIEWPORT
- CONFIG_USB_ULPI_VIEWPORT_OMAP

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add better (any) descriptions for Kconfig items.

Changes in v1: None

 drivers/usb/Kconfig      |  2 ++
 drivers/usb/ulpi/Kconfig | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 drivers/usb/ulpi/Kconfig

drivers/usb/Kconfig +2 -0

index abb06fc..57b99f2 100644
@@ -53,6 +53,8 @@ source "drivers/usb/musb-new/Kconfig"
 
 source "drivers/usb/emul/Kconfig"
 
+source "drivers/usb/ulpi/Kconfig"
+
 comment "USB peripherals"
 
 config USB_STORAGE

drivers/usb/ulpi/Kconfig new file +33 -0

new file mode 100644
index 0000000..329d2df
@@ -0,0 +1,33 @@
+comment "ULPI drivers"
+
+choice
+	prompt "ULPI Viewport type"
+	optional
+	default n
+	help
+	  Select ULPI viewport (SoC-side interface to ULPI) implementation
+	  appropriate for the device if you want to communicate with
+	  UTMI (USB PHY) via ULPI interface.
+
+config USB_ULPI_VIEWPORT
+	bool "Generic ULPI Viewport"
+	help
+	  Support generic ULPI Viewport implementation that is used on
+	  some Tegra and Snapdragon devices.
+
+config USB_ULPI_VIEWPORT_OMAP
+	bool "OMAP ULPI Viewport"
+	help
+	  Support ULPI Viewport implementation that is used on OMAP devices.
+
+endchoice
+
+config USB_ULPI
+	bool "ULPI support"
+	depends on (USB_ULPI_VIEWPORT || USB_ULPI_VIEWPORT_OMAP)
+	help
+	  Select to commnicate with USB PHY via ULPI interface.
+	  ULPI is wrapper on UTMI+ core that is used as
+	  PHY Transreceiver for USB controllers.
+
+	  This driver uses ULPI viewports that are specific for each SoC.

Signature · 1 line

2.5.0

Marek Vasut

2016-03-14 17:23 UTC #6 lore raw

PATCH v3 5/21 usb: ulpi: Add Kconfig options for ULPI

Quoted 7 lines · Mateusz Kulikowski

The following options can be now enabled via defconfig:
- CONFIG_USB_ULPI
- CONFIG_USB_ULPI_VIEWPORT
- CONFIG_USB_ULPI_VIEWPORT_OMAP
Signed-off-by Mateusz Kulikowski <[email protected]>
Reviewed-by Simon Glass <[email protected]>

Best regards,
Marek Vasut

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #7 lore raw

PATCH v3 6/21 Migrate CONFIG_ULPI* to Kconfig

Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly.

Affected boards:
colibri_t20, harmony, mcx, mt_ventoux, twister,
zynq_(picozed, zc702, zc706, zed, zybo)

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- New patch, independent of the rest
- Should compile cleanly on all affected platforms
- Is orthogonal to series (i.e. if get's NAK will not break rest of series)

Changes in v1: None

 configs/colibri_t20_defconfig    | 2 ++
 configs/harmony_defconfig        | 2 ++
 configs/mcx_defconfig            | 3 +++
 configs/mt_ventoux_defconfig     | 3 +++
 configs/twister_defconfig        | 3 +++
 configs/zynq_picozed_defconfig   | 3 +++
 configs/zynq_zc702_defconfig     | 3 +++
 configs/zynq_zc706_defconfig     | 3 +++
 configs/zynq_zed_defconfig       | 3 +++
 configs/zynq_zybo_defconfig      | 3 +++
 include/configs/colibri_t20.h    | 3 +--
 include/configs/harmony.h        | 2 --
 include/configs/mcx.h            | 2 --
 include/configs/tam3517-common.h | 2 --
 include/configs/zynq-common.h    | 2 --
 15 files changed, 29 insertions(+), 10 deletions(-)

configs/colibri_t20_defconfig +2 -0

index e8b3e0c..c964387 100644
@@ -20,4 +20,6 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/harmony_defconfig +2 -0

index 14125b4..0b2422e 100644
@@ -21,4 +21,6 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y

configs/mcx_defconfig +3 -0

index 1e204d5..612bf66 100644
@@ -10,3 +10,6 @@ CONFIG_SYS_PROMPT="mcx # "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y

configs/mt_ventoux_defconfig +3 -0

index a0153e4..8b3298b 100644
@@ -8,3 +8,6 @@ CONFIG_SYS_PROMPT="mt_ventoux => "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y

configs/twister_defconfig +3 -0

index e721edb..a1abbe1 100644
@@ -8,3 +8,6 @@ CONFIG_SYS_PROMPT="twister => "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT_OMAP=y

configs/zynq_picozed_defconfig +3 -0

index f34e2e3..540b0dd 100644
@@ -12,3 +12,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y

configs/zynq_zc702_defconfig +3 -0

index f01874f..a6db9ff 100644
@@ -24,3 +24,6 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y

configs/zynq_zc706_defconfig +3 -0

index 215f00d..d9a9bff 100644
@@ -21,3 +21,6 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y

configs/zynq_zed_defconfig +3 -0

index 4a2a2fc..25df8e5 100644
@@ -21,3 +21,6 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y

configs/zynq_zybo_defconfig +3 -0

index 7c23fec..dd8cb62 100644
@@ -22,3 +22,6 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y

include/configs/colibri_t20.h +1 -2

index b7ad189..e97e5a1 100644
@@ -36,8 +36,7 @@
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB

include/configs/harmony.h +0 -2

index f66ac70..0a3cb18 100644
@@ -44,8 +44,6 @@
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB

include/configs/mcx.h +0 -2

index 4eea06d..7987b2c 100644
@@ -105,8 +105,6 @@
 #define CONFIG_OMAP3_GPIO_5
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define	CONFIG_USB_HOST_ETHER

include/configs/tam3517-common.h +0 -2

index 2d941ca..0a4d3fa 100644
@@ -91,8 +91,6 @@
 #define CONFIG_OMAP3_GPIO_5
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_STORAGE

include/configs/zynq-common.h +0 -2

index 982905d..9134bfb 100644
@@ -96,8 +96,6 @@
 # define CONFIG_CMD_USB
 # define CONFIG_USB_STORAGE
 # define CONFIG_USB_EHCI_ZYNQ
-# define CONFIG_USB_ULPI_VIEWPORT
-# define CONFIG_USB_ULPI
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #8 lore raw

PATCH v3 7/21 usb: ulpi: Fix viewport_addr type

viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices.

This fix changes its type to match pointer size.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 include/usb/ulpi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

include/usb/ulpi.h +1 -1

index 4fa765b..dfea395 100644
@@ -32,7 +32,7 @@
  * be extended from this structure
  */
 struct ulpi_viewport {
-	u32 viewport_addr;
+	uintptr_t viewport_addr;
 	u32 port_num;
 };

Signature · 1 line

2.5.0

Marek Vasut

2016-03-14 17:23 UTC #9 lore raw

PATCH v3 7/21 usb: ulpi: Fix viewport_addr type

Quoted 7 lines · Mateusz Kulikowski

viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices.
This fix changes its type to match pointer size.
Signed-off-by Mateusz Kulikowski <[email protected]>

Best regards,
Marek Vasut

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #10 lore raw

PATCH v3 8/21 usb: ulpi: Fix compile warning in read/write on 64-bit machines.

ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32.

This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit.

It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing.

This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 drivers/usb/ulpi/ulpi-viewport.c | 5 +++--
 include/usb/ulpi.h               | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

drivers/usb/ulpi/ulpi-viewport.c +3 -2

index 72a06de..d111680 100644
@@ -92,7 +92,8 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
 
 int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 {
-	u32 val = ULPI_RWRUN | ULPI_RWCTRL | ((u32)reg << 16) | (value & 0xff);
+	u32 addr = (uintptr_t)reg & 0xFF;
+	u32 val = ULPI_RWRUN | ULPI_RWCTRL | addr << 16 | (value & 0xff);
 
 	val |= (ulpi_vp->port_num & 0x7) << 24;
 	return ulpi_request(ulpi_vp, val);

@@ -101,7 +102,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
 u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
 {
 	int err;
-	u32 val = ULPI_RWRUN | ((u32)reg << 16);
+	u32 val = ULPI_RWRUN | ((uintptr_t)reg & 0xFF) << 16;
 
 	val |= (ulpi_vp->port_num & 0x7) << 24;
 	err = ulpi_request(ulpi_vp, val);

include/usb/ulpi.h +2 -0

index dfea395..747fb0a 100644
@@ -123,6 +123,7 @@ int ulpi_reset(struct ulpi_viewport *ulpi_vp);
 /*
  * Write to the ULPI PHY register via the viewport.
  * @reg		- the ULPI register (one of the fields in struct ulpi_regs).
+ *		  Due to ULPI design, only 8 lsb of address are used.
  * @value	- the value - only 8 lower bits are used, others ignored.
  *
  * returns 0 on success, ULPI_ERROR on failure.

@@ -132,6 +133,7 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value);
 /*
  * Read the ULPI PHY register content via the viewport.
  * @reg		- the ULPI register (one of the fields in struct ulpi_regs).
+ *		  Due to ULPI design, only 8 lsb of address are used.
  *
  * returns register content on success, ULPI_ERROR on failure.
  */

Signature · 1 line

2.5.0

Marek Vasut

2016-03-14 17:24 UTC #11 lore raw

PATCH v3 8/21 usb: ulpi: Fix compile warning in read/write on 64-bit machines.

Quoted 7 lines · Mateusz Kulikowski

ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32.
This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit.

Quoted 8 lines

It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing.
This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range.
Signed-off-by Mateusz Kulikowski <[email protected]>

Signature · 2 lines

Best regards,
Marek Vasut

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #12 lore raw

PATCH v3 9/21 eth: asix88179: Print packet length properly

Debug printf used '%u' to print size_t variable.
This caused warnings on 64-bit machines.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3:
- New patch

Changes in v2: None
Changes in v1: None

 drivers/usb/eth/asix88179.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/usb/eth/asix88179.c +1 -1

index cf4085d..5e1ea86 100644
@@ -497,7 +497,7 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
 				length + sizeof(packet_len) + sizeof(tx_hdr2),
 				&actual_len,
 				USB_BULK_SEND_TIMEOUT);
-	debug("Tx: len = %u, actual = %u, err = %d\n",
+	debug("Tx: len = %zu, actual = %u, err = %d\n",
 	      length + sizeof(packet_len), actual_len, err);
 
 	return err;

Signature · 1 line

2.5.0

Marek Vasut

2016-03-14 17:24 UTC #13 lore raw

PATCH v3 9/21 eth: asix88179: Print packet length properly

Quoted 4 lines · Mateusz Kulikowski

Debug printf used '%u' to print size_t variable.
This caused warnings on 64-bit machines.
Signed-off-by Mateusz Kulikowski <[email protected]>

Best regards,
Marek Vasut

Joe Hershberger

2016-03-25 21:18 UTC #14 lore raw

PATCH v3 9/21 eth: asix88179: Print packet length properly

Quoted 4 lines · Mateusz Kulikowski

Debug printf used '%u' to print size_t variable.
This caused warnings on 64-bit machines.
Signed-off-by Mateusz Kulikowski <[email protected]>

Acked-by Joe Hershberger <[email protected]>

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #15 lore raw

PATCH v3 10/21 usb: Rename ehci-fsl.h to ehci-ci.h

Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs).

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add acked-by

Changes in v1: None

 drivers/usb/host/ehci-fsl.c           | 2 +-
 drivers/usb/host/ehci-mpc512x.c       | 2 +-
 drivers/usb/host/ehci-mx5.c           | 2 +-
 drivers/usb/host/ehci-mx6.c           | 2 +-
 drivers/usb/host/ehci-mxc.c           | 2 +-
 drivers/usb/host/ehci-vf.c            | 2 +-
 drivers/usb/host/ehci-zynq.c          | 2 +-
 include/usb/{ehci-fsl.h => ehci-ci.h} | 6 +++---
 8 files changed, 10 insertions(+), 10 deletions(-)
 rename include/usb/{ehci-fsl.h => ehci-ci.h} (99%)

drivers/usb/host/ehci-fsl.c +1 -1

index 97b7f14..4bcea9d 100644
@@ -12,7 +12,7 @@
 #include <pci.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <hwconfig.h>
 #include <fsl_usb.h>
 #include <fdt_support.h>

drivers/usb/host/ehci-mpc512x.c +1 -1

index b320c4a..4b50ac8 100644
@@ -17,7 +17,7 @@
 #include <pci.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 
 #include "ehci.h"

drivers/usb/host/ehci-mx5.c +1 -1

index d319962..2b36ceb 100644
@@ -9,7 +9,7 @@
 #include <usb.h>
 #include <errno.h>
 #include <linux/compiler.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>

drivers/usb/host/ehci-mx6.c +1 -1

index e1c67f7..a981b50 100644
@@ -10,7 +10,7 @@
 #include <errno.h>
 #include <wait_bit.h>
 #include <linux/compiler.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>

drivers/usb/host/ehci-mxc.c +1 -1

index f09c75a..f8324ee 100644
@@ -9,7 +9,7 @@
 #include <usb.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <errno.h>
 
 #include "ehci.h"

drivers/usb/host/ehci-vf.c +1 -1

index 335e303..61789dd 100644
@@ -17,7 +17,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/regs-usbphy.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 
 #include "ehci.h"

drivers/usb/host/ehci-zynq.c +1 -1

index 7770d05..37a7935 100644
@@ -11,7 +11,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <usb/ulpi.h>
 
 #include "ehci.h"

include/usb/ehci-ci.h renamed from include/usb/ehci-fsl.h +3 -3

similarity index 99%
rename from include/usb/ehci-fsl.h
rename to include/usb/ehci-ci.h
index e9349b5..725aec5 100644
@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _EHCI_FSL_H
-#define _EHCI_FSL_H
+#ifndef _EHCI_CI_H
+#define _EHCI_CI_H
 
 #include <asm/processor.h>

@@ -285,4 +285,4 @@ int usb_phy_mode(int port);
 int board_ehci_hcd_init(int port);
 int board_usb_phy_mode(int port);
 
-#endif /* _EHCI_FSL_H */
+#endif /* _EHCI_CI_H */

Signature · 1 line

2.5.0

Tom Rini

2016-03-27 13:36 UTC #16 lore raw

PATCH v3 10/21 usb: Rename ehci-fsl.h to ehci-ci.h

Quoted 10 lines · Mateusz Kulikowski

Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs).
Signed-off-by Mateusz Kulikowski <[email protected]>
Acked-by Marek Vasut <[email protected]>
Tested-by Simon Glass <[email protected]>

This misses about 10 files, easily found with a 'git grep -l usb/ehci-fsl.h', please respin, thanks.

Signature · 8 lines

Tom
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Mateusz Kulikowski

author

2016-03-13 21:36 UTC #17 lore raw

PATCH v3 11/21 usb: ehci-ci: Add missing registers.

Some registers of usb_ehci were marked as reserved.
This may be true for some variants of Chipidea USB core, but they have meaning on other devices.

The following registers were added:
sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers.

Signed-off-by Mateusz Kulikowski <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add reviewed-by

Changes in v1: None

 include/usb/ehci-ci.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

include/usb/ehci-ci.h +5 -1

index 725aec5..305b180 100644
@@ -191,7 +191,11 @@ struct usb_ehci {
 	u32     gptimer1_ld;	/* 0x088 - General Purpose Timer 1 load value */
 	u32     gptimer1_ctrl;	/* 0x08C - General Purpose Timer 1 control */
 	u32	sbuscfg;	/* 0x090 - System Bus Interface Control */
-	u8	res2[0x6C];
+	u32	sbusstatus;	/* 0x094 - System Bus Interface Status */
+	u32	sbusmode;	/* 0x098 - System Bus Interface Mode */
+	u32	genconfig;	/* 0x09C - USB Core Configuration */
+	u32	genconfig2;	/* 0x0A0 - USB Core Configuration 2 */
+	u8	res2[0x5c];
 	u8	caplength;	/* 0x100 - Capability Register Length */
 	u8	res3[0x1];
 	u16	hciversion;	/* 0x102 - Host Interface Version */

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #18 lore raw

PATCH v3 12/21 ehci-ci.h: drop generic USBCMD fields

Use definitions from ehci.h instead.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add Acked-by

Changes in v1: None

 drivers/usb/host/ehci-mpc512x.c | 4 ++--
 include/usb/ehci-ci.h           | 4 ----
 2 files changed, 2 insertions(+), 6 deletions(-)

drivers/usb/host/ehci-mpc512x.c +2 -2

index 4b50ac8..bb4f461 100644
@@ -93,7 +93,7 @@ static int reset_usb_controller(volatile struct usb_ehci *ehci)
 	unsigned int i;
 
 	/* Command a reset of the USB Controller */
-	out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST);
+	out_be32(&(ehci->usbcmd), CMD_RESET);
 
 	/* Wait for the reset process to finish */
 	for (i = 65535 ; i > 0 ; i--) {

@@ -101,7 +101,7 @@ static int reset_usb_controller(volatile struct usb_ehci *ehci)
 		 * The host will set this bit to zero once the
 		 * reset process is complete
 		 */
-		if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0)
+		if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0)
 			return 0;
 	}

include/usb/ehci-ci.h +0 -4

index 305b180..586d32a 100644
@@ -97,10 +97,6 @@
 #define INTR_DATA_PULSING_EN	(0x1<<30)
 #define INTSTS_MASK		(0x00ff0000)
 
-/* USBCMD Bits of interest */
-#define EHCI_FSL_USBCMD_RST	(1 <<  1)
-#define EHCI_FSL_USBCMD_RS	(1 <<  0)
-
 #define  INTERRUPT_ENABLE_BITS_MASK  \
 		(INTR_USB_ID_EN		| \
 		INTR_1MS_TIMER_EN	| \

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #19 lore raw

PATCH v3 13/21 ehci: Add support for Qualcomm EHCI

This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Use PORT_... macro to write to portsc
- Remove extra whitespace in probe()
- Add acked-by

Changes in v1:
- Reordered header files
- Removed braces around constant
- Added more verbose help to KConfig
- Added ULPI dependency to Kconfig
- Drop register #defines - use ehci-ci.h instead
- Create fixed ulpi viewport for device
- Use setbits/clearbits where possible
- Use wait_for_bit to reset controller
- Add dt binding documents

 doc/device-tree-bindings/usb/ehci-msm.txt |  10 ++
 drivers/usb/host/Kconfig                  |  11 ++
 drivers/usb/host/Makefile                 |   1 +
 drivers/usb/host/ehci-msm.c               | 178 ++++++++++++++++++++++++++++++
 4 files changed, 200 insertions(+)
 create mode 100644 doc/device-tree-bindings/usb/ehci-msm.txt
 create mode 100644 drivers/usb/host/ehci-msm.c

doc/device-tree-bindings/usb/ehci-msm.txt new file +10 -0

new file mode 100644
index 0000000..205bb07
@@ -0,0 +1,10 @@
+Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
+
+Required properties:
+- compatible: must be "qcom,ehci-host"
+- reg: start address and size of the registers
+
+ehci at 78d9000 {
+	compatible = "qcom,ehci-host";
+	reg = <0x78d9000 0x400>;
+};

drivers/usb/host/Kconfig +11 -0

index 9332374..d2363c8 100644
@@ -74,6 +74,17 @@ config USB_EHCI_MX6
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
 
+config USB_EHCI_MSM
+	bool "Support for Qualcomm on-chip EHCI USB controller"
+	depends on DM_USB
+	select USB_ULPI_VIEWPORT
+	default n
+	---help---
+	  Enables support for the on-chip EHCI controller on Qualcomm
+	  Snapdragon SoCs.
+	  This driver supports combination of Chipidea USB controller
+	  and Synapsys USB PHY in host mode only.
+
 config USB_EHCI_GENERIC
 	bool "Support for generic EHCI USB controller"
 	depends on OF_CONTROL

drivers/usb/host/Makefile +1 -0

index 9a87d2b..507519e 100644
@@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
 obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
 obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
+obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o

drivers/usb/host/ehci-msm.c new file +178 -0

178 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #20 lore raw

PATCH v3 14/21 drivers: Add SPMI bus uclass

Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Use proper entry order in Kconfig
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Fix header ordering
- Add reviewed-by

Changes in v1:
- Reorder includes
- Add read/write arguments documentation

 drivers/Kconfig            |  2 ++
 drivers/Makefile           |  1 +
 drivers/spmi/Kconfig       | 10 ++++++++++
 drivers/spmi/Makefile      |  7 +++++++
 drivers/spmi/spmi-uclass.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++
 include/dm/uclass-id.h     |  1 +
 include/spmi/spmi.h        | 47 +++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 116 insertions(+)
 create mode 100644 drivers/spmi/Kconfig
 create mode 100644 drivers/spmi/Makefile
 create mode 100644 drivers/spmi/spmi-uclass.c
 create mode 100644 include/spmi/spmi.h

drivers/Kconfig +2 -0

index 70993fd..c82a94b 100644
@@ -60,6 +60,8 @@ source "drivers/sound/Kconfig"
 
 source "drivers/spi/Kconfig"
 
+source "drivers/spmi/Kconfig"
+
 source "drivers/thermal/Kconfig"
 
 source "drivers/timer/Kconfig"

drivers/Makefile +1 -0

index e7eab66..6900097 100644
@@ -54,6 +54,7 @@ obj-y += dfu/
 obj-$(CONFIG_X86) += pch/
 obj-y += rtc/
 obj-y += sound/
+obj-y += spmi/
 obj-y += timer/
 obj-y += tpm/
 obj-y += twserial/

drivers/spmi/Kconfig new file +10 -0

new file mode 100644
index 0000000..0b9bd31
@@ -0,0 +1,10 @@
+menu "SPMI support"
+
+config SPMI
+	bool "Enable SPMI bus support"
+	depends on DM
+	---help---
+	  Select this to enable to support SPMI bus.
+	  SPMI (System Power Management Interface) bus is used
+	  to connect PMIC devices on various SoCs.
+endmenu

drivers/spmi/Makefile new file +7 -0

new file mode 100644
index 0000000..99092eb
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPMI)  += spmi-uclass.o

drivers/spmi/spmi-uclass.c new file +48 -0

48 lines not on this page · raw message

include/dm/uclass-id.h +1 -0

index 3bea308..917d550 100644
@@ -65,6 +65,7 @@ enum uclass_id {
 	UCLASS_RTC,		/* Real time clock device */
 	UCLASS_SERIAL,		/* Serial UART */
 	UCLASS_SPI,		/* SPI bus */
+	UCLASS_SPMI,		/* System Power Management Interface bus */
 	UCLASS_SPI_FLASH,	/* SPI flash */
 	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
 	UCLASS_SYSCON,		/* System configuration device */

include/spmi/spmi.h new file +47 -0

47 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #21 lore raw

PATCH v3 15/21 spmi: Add sandbox test driver

This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3:
- Updated test.dts to include SPMI like sandbox.dts does

Changes in v2:
- Rename CONFIG_DM_SPMI -> CONFIG_SPMI
- Rename r -> regs, p -> priv
- Add reviewed-by
- Update binding doc (drop unused bindig)

Changes in v1: None

 arch/sandbox/dts/sandbox.dts                   |  20 ++++
 arch/sandbox/dts/test.dts                      |  20 ++++
 configs/sandbox_defconfig                      |   4 +
 doc/device-tree-bindings/spmi/spmi-sandbox.txt |  31 +++++
 drivers/spmi/Kconfig                           |   8 ++
 drivers/spmi/Makefile                          |   1 +
 drivers/spmi/spmi-sandbox.c                    | 157 +++++++++++++++++++++++++
 test/dm/Makefile                               |   1 +
 test/dm/spmi.c                                 | 115 ++++++++++++++++++
 9 files changed, 357 insertions(+)
 create mode 100644 doc/device-tree-bindings/spmi/spmi-sandbox.txt
 create mode 100644 drivers/spmi/spmi-sandbox.c
 create mode 100644 test/dm/spmi.c

arch/sandbox/dts/sandbox.dts +20 -0

index e3f02bf..2ae4014 100644
@@ -240,6 +240,26 @@
 		status = "disabled";
 	};
 
+	spmi: spmi at 0 {
+		compatible = "sandbox,spmi";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		pm8916 at 0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0x0 0x1>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+
+			spmi_gpios: gpios at c000 {
+				compatible = "qcom,pm8916-gpio";
+				reg = <0xc000 0x400>;
+				gpio-controller;
+				gpio-count = <4>;
+				#gpio-cells = <2>;
+				gpio-bank-name="spmi";
+			};
+		};
+	};
 };
 
 #include "cros-ec-keyboard.dtsi"

arch/sandbox/dts/test.dts +20 -0

index 9b8d658..8930009 100644
@@ -351,6 +351,26 @@
 		status = "disabled";
 	};
 
+	spmi: spmi at 0 {
+		compatible = "sandbox,spmi";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		pm8916 at 0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0x0 0x1>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+
+			spmi_gpios: gpios at c000 {
+				compatible = "qcom,pm8916-gpio";
+				reg = <0xc000 0x400>;
+				gpio-controller;
+				gpio-count = <4>;
+				#gpio-cells = <2>;
+				gpio-bank-name="spmi";
+			};
+		};
+	};
 };
 
 #include "sandbox_pmic.dtsi"

configs/sandbox_defconfig +4 -0

index 02534bf..d77710d 100644
@@ -30,6 +30,7 @@ CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_CLK=y
 CONFIG_SANDBOX_GPIO=y
+CONFIG_PM8916_GPIO=y
 CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y

@@ -58,6 +59,9 @@ CONFIG_PINCONF=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_PM8916=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_SANDBOX=y
 CONFIG_RAM=y

doc/device-tree-bindings/spmi/spmi-sandbox.txt new file +31 -0

new file mode 100644
index 0000000..8569a1a
@@ -0,0 +1,31 @@
+Sandbox SPMI emulated arbiter.
+
+This is bus driver for Sandbox. It includes part of emulated pm8916 pmic.
+
+Required properties:
+- compatible: "sandbox,spmi"
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+Example:
+
+spmi: spmi at 0 {
+	compatible = "sandbox,spmi";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	pm8916 at 0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x0 0x1>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+
+		spmi_gpios: gpios at c000 {
+			compatible = "qcom,pm8916-gpio";
+			reg = <0xc000 0x400>;
+			gpio-controller;
+			gpio-count = <4>;
+			#gpio-cells = <2>;
+			gpio-bank-name="spmi";
+		};
+	};
+};

drivers/spmi/Kconfig +8 -0

index 0b9bd31..c70d675 100644
@@ -7,4 +7,12 @@ config SPMI
 	  Select this to enable to support SPMI bus.
 	  SPMI (System Power Management Interface) bus is used
 	  to connect PMIC devices on various SoCs.
+
+config SPMI_SANDBOX
+	boolean "Support for Sandbox SPMI bus"
+	depends on SPMI
+	---help---
+	  Demo SPMI bus implementation. Emulates part of PM8916 as single
+          slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
+
 endmenu

drivers/spmi/Makefile +1 -0

index 99092eb..4ca65a9 100644
@@ -5,3 +5,4 @@
 #
 
 obj-$(CONFIG_SPMI)  += spmi-uclass.o
+obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o

drivers/spmi/spmi-sandbox.c new file +157 -0

157 lines not on this page · raw message

test/dm/Makefile +1 -0

index fd0198f..ab33cd6 100644
@@ -36,4 +36,5 @@ obj-$(CONFIG_DM_REGULATOR) += regulator.o
 obj-$(CONFIG_TIMER) += timer.o
 obj-$(CONFIG_DM_VIDEO) += video.o
 obj-$(CONFIG_ADC) += adc.o
+obj-$(CONFIG_SPMI) += spmi.o
 endif

test/dm/spmi.c new file +115 -0

115 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #22 lore raw

PATCH v3 16/21 drivers: spmi: Add support for Qualcomm SPMI bus driver

Support SPMI arbiter on Qualcomm Snapdragon devices.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Rename p -> priv (in write/read)
- Fix header ordering (again)
- Add reviewed-by

Changes in v1:
- add binding documentation and better Kconfig help
- Changed a bit mapping
- Change include order
- Use clrsetbits* where possible
- Add one more supported dts id
- Handle missing fields in dt properly

 doc/device-tree-bindings/spmi/spmi-msm.txt |  26 ++++
 drivers/spmi/Kconfig                       |   7 +-
 drivers/spmi/Makefile                      |   1 +
 drivers/spmi/spmi-msm.c                    | 189 +++++++++++++++++++++++++++++
 4 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 doc/device-tree-bindings/spmi/spmi-msm.txt
 create mode 100644 drivers/spmi/spmi-msm.c

doc/device-tree-bindings/spmi/spmi-msm.txt new file +26 -0

new file mode 100644
index 0000000..ae47673
@@ -0,0 +1,26 @@
+Qualcomm SPMI arbiter/bus driver
+
+This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
+
+Required properties:
+- compatible: "qcom,spmi-pmic-arb"
+- reg: Register block adresses and sizes for various parts of device:
+   1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
+   2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
+   3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
+
+Optional properties (if not set by parent):
+- #address-cells: 0x1 - childs slave ID address
+- #size-cells: 0x1
+
+All PMICs should be placed as a child nodes of bus arbiter.
+Automatic detection of childs is currently not supported.
+
+Example:
+
+spmi at 200f000 {
+	compatible = "qcom,spmi-pmic-arb";
+	reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+};

drivers/spmi/Kconfig +6 -1

index c70d675..8d25b45 100644
@@ -8,11 +8,16 @@ config SPMI
 	  SPMI (System Power Management Interface) bus is used
 	  to connect PMIC devices on various SoCs.
 
+config SPMI_MSM
+	boolean "Support Qualcomm SPMI bus"
+	depends on SPMI
+	---help---
+	  Support SPMI bus implementation found on Qualcomm Snapdragon SoCs.
+
 config SPMI_SANDBOX
 	boolean "Support for Sandbox SPMI bus"
 	depends on SPMI
 	---help---
 	  Demo SPMI bus implementation. Emulates part of PM8916 as single
           slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
-
 endmenu

drivers/spmi/Makefile +1 -0

index 4ca65a9..c0b1220 100644
@@ -5,4 +5,5 @@
 #
 
 obj-$(CONFIG_SPMI)  += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
 obj-$(CONFIG_SPMI_SANDBOX) += spmi-sandbox.o

drivers/spmi/spmi-msm.c new file +189 -0

189 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #23 lore raw

PATCH v3 17/21 pmic: Add support for Qualcomm PM8916 PMIC

This PMIC is connected on SPMI bus so needs SPMI support enabled.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add reviewed-by
- Reordered Kconfig & Makefile (to keep alphabetical ordering)
- Added link to dt binding @ help

Changes in v1:
- Added dt bindings
- Reoder includes
- Replaced extract_* macros with ordinary shift/mask
- Added error checking and whitespaces in probe

 doc/device-tree-bindings/pmic/pm8916.txt | 18 ++++++
 drivers/power/pmic/Kconfig               | 16 ++++++
 drivers/power/pmic/Makefile              |  1 +
 drivers/power/pmic/pm8916.c              | 96 ++++++++++++++++++++++++++++++++
 4 files changed, 131 insertions(+)
 create mode 100644 doc/device-tree-bindings/pmic/pm8916.txt
 create mode 100644 drivers/power/pmic/pm8916.c

doc/device-tree-bindings/pmic/pm8916.txt new file +18 -0

new file mode 100644
index 0000000..15c598b
@@ -0,0 +1,18 @@
+Qualcomm pm8916 PMIC
+
+This PMIC is connected using SPMI bus so should be child of SPMI bus controller.
+
+Required properties:
+- compatible: "qcom,spmi-pmic";
+- reg: SPMI Slave ID, size (ignored)
+- #address-cells: 0x1 (peripheral ID)
+- #size-cells: 0x1 (size of peripheral register space)
+
+Example:
+
+pm8916 at 0 {
+	compatible = "qcom,spmi-pmic";
+	reg = <0x0 0x1>;
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+};

drivers/power/pmic/Kconfig +16 -0

index 7f69ae1..69f8d51 100644
@@ -54,6 +54,22 @@ config DM_PMIC_MAX77686
 	This config enables implementation of driver-model pmic uclass features
 	for PMIC MAX77686. The driver implements read/write operations.
 
+config PMIC_PM8916
+	bool "Enable Driver Model for Qualcomm PM8916 PMIC"
+	depends on DM_PMIC
+	---help---
+	The PM8916 is a PMIC connected to one (or several) processors
+	with SPMI bus. It has 2 slaves with several peripherals:
+	- 18x LDO
+	- 4x GPIO
+	- Power and Reset buttons
+	- Watchdog
+	- RTC
+	- Vibrator drivers
+	- Others
+
+	Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt
+
 config PMIC_RK808
 	bool "Enable support for Rockchip PMIC RK808"
 	depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index c6e8d0c..52b4f71 100644
@@ -11,6 +11,7 @@ obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
+obj-$(CONFIG_PMIC_PM8916) += pm8916.o
 obj-$(CONFIG_PMIC_RK808) += rk808.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

drivers/power/pmic/pm8916.c new file +96 -0

96 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #24 lore raw

PATCH v3 18/21 gpio: Add support for Qualcomm PM8916 gpios

This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Add Reviewed-by

Changes in v1:
- Add binding doc
- Fixed inlcude ordering
- Merged direction_input and direction_output functions
- gpio_get: use switch instead of stacked if
- use pmic_clrsetbits
- add possibility to change prwkey bank name
- Handle invalid bindings
- Sanity HW check (i.e. check type/subtype registers)

 doc/device-tree-bindings/gpio/pm8916_gpio.txt |  48 ++++
 drivers/gpio/Kconfig                          |  10 +
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/pm8916_gpio.c                    | 302 ++++++++++++++++++++++++++
 4 files changed, 361 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/pm8916_gpio.txt
 create mode 100644 drivers/gpio/pm8916_gpio.c

doc/device-tree-bindings/gpio/pm8916_gpio.txt new file +48 -0

new file mode 100644
index 0000000..58185b8
@@ -0,0 +1,48 @@
+Driver for part of pm8916 PMIC - gpio and power/reset keys
+
+This device should be child of SPMI pmic.
+
+1) GPIO driver
+
+Required properties:
+- compatible: "qcom,pm8916-gpio"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- gpio-count: number of GPIOs
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916" is used)
+
+Example:
+
+pmic_gpios: gpios at c000 {
+	compatible = "qcom,pm8916-gpio";
+	reg = <0xc000 0x400>;
+	gpio-controller;
+	gpio-count = <4>;
+	#gpio-cells = <2>;
+	gpio-bank-name="pmic";
+};
+
+
+2) Power/Reset key driver
+
+Required properties:
+- compatible: "qcom,pm8916-pwrkey"
+- reg: peripheral ID, size of register block
+- gpio-controller
+- #gpio-cells: 2
+
+Optional properties:
+- gpio-bank-name: name of bank (as default "pm8916_key" is used)
+
+
+Example:
+
+pmic_pon: pon at 800 {
+	compatible = "qcom,pm8916-pwrkey";
+	reg = <0x800 0x96>;
+	#gpio-cells = <2>;
+	gpio-controller;
+};

drivers/gpio/Kconfig +10 -0

index befb4af..7b4f0ed 100644
@@ -60,6 +60,16 @@ config MSM_GPIO
 	  - APQ8016
 	  - MSM8916
 
+config PM8916_GPIO
+	bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
+	depends on DM_GPIO && PMIC_PM8916
+	help
+	  Support for GPIO pins and power/reset buttons found on
+	  Qualcomm PM8916 PMIC.
+	  Default name for GPIO bank is "pm8916".
+	  Power and reset buttons are placed in "pm8916_key" bank and
+          have gpio numbers 0 and 1 respectively.
+
 config ROCKCHIP_GPIO
 	bool "Rockchip GPIO driver"
 	depends on DM_GPIO

drivers/gpio/Makefile +1 -0

index 830d7a6..fe06f8e 100644
@@ -49,3 +49,4 @@ obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)	+= hi6220_gpio.o
 obj-$(CONFIG_PIC32_GPIO)	+= pic32_gpio.o
 obj-$(CONFIG_MSM_GPIO)		+= msm_gpio.o
+obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o

drivers/gpio/pm8916_gpio.c new file +302 -0

302 lines not on this page · raw message

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #25 lore raw

PATCH v3 19/21 arm: Add support for Qualcomm Snapdragon family

First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3: None
Changes in v2:
- Rename DM_SPMI -> SPMI
- Make MND divider comments more compact :)
- p -> priv
- Add reviewed-by
- Reordered Kconfig to keep alphabetical order
- Renamed reset_sandbox -> msm_reset (typo in reset.c)

Changes in v1:
- Fix include order
- Cleanup defines (added spaces for readibility)
- Base address is integer to avoid casting
- Use setbits_* family where possible
- Drop unneded comments, added newlines where needed
- Check return value of dev_get_addr
- Add binding for apq8016
- Cleaned up divider calculation
- Drop most of gpio.h (only empty file is needed)

 arch/arm/Kconfig                                   |  12 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/mach-snapdragon/Kconfig                   |   6 +
 arch/arm/mach-snapdragon/Makefile                  |   8 +
 arch/arm/mach-snapdragon/clock-apq8016.c           | 262 +++++++++++++++++++++
 arch/arm/mach-snapdragon/include/mach/gpio.h       |   9 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  14 ++
 arch/arm/mach-snapdragon/reset.c                   |  40 ++++
 8 files changed, 352 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/Kconfig
 create mode 100644 arch/arm/mach-snapdragon/Makefile
 create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
 create mode 100644 arch/arm/mach-snapdragon/reset.c

arch/arm/Kconfig +12 -0

index 6e5544f..2cb96e2 100644
@@ -504,6 +504,16 @@ config RMOBILE
 	bool "Renesas ARM SoCs"
 	select CPU_V7
 
+config ARCH_SNAPDRAGON
+	bool "Qualcomm Snapdragon SoCs"
+	select ARM64
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+	select SPMI
+	select OF_CONTROL
+	select OF_SEPARATE
+
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7

@@ -762,6 +772,8 @@ source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
 
+source "arch/arm/mach-snapdragon/Kconfig"
+
 source "arch/arm/mach-socfpga/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"

arch/arm/Makefile +1 -0

index 6defdfb..bb2666c 100644
@@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
+machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_STM32)			+= stm32

arch/arm/mach-snapdragon/Kconfig new file +6 -0

new file mode 100644
index 0000000..156e733
@@ -0,0 +1,6 @@
+if ARCH_SNAPDRAGON
+
+config SYS_SOC
+	default "snapdragon"
+
+endif

arch/arm/mach-snapdragon/Makefile new file +8 -0

new file mode 100644
index 0000000..8e84705
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clock-apq8016.o
+obj-y += reset.o

arch/arm/mach-snapdragon/clock-apq8016.c new file +262 -0

262 lines not on this page · raw message

arch/arm/mach-snapdragon/include/mach/gpio.h new file +9 -0

new file mode 100644
index 0000000..ff949b2
@@ -0,0 +1,9 @@
+/*
+ * Empty gpio.h
+ *
+ * This file must stay as arch/arm/include/asm/gpio.h requires it.
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */

arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h new file +14 -0

new file mode 100644
index 0000000..cdbfad0
@@ -0,0 +1,14 @@
+/*
+ * Qualcomm APQ8916 sysmap
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8016_H
+#define _MACH_SYSMAP_APQ8016_H
+
+#define GICD_BASE 0x0b000000
+#define GICC_BASE 0x0a20c000
+
+#endif

arch/arm/mach-snapdragon/reset.c new file +40 -0

new file mode 100644
index 0000000..2627eec
@@ -0,0 +1,40 @@
+/*
+ * Qualcomm APQ8016 reset controller driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int msm_reset_request(struct udevice *dev, enum reset_t type)
+{
+	phys_addr_t addr = dev_get_addr(dev);
+	if (!addr)
+		return -EINVAL;
+	writel(0, addr);
+	return -EINPROGRESS;
+}
+
+static struct reset_ops msm_reset_ops = {
+	.request	= msm_reset_request,
+};
+
+static const struct udevice_id msm_reset_ids[] = {
+	{ .compatible = "qcom,pshold" },
+	{ }
+};
+
+U_BOOT_DRIVER(msm_reset) = {
+	.name		= "msm_reset",
+	.id		= UCLASS_RESET,
+	.of_match	= msm_reset_ids,
+	.ops		= &msm_reset_ops,
+};

Signature · 1 line

2.5.0

Mateusz Kulikowski

author

2016-03-13 21:36 UTC #26 lore raw

PATCH v3 20/21 board: Add Qualcomm Dragonboard 410C support

This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC

U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.

Signed-off-by Mateusz Kulikowski <[email protected]>

---

Changes in v3:
- readme: Added info on how to enter fastboot mode and that dtbTool is also part of skales. Added more explanation on image generation.
- head: Add comment why it's needed, drop MZ EFI signature that makes no sense on this particular SoC, fix confusing entry point name (+update .lds file)

Changes in v2:
- Renamed CONFIG_DM_SPMI -> CONFIG_SPMI
- Removed extra enter in dragonboard file
- Added ULPI* to defconfig
- Added MAINTAINERS to board
- Cleaned up config file - use distro defaults/environment:
- Dropped multiple CONFIG_CMD* and other CONFIG_*
- Added distro env/config
- Dropped old boot commands
- Split dts - pm8916_gpio entries are taken directly from Linux Dragonboard dts; Add handles for u-boot in -uboot.dtsi; They will be removed once gpio drivers are converted to pinctrl.
- Renamed some pmic nodes, fixed dragonboard.c to find them properly.
- Added header and converted comments to c98-style in head.S
- Print error if pmic gpio node is not found.

Changes in v1:
- Add better help for dragonboard
- Move static structures to board_prepare_usb
- Add DM_SPMI to defconfig

 arch/arm/dts/Makefile                            |   2 +
 arch/arm/dts/dragonboard410c-uboot.dtsi          |  28 +++++
 arch/arm/dts/dragonboard410c.dts                 | 148 ++++++++++++++++++++++
 arch/arm/mach-snapdragon/Kconfig                 |  20 +++
 board/qualcomm/dragonboard410c/Kconfig           |  15 +++
 board/qualcomm/dragonboard410c/MAINTAINERS       |   6 +
 board/qualcomm/dragonboard410c/Makefile          |   8 ++
 board/qualcomm/dragonboard410c/dragonboard410c.c | 131 +++++++++++++++++++
 board/qualcomm/dragonboard410c/head.S            |  34 +++++
 board/qualcomm/dragonboard410c/readme.txt        |  71 +++++++++++
 board/qualcomm/dragonboard410c/u-boot.lds        |  90 +++++++++++++
 configs/dragonboard410c_defconfig                |  31 +++++
 include/configs/dragonboard410c.h                | 153 +++++++++++++++++++++++
 13 files changed, 737 insertions(+)
 create mode 100644 arch/arm/dts/dragonboard410c-uboot.dtsi
 create mode 100644 arch/arm/dts/dragonboard410c.dts
 create mode 100644 board/qualcomm/dragonboard410c/Kconfig
 create mode 100644 board/qualcomm/dragonboard410c/MAINTAINERS
 create mode 100644 board/qualcomm/dragonboard410c/Makefile
 create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c
 create mode 100644 board/qualcomm/dragonboard410c/head.S
 create mode 100644 board/qualcomm/dragonboard410c/readme.txt
 create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds
 create mode 100644 configs/dragonboard410c_defconfig
 create mode 100644 include/configs/dragonboard410c.h

arch/arm/dts/Makefile +2 -0

index 578038b..3515bea 100644
@@ -105,6 +105,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb
 
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
 	sun4i-a10-ba10-tvbox.dtb \

arch/arm/dts/dragonboard410c-uboot.dtsi new file +28 -0

new file mode 100644
index 0000000..cc2c175
@@ -0,0 +1,28 @@
+/*
+ * U-Boot addition to handle Dragonboard 410c pins
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+&pm8916_gpios {
+	usb_hub_reset_pm {
+		gpios = <&pm8916_gpios 2 0>;
+	};
+
+	usb_sw_sel_pm {
+		gpios = <&pm8916_gpios 3 0>;
+	};
+};
+
+
+&pm8916_pon {
+	key_vol_down {
+		gpios = <&pm8916_pon 1 0>;
+	};
+
+	key_power {
+		gpios = <&pm8916_pon 0 0>;
+	};
+};

arch/arm/dts/dragonboard410c.dts new file +148 -0

148 lines not on this page · raw message

arch/arm/mach-snapdragon/Kconfig +20 -0

index 156e733..dc7ba21 100644
@@ -3,4 +3,24 @@ if ARCH_SNAPDRAGON
 config SYS_SOC
 	default "snapdragon"
 
+choice
+	prompt "Snapdragon board select"
+
+config TARGET_DRAGONBOARD410C
+	bool "96Boards Dragonboard 410C"
+	help
+	  Support for 96Boards Dragonboard 410C. This board complies with
+	  96Board Open Platform Specifications. Features:
+	  - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
+	  - 1GiB RAM
+	  - 8GiB eMMC, uSD slot
+	  - WiFi, Bluetooth and GPS module
+	  - 2x Host, 1x Device USB port
+	  - HDMI
+	  - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
+
+endchoice
+
+source "board/qualcomm/dragonboard410c/Kconfig"
+
 endif

board/qualcomm/dragonboard410c/Kconfig new file +15 -0

new file mode 100644
index 0000000..03bd7ae
@@ -0,0 +1,15 @@
+if TARGET_DRAGONBOARD410C
+
+config SYS_BOARD
+	default "dragonboard410c"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+config SYS_SOC
+	default "apq8016"
+
+config SYS_CONFIG_NAME
+	default "dragonboard410c"
+
+endif

board/qualcomm/dragonboard410c/MAINTAINERS new file +6 -0

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index 0000000..65cb47c
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+DRAGONBOARD410C BOARD
+M:	Mateusz Kulikowski <[email protected]>
+S:	Maintained
+F:	board/qualcomm/dragonboard410c/
+F:	include/configs/dragonboard410c.h
+F:	configs/dragonboard410c_defconfig

board/qualcomm/dragonboard410c/Makefile new file +8 -0

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+#
+# (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= dragonboard410c.o
+extra-y += head.o

board/qualcomm/dragonboard410c/dragonboard410c.c new file +131 -0

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board/qualcomm/dragonboard410c/head.S new file +34 -0

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+/*
+ * ARM64 header for proper chain-loading with Little Kernel.
+ *
+ * Little Kernel shipped with Dragonboard410C boots standard Linux images for
+ * ARM64. This file adds header that is required to boot U-Boot properly.
+ *
+ * For details see:
+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.global _arm64_header
+_arm64_header:
+	b _start
+	.word 0
+	/* Image load offset from start of RAM, little-endian */
+	.quad   CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1
+	/* Effective size of kernel image, little-endian */
+	.quad   0 /* 0x60000 - ignored */
+	/* Informative flags, little-endian */
+	.quad   0
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.quad   0                               /* reserved */
+	.byte   0x41                            /* Magic number, "ARM\x64" */
+	.byte   0x52
+	.byte   0x4d
+	.byte   0x64
+	.word   0                               /* reserved */

board/qualcomm/dragonboard410c/readme.txt new file +71 -0

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board/qualcomm/dragonboard410c/u-boot.lds new file +90 -0

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configs/dragonboard410c_defconfig new file +31 -0

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+CONFIG_ARM=y
+CONFIG_ARM64=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_TARGET_DRAGONBOARD410C=y
+
+CONFIG_SYS_PROMPT="dragonboard410c => "
+CONFIG_CMD_USB=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+
+CONFIG_CLK=y
+CONFIG_MSM_GPIO=y
+CONFIG_PM8916_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_MSM_SDHCI=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM=y
+CONFIG_MSM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_STORAGE=y

include/configs/dragonboard410c.h new file +153 -0

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Signature · 1 line

2.5.0

Tom Rini

2016-03-27 13:36 UTC #27 lore raw

PATCH v3 20/21 board: Add Qualcomm Dragonboard 410C support

Quoted 14 lines · Mateusz Kulikowski

This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC

Quoted 5 lines

U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by Mateusz Kulikowski <[email protected]>
Tested-by Simon Glass <[email protected]>

Two problems. One, OF_LIBFDT has moved to Kconfig, please update the defconfig _and_ re-run savedefconfig. Two, the MMU code has updated and you need to provide a mem_map. This shouldn't be hard, but I don't have the hardware and can't test a patch. Thanks!

Signature · 8 lines

Tom
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Mateusz Kulikowski

author

2016-03-13 21:36 UTC #28 lore raw

PATCH v3 21/21 Add myself as Snapdragon and SPMI maintainer

- Update MAINTAINERS
- Update git-mailrc

Signed-off-by Mateusz Kulikowski <[email protected]>