board: ti: DRA72: Add support for SR2.0 rev C evm

index 7f8c0a423bad..93d1efbca17d 100644
@@ -775,6 +775,7 @@ void __weak hw_data_init(void)
 	break;
 
 	case DRA722_ES1_0:
+	case DRA722_ES2_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
 	*omap_vcores = &dra722_volts;

@@ -807,6 +808,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_dra7xx_es1;
 		break;
 	case DRA722_ES1_0:
+	case DRA722_ES2_0:
 		*regs = &ioregs_dra72x_es1;
 		break;
 

index 8f184df2abb7..e3ac8bbe9524 100644
@@ -373,6 +373,9 @@ void init_omap_revision(void)
 	case DRA722_CONTROL_ID_CODE_ES1_0:
 		*omap_si_rev = DRA722_ES1_0;
 		break;
+	case DRA722_CONTROL_ID_CODE_ES2_0:
+		*omap_si_rev = DRA722_ES2_0;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}

index 7dc5bb7e4a4b..5cf360c41468 100644
@@ -438,6 +438,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		}
 		break;
 	case DRA722_ES1_0:
+	case DRA722_ES2_0:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;

@@ -670,6 +671,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
 	case DRA722_ES1_0:
+	case DRA722_ES2_0:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);

index b5b3838f4500..1eeb8d5f626f 100644
@@ -60,6 +60,7 @@
 #define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)

index aef31266ce9e..8c85f46db6ef 100644
@@ -700,6 +700,7 @@ static inline u8 is_dra72x(void)
 #define DRA752_ES1_1	0x07520110
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
+#define DRA722_ES2_0	0x07220200
 
 /*
  * SRAM scratch space entries

index 93d1efbca17d..b69c0d13715a 100644
@@ -743,6 +743,18 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
+const struct ctrl_ioregs ioregs_dra72x_es2 = {
+	.ctrl_ddrch = 0x40404040,
+	.ctrl_lpddr2ch = 0x40404040,
+	.ctrl_ddr3ch = 0x60606060,
+	.ctrl_ddrio_0 = 0x00094A40,
+	.ctrl_ddrio_1 = 0x00000000,
+	.ctrl_ddrio_2 = 0x00000000,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
 void __weak hw_data_init(void)
 {
 	u32 omap_rev = omap_revision();

@@ -808,9 +820,11 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_dra7xx_es1;
 		break;
 	case DRA722_ES1_0:
-	case DRA722_ES2_0:
 		*regs = &ioregs_dra72x_es1;
 		break;
+	case DRA722_ES2_0:
+		*regs = &ioregs_dra72x_es2;
+		break;
 
 	default:
 		printf("\n INVALID OMAP REVISION ");

index 5cf360c41468..7712923d8572 100644
@@ -398,6 +398,45 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 	0x0
 };
 
+const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
+	0x04040100,
+	0x006B009F,
+	0x006B00A2,
+	0x006B00A8,
+	0x006B00A8,
+	0x006B00B2,
+	0x002F002F,
+	0x002F002F,
+	0x002F002F,
+	0x002F002F,
+	0x002F002F,
+	0x00600073,
+	0x00600071,
+	0x0060007C,
+	0x0060007E,
+	0x00600084,
+	0x00400053,
+	0x00400051,
+	0x0040005C,
+	0x0040005E,
+	0x00400064,
+	0x00800080,
+	0x00800080,
+	0x40010080,
+	0x08102040,
+	0x005B008F,
+	0x005B0092,
+	0x005B0098,
+	0x005B0098,
+	0x005B00A2,
+	0x00300043,
+	0x00300041,
+	0x0030004C,
+	0x0030004E,
+	0x00300054,
+	0x00000077
+};
+
 const struct lpddr2_mr_regs mr_regs = {
 	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 	.mr2	= 0x6,

@@ -438,10 +477,13 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		}
 		break;
 	case DRA722_ES1_0:
-	case DRA722_ES2_0:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;
+	case DRA722_ES2_0:
+		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
+		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
+		break;
 	default:
 		*regs = ddr3_ext_phy_ctrl_const_base_es2;
 		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);

index 97174c8bb812..0461b53ba2f8 100644
@@ -32,8 +32,11 @@
 #include "../common/board_detect.h"
 
 #define board_is_dra74x_evm()		board_ti_is("5777xCPU")
+#define board_is_dra72x_evm()		board_ti_is("DRA72x-T")
 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&	\
 				(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() &&	\
+				(strncmp("C", board_ti_get_rev(), 1) <= 0)
 #define board_ti_get_emif_size()	board_ti_get_emif1_size() +	\
 					board_ti_get_emif2_size()
 

@@ -127,6 +130,31 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
 
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
+	.sdram_config_init              = 0x61862BB2,
+	.sdram_config                   = 0x61862BB2,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514D,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD1137824,
+	.sdram_tim2                     = 0x30B37FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400E,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400E,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 	.sdram_config_init              = 0x61851ab2,
 	.sdram_config                   = 0x61851ab2,

@@ -203,7 +231,11 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 		}
 		break;
 	case DRA722_ES1_0:
-		*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+	case DRA722_ES2_0:
+		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+		else
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 		break;
 	default:
 		*regs = &emif1_ddr3_532_mhz_1cs;

@@ -234,6 +266,18 @@ const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 	.is_ma_present	= 0x1
 };
 
+/*
+ * DRA722 EVM EMIF1 2GB CONFIGURATION
+ * EMIF1 4 devices of 512Mb x 8 Micron
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80700100,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 {
 	u64 ram_size;

@@ -250,8 +294,13 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 			*dmm_lisa_regs = &lisa_map_dra7_1536MB;
 		break;
 	case DRA722_ES1_0:
+	case DRA722_ES2_0:
 	default:
-		*dmm_lisa_regs = &lisa_map_2G_x_2;
+		if (ram_size < CONFIG_MAX_MEM_MAPPED)
+			*dmm_lisa_regs = &lisa_map_2G_x_2;
+		else
+			*dmm_lisa_regs = &lisa_map_2G_x_4;
+		break;
 	}
 }
 

@@ -324,8 +373,10 @@ void do_board_detect(void)
 
 	if (board_is_dra74x_evm()) {
 		bname = "DRA74x EVM";
-	/* If EEPROM is not populated */
+	} else if (board_is_dra72x_evm()) {
+		bname = "DRA72x EVM";
 	} else {
+		/* If EEPROM is not populated */
 		if (is_dra72x())
 			bname = "DRA72x EVM";
 		else

@@ -614,7 +665,7 @@ static inline void vtt_regulator_enable(void)
 		return;
 
 	/* Do not enable VTT for DRA722 */
-	if (omap_revision() == DRA722_ES1_0)
+	if (is_dra72x())
 		return;
 
 	/*

index 9fa6e6991f0e..744950f01bd9 100644
@@ -166,16 +166,14 @@ static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
 	return 0;
 }
 
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
-			   struct iodelay_cfg_entry const *iodelay,
-			   int niodelays)
+int __recalibrate_iodelay_start(void)
 {
 	int ret = 0;
 
 	/* IO recalibration should be done only from SRAM */
 	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
 		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
-		return;
+		return -1;
 	}
 
 	/* unlock IODELAY CONFIG registers */

@@ -191,23 +189,27 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
 		goto err;
 
 	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
-	if (ret)
-		goto err;
 
-	/* Configure Mux settings */
-	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+err:
+	return ret;
+}
 
-	/* Configure Manual IO timing modes */
-	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
-	if (ret)
-		goto err;
+void __recalibrate_iodelay_end(int ret)
+{
 
-	ret = isolate_io(DEISOLATE_IO);
+	/* IO recalibration should be done only from SRAM */
+	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+		return;
+	}
+
+	if (!ret)
+		ret = isolate_io(DEISOLATE_IO);
 
-err:
 	/* lock IODELAY CONFIG registers */
 	writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
 	       CFG_REG_8_OFFSET);
+
 	/*
 	 * UART cannot be used during IO recalibration sequence as IOs are in
 	 * isolation. So error handling and debug prints are done after

@@ -232,7 +234,41 @@ err:
 	case ERR_FPDE:
 		puts("IODELAY: FPDE calculation failed\n");
 		break;
+	case -1:
+		puts("IODELAY: Wrong Context call?\n");
+		break;
 	default:
 		debug("IODELAY: IO delay recalibration successfully completed\n");
 	}
+
+	return;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays)
+{
+	int ret = 0;
+
+	/* IO recalibration should be done only from SRAM */
+	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+		return;
+	}
+
+	ret = __recalibrate_iodelay_start();
+	if (ret)
+		goto err;
+
+	/* Configure Mux settings */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+	/* Configure Manual IO timing modes */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+	if (ret)
+		goto err;
+
+err:
+	__recalibrate_iodelay_end(ret);
+
 }

index 4cd0a3cc80d0..0de8a800c1a2 100644
@@ -83,5 +83,7 @@
 void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
 			   struct iodelay_cfg_entry const *iodelay,
 			   int niodelays);
+int __recalibrate_iodelay_start(void);
+void __recalibrate_iodelay_end(int ret);
 
 #endif

index 744950f01bd9..87987308aced 100644
@@ -138,8 +138,8 @@ static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
 	return reg;
 }
 
-static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
-			   int niodelays)
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+		   int niodelays)
 {
 	struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
 	u32 reg, cpde, fpde, i;

index 0de8a800c1a2..c99700403914 100644
@@ -86,4 +86,6 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
 int __recalibrate_iodelay_start(void);
 void __recalibrate_iodelay_end(int ret);
 
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+		   int niodelays);
 #endif

index 0461b53ba2f8..d975f8c575ab 100644
@@ -398,16 +398,29 @@ void set_muxconf_regs_essential(void)
 #ifdef CONFIG_IODELAY_RECALIBRATION
 void recalibrate_iodelay(void)
 {
-	struct pad_conf_entry const *pads;
+	struct pad_conf_entry const *pads, *delta_pads = NULL;
 	struct iodelay_cfg_entry const *iodelay;
-	int npads, niodelays;
+	int npads, niodelays, delta_npads = 0;
+	int ret;
 
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
-		pads = dra72x_core_padconf_array;
-		npads = ARRAY_SIZE(dra72x_core_padconf_array);
-		iodelay = dra72_iodelay_cfg_array;
-		niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array);
+	case DRA722_ES2_0:
+		pads = dra72x_core_padconf_array_common;
+		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
+		if (board_is_dra72x_revc_or_later()) {
+			delta_pads = dra72x_rgmii_padconf_array_revc;
+			delta_npads =
+				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
+			iodelay = dra72_iodelay_cfg_array_revc;
+			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
+		} else {
+			delta_pads = dra72x_rgmii_padconf_array_revb;
+			delta_npads =
+				ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
+			iodelay = dra72_iodelay_cfg_array_revb;
+			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
+		}
 		break;
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:

@@ -427,7 +440,24 @@ void recalibrate_iodelay(void)
 				      RGMII1_ID_MODE_N_MASK);
 		break;
 	}
-	__recalibrate_iodelay(pads, npads, iodelay, niodelays);
+	/* Setup I/O isolation */
+	ret = __recalibrate_iodelay_start();
+	if (ret)
+		goto err;
+
+	/* Do the muxing here */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
+
+	/* Now do the weird minor deltas that should be safe */
+	if (delta_npads)
+		do_set_mux32((*ctrl)->control_padconf_core_base,
+			     delta_pads, delta_npads);
+
+	/* Setup IOdelay configuration */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+err:
+	/* Closeup.. remove isolation */
+	__recalibrate_iodelay_end(ret);
 }
 #endif
 

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