mips: add base support for QCA/Atheros ath79 SOCs
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A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Use setbits_be32
- Use lookup-table instead of big switch statement for CPU detection
Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers
Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
Changes in v5:
- Add independent Kconfig
- Use SRAM for initial stack
- Move DDR initialization into board_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version into arch_global_data
Changes in v4:
- Use global_data to save CPU/DDR/AHB clock
- Use arch_global_data to save SOC's type, revison and id
Changes in v3:
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion
Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79
arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/include/asm/global_data.h | 6 + arch/mips/mach-ath79/Kconfig | 7 + arch/mips/mach-ath79/Makefile | 7 + arch/mips/mach-ath79/cpu.c | 142 +++ arch/mips/mach-ath79/dram.c | 16 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1184 +++++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/include/mach/reset.h | 14 + arch/mips/mach-ath79/reset.c | 71 ++ 12 files changed, 1610 insertions(+) create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/include/mach/reset.h create mode 100644 arch/mips/mach-ath79/reset.c
arch/mips/Kconfig +6 -0
@@ -55,6 +55,11 @@ config TARGET_PB1X00 select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_4KC +config ARCH_ATH79 + bool "Support QCA/Atheros ath79" + select OF_CONTROL + select DM + config MACH_PIC32 bool "Support Microchip PIC32" select OF_CONTROL
@@ -67,6 +72,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-pic32/Kconfig" if MIPS
arch/mips/Makefile +1 -0
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
arch/mips/include/asm/global_data.h +6 -0
@@ -23,6 +23,12 @@ struct arch_global_data {unsigned long tbl;unsigned long lastinc;#endif +#ifdef CONFIG_ARCH_ATH79 +unsigned long id; +unsigned long soc; +unsigned long rev; +unsigned long ver; +#endif };#include <asm-generic/global_data.h>
arch/mips/mach-ath79/Kconfig new file +7 -0
@@ -0,0 +1,7 @@ +menu "QCA/Atheros 7xxx/9xxx platforms" + depends on ARCH_ATH79 + +config SYS_SOC + default "ath79" + +endmenu
arch/mips/mach-ath79/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o
arch/mips/mach-ath79/cpu.c new file +142 -0
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arch/mips/mach-ath79/dram.c new file +16 -0
@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h> + +phys_size_t initdram (int board_type) +{ +ddr_tap_tuning (); +return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}
arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +1184 -0
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arch/mips/mach-ath79/include/mach/ath79.h new file +143 -0
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arch/mips/mach-ath79/include/mach/ddr.h new file +13 -0
@@ -0,0 +1,13 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_init (void ); +void ddr_tap_tuning (void ); + +#endif /* __ASM_MACH_DDR_H */
arch/mips/mach-ath79/include/mach/reset.h new file +14 -0
@@ -0,0 +1,14 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_RESET_H +#define __ASM_MACH_RESET_H + +#include <linux/types.h> + +u32 get_bootstrap (void ); + +#endif /* __ASM_MACH_RESET_H */
arch/mips/mach-ath79/reset.c new file +71 -0
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Signature · 1 line
1.9.1
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detection
Good stuff, minor nits below.
Quoted 10 lines
+++
b/arch/mips/mach-ath79/cpu.carch/mips/mach-ath79/cpu.c new file +8
-0@@ -0,0 +1,142 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h>
arch/mips/mach-ath79/cpu.c line 18
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arch/mips/mach-ath79/cpu.c new file +10
-0+#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> + +struct ath79_soc_desc { +enum ath79_soc_type soc; +const char *chip; +int major; +int minor;
All of this stuff can be const, no ?
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-0+};
[...]
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arch/mips/mach-ath79/dram.c new file +4
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+
arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +10
-0+*/ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h> + +phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();
Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]> +* Copyright (C) 2008-2010 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+
arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +10
-0+*/ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))
This should really go into some common header.
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +4
-0+#endif +#endif + +#define AR71XX_APB_BASE 0x18000000
arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 33
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +10
-0+#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000
Indent the macro value with tabs in this file please.
[...]
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 26 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
Quoted 13 lines
+++
b/arch/mips/mach-ath79/cpu.carch/mips/mach-ath79/cpu.c new file +11
-0@@ -0,0 +1,142 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h>
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arch/mips/mach-ath79/cpu.c line 18
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arch/mips/mach-ath79/cpu.c new file +7
-0+#include <mach/ar71xx_regs.h> + +struct ath79_soc_desc { +enum ath79_soc_type soc; +const char *chip; +int major; +int minor;All of this stuff can be const, no ?
OK.
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-0+};[...]
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arch/mips/mach-ath79/dram.c new file +7
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h>
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arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +7
-0+#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h> + +phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +12
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]> +* Copyright (C) 2008-2010 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_AR71XX_REGS_H
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +7
-0+#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
This header is also included by some assembly code,
but the BIT macro in linux/bitops.h isn't compatiable with assembler.
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +4
-0+#endif +#endif + +#define AR71XX_APB_BASE 0x18000000arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 33
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +10
-0+#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000Indent the macro value with tabs in this file please.
[...]
Signature · 2 lines
Best Regards Wills
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 15 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
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arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +3
-0+phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +12
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]> +* Copyright (C) 2008-2010 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_AR71XX_REGS_HQuoted 8 lines
arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +7
-0+#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
Quoted 2 lines
This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.
Because of the 1UL in it ?
[...]
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 17 lines · Marek Vasut
Quoted 14 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
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arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +3
-0+phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123
ath_ddr_tap_cal();Quoted 29 lines
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]> +* Copyright (C) 2008-2010 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +10
-0+*/ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
Quoted 3 lines
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Quoted 3 lines
[...]
Signature · 2 lines
Best Regards Wills
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 24 lines · Wills Wang
Quoted 21 lines · Marek Vasut
Quoted 14 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
Quoted 4 lines
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arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +3
-0+phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
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Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();
Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 23 lines · Marek Vasut
Quoted 22 lines · Wills Wang
Quoted 20 lines · Marek Vasut
Quoted 13 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
Quoted 4 lines
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arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +3
-0+phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
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Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
You can refer to u-boot from Atheros QSDK
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/
It's almost same as u-boot from Atheros LSDK.
The above snippet can be found in
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/tree/board/ar7240/ap123/ap123.c?h=1.1
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
Signature · 2 lines
Best Regards Wills
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 32 lines · Wills Wang
Quoted 29 lines · Marek Vasut
Quoted 28 lines · Wills Wang
Quoted 16 lines · Marek Vasut
Quoted 13 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
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Review
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(quoted diff) +3
-0+phys_size_t initdram(int board_type) +{ + ddr_tap_tuning();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();
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Quoted 2 lines
Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
You can refer to u-boot from Atheros QSDK
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/
It's almost same as u-boot from Atheros LSDK.
The above snippet can be found in
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/tree/board/ar7240/ap123/ap123.c?h=1.1
Thank you!
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-0+ return get_ram_size((void *)KSEG1, SZ_256M); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h
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arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
In reply to Wills WangQuoted 32 lines · Wills Wang
Quoted 29 lines · Marek Vasut
Quoted 28 lines · Wills Wang
Quoted 16 lines · Marek Vasut
Quoted 13 lines · Wills Wang
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Wills Wang
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
Quoted 7 lines
Quoted 6 lines
Quoted 4 lines
Review
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(quoted diff) +3
-0+phys_size_t initdram(int board_type) +{ + ddr_tap_tuning();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();
Quoted 47 lines
Quoted 2 lines
Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
You can refer to u-boot from Atheros QSDK
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/
It's almost same as u-boot from Atheros LSDK.
The above snippet can be found in
https://us.codeaurora.org/cgit/quic/qsdk/oss/boot/u-boot-1.1.4/tree/board/ar7240/ap123/ap123.c?h=1.1Quoted 38 lines
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-0+ return get_ram_size((void *)KSEG1, SZ_256M); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h
Quoted 9 lines
arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
Daniel, can we have this V8 applied, so I can start adding more stuff on top of these patches into mainline ?
Thanks!
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
In reply to Marek Vasut2016-03-17 13:20 GMT+01:00 Marek Vasut <[email protected]>:
Quoted 65 lines · Wills Wang
Quoted 24 lines · Marek Vasut
Quoted 21 lines · Wills Wang
Quoted 14 lines · Marek Vasut
Quoted 12 lines · Wills Wang
Quoted 10 lines
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
Quoted 4 lines
Quoted 4 lines
arch/mips/mach-ath79/dram.c line 14
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arch/mips/mach-ath79/dram.c new file +3
-0+phys_size_t initdram (int board_type) +{ +ddr_tap_tuning ();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
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Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
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arch/mips/mach-ath79/dram.c new file +2
-0+return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19
Quoted 9 lines
arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
actually such register definitions files are obsolete because register base adresses and sizes are taken from device-tree. The only exceptions are early startup or assembly code, but then you only need to add the definitions whose are needed by a driver. Thus I suggest you remove all the crap from this file you don't need.
Signature · 1 line
- Daniel
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
Quoted 76 lines · Daniel Schwierzeck
2016-03-17 13:20 GMT+01:00 Marek Vasut <[email protected]>:
Quoted 65 lines · Wills Wang
Quoted 24 lines · Marek Vasut
Quoted 21 lines · Wills Wang
Quoted 14 lines · Marek Vasut
Quoted 12 lines · Wills Wang
Quoted 10 lines
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionGood stuff, minor nits below.
[...]
Quoted 4 lines
Quoted 4 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+phys_size_t initdram(int board_type) +{ + ddr_tap_tuning();Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
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Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
I seem the following code in u-boot from Atheros LSDK:
#ifdef CONFIG_AP123 ath_ddr_tap_cal();Where can I get the LSDK ? I'd like to take a look and add it into my ar934x support patch.
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-0+ return get_ram_size((void *)KSEG1, SZ_256M); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */arch/mips/mach-ath79/include/mach/ar71xx_regs.h
Quoted 9 lines
arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9
-0+ +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr))This should really go into some common header.
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This header is also included by some assembly code,
but the BIT macro inlinux/bitops.hisn't compatiable with assembler.Because of the 1UL in it ?
Yes, there are also a few other C keywords and syntax, such as in-line function.
Hmmmmm, it pains me to see such duplication, but I have no better idea how to deal with it without introducing ifdefs.
Quoted 5 lines
actually such register definitions files are obsolete because register base adresses and sizes are taken from device-tree. The only exceptions are early startup or assembly code, but then you only need to add the definitions whose are needed by a driver. Thus I suggest you remove all the crap from this file you don't need.
And put the remaining bits into drivers themselves , right ?
But still, this doesn't help us with the BIT() macro redefinition problem.
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 1/9 mips: add base support for QCA/Atheros ath79 SOCs
In reply to Wills WangAm 16.03.2016 um 09:59 schrieb Wills Wang:
Quoted 5 lines
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by Wills Wang <[email protected]>---
all nine patches applied to u-boot-mips/next, thanks.
Quoted 1,763 lines
Changes in v8:
- Usesetbits_be32
- Use lookup-table instead of big switch statement for CPU detectionChanges in v7:
- Usesetbits_32
- Fix include path for SoC specific headersChanges in v6:
- Move ar933x as separate patch
- Addget_bootstrapinreset.c
- Usemap_physmeminstead of KSEG1ADDR
- Addarch_cpu_initfor detect SOC type for earlyChanges in v5:
- Add independentKconfig
- Use SRAM for initial stack
- Move DDR initialization intoboard_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version intoarch_global_dataChanges in v4:
- Useglobal_datato save CPU/DDR/AHB clock
- Usearch_global_datato save SOC's type, revison and idChanges in v3:
- Move SoC specific header files intoarch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertionChanges in v2:
- Move all SoC specific header files intoarch/mips/include/asm/arch-ath79
- Check SOC type and extract common code intoarch/mips/mach-ath79arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/include/asm/global_data.h | 6 + arch/mips/mach-ath79/Kconfig | 7 + arch/mips/mach-ath79/Makefile | 7 + arch/mips/mach-ath79/cpu.c | 142 +++ arch/mips/mach-ath79/dram.c | 16 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1184 +++++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/include/mach/reset.h | 14 + arch/mips/mach-ath79/reset.c | 71 ++ 12 files changed, 1610 insertions(+) create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/include/mach/reset.h create mode 100644 arch/mips/mach-ath79/reset.carch/mips/Kconfig +6
-0@@ -55,6 +55,11 @@ config TARGET_PB1X00 select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_4KC +config ARCH_ATH79 + bool "Support QCA/Atheros ath79" + select OF_CONTROL + select DM + config MACH_PIC32 bool "Support Microchip PIC32" select OF_CONTROL@@ -67,6 +72,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-pic32/Kconfig" if MIPSarch/mips/Makefile +1
-0@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))arch/mips/include/asm/global_data.h +6
-0@@ -23,6 +23,12 @@ struct arch_global_data {unsigned long tbl;unsigned long lastinc;#endif +#ifdef CONFIG_ARCH_ATH79 +unsigned long id; +unsigned long soc; +unsigned long rev; +unsigned long ver; +#endif };#include <asm-generic/global_data.h> arch/mips/mach-ath79/Kconfig new file +7
-0@@ -0,0 +1,7 @@ +menu "QCA/Atheros 7xxx/9xxx platforms" + depends on ARCH_ATH79 + +config SYS_SOC + default "ath79" + +endmenuarch/mips/mach-ath79/Makefile new file +7
-0@@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.oarch/mips/mach-ath79/cpu.c new file +142
-0@@ -0,0 +1,142 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> + +struct ath79_soc_desc { +enum ath79_soc_type soc; +const char *chip; +int major; +int minor; +}; + +static struct ath79_soc_desc desc[] = { + {ATH79_SOC_AR7130 ,"7130" , +REV_ID_MAJOR_AR71XX ,AR71XX_REV_ID_MINOR_AR7130 }, + {ATH79_SOC_AR7141 ,"7141" , +REV_ID_MAJOR_AR71XX ,AR71XX_REV_ID_MINOR_AR7141 }, + {ATH79_SOC_AR7161 ,"7161" , +REV_ID_MAJOR_AR71XX ,AR71XX_REV_ID_MINOR_AR7161 }, + {ATH79_SOC_AR7240 ,"7240" ,REV_ID_MAJOR_AR7240 ,0 }, + {ATH79_SOC_AR7241 ,"7241" ,REV_ID_MAJOR_AR7241 ,0 }, + {ATH79_SOC_AR7242 ,"7242" ,REV_ID_MAJOR_AR7242 ,0 }, + {ATH79_SOC_AR9130 ,"9130" , +REV_ID_MAJOR_AR913X ,AR913X_REV_ID_MINOR_AR9130 }, + {ATH79_SOC_AR9132 ,"9132" , +REV_ID_MAJOR_AR913X ,AR913X_REV_ID_MINOR_AR9132 }, + {ATH79_SOC_AR9330 ,"9330" ,REV_ID_MAJOR_AR9330 ,0 }, + {ATH79_SOC_AR9331 ,"9331" ,REV_ID_MAJOR_AR9331 ,0 }, + {ATH79_SOC_AR9341 ,"9341" ,REV_ID_MAJOR_AR9341 ,0 }, + {ATH79_SOC_AR9342 ,"9342" ,REV_ID_MAJOR_AR9342 ,0 }, + {ATH79_SOC_AR9344 ,"9344" ,REV_ID_MAJOR_AR9344 ,0 }, + {ATH79_SOC_QCA9533 ,"9533" ,REV_ID_MAJOR_QCA9533 ,0 }, + {ATH79_SOC_QCA9533 ,"9533" , +REV_ID_MAJOR_QCA9533_V2 ,0 }, + {ATH79_SOC_QCA9556 ,"9556" ,REV_ID_MAJOR_QCA9556 ,0 }, + {ATH79_SOC_QCA9558 ,"9558" ,REV_ID_MAJOR_QCA9558 ,0 }, + {ATH79_SOC_TP9343 ,"9343" ,REV_ID_MAJOR_TP9343 ,0 }, + {ATH79_SOC_QCA9561 ,"9561" ,REV_ID_MAJOR_QCA9561 ,0 }, +}; + +int arch_cpu_init (void ) +{ +void __iomem *base; +enum ath79_soc_type soc =ATH79_SOC_UNKNOWN ; +u32 id, major, minor =0 ; +u32 rev =0 , ver =1 ; +int i; + + base =map_physmem (AR71XX_RESET_BASE ,AR71XX_RESET_SIZE , +MAP_NOCACHE ); + + id =readl (base +AR71XX_RESET_REG_REV_ID ); + major = id &REV_ID_MAJOR_MASK ; +switch (major) { +case REV_ID_MAJOR_AR71XX : +case REV_ID_MAJOR_AR913X : + minor = id &AR71XX_REV_ID_MINOR_MASK ; + rev = id >>AR71XX_REV_ID_REVISION_SHIFT ; + rev &=AR71XX_REV_ID_REVISION_MASK ; +break ; + +case REV_ID_MAJOR_QCA9533_V2 : + ver =2 ; +/* drop through */ + +case REV_ID_MAJOR_AR9341 : +case REV_ID_MAJOR_AR9342 : +case REV_ID_MAJOR_AR9344 : +case REV_ID_MAJOR_QCA9533 : +case REV_ID_MAJOR_QCA9556 : +case REV_ID_MAJOR_QCA9558 : +case REV_ID_MAJOR_TP9343 : +case REV_ID_MAJOR_QCA9561 : + rev = id &AR71XX_REV_ID_REVISION2_MASK ; +break ; +default : + rev = id &AR71XX_REV_ID_REVISION_MASK ; +break ; + } + +for (i =0 ; i <ARRAY_SIZE (desc); i++) { +if ((desc[i].major == major) && + (desc[i].minor == minor)) { + soc = desc[i].soc; +break ; + } + } + + gd->arch.id = id; + gd->arch.soc = soc; + gd->arch.rev = rev; + gd->arch.ver = ver; +return 0 ; +} + +int print_cpuinfo (void ) +{ +enum ath79_soc_type soc =ATH79_SOC_UNKNOWN ; +const char *chip ="????" ; +u32 id, rev, ver; +int i; + +for (i =0 ; i <ARRAY_SIZE (desc); i++) { +if (desc[i].soc == gd->arch.soc) { + chip = desc[i].chip; + soc = desc[i].soc; +break ; + } + } + + id = gd->arch.id; + rev = gd->arch.rev; + ver = gd->arch.ver; + +switch (soc) { +case ATH79_SOC_QCA9533 : +case ATH79_SOC_QCA9556 : +case ATH79_SOC_QCA9558 : +case ATH79_SOC_QCA9561 : +printf ("Qualcomm Atheros QCA%s ver %u rev %u\n" , chip, + ver, rev); +break ; +case ATH79_SOC_TP9343 : +printf ("Qualcomm Atheros TP%s rev %u\n" , chip, rev); +break ; +case ATH79_SOC_UNKNOWN : +printf ("ATH79: unknown SoC, id:0x%08x" , id); +break ; +default : +printf ("Atheros AR%s rev %u\n" , chip, rev); + } + +return 0 ; +}arch/mips/mach-ath79/dram.c new file +16
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h> + +phys_size_t initdram (int board_type) +{ +ddr_tap_tuning (); +return get_ram_size ((void *)KSEG1 ,SZ_256M ); +}arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +1184
-0@@ -0,0 +1,1184 @@ +/* +* Atheros AR71XX/AR724X/AR913X SoC register definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]> +* Copyright (C) 2008-2010 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT (nr) (1 << (nr)) +#endif +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define QCA953X_RTC_SIZE 0x1000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +/* +* DDR_CTRL block +*/ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac +#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 +#define QCA953X_DDR_REG_BURST 0xc4 +#define QCA953X_DDR_REG_BURST2 0xc8 +#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc +#define QCA953X_DDR_REG_CTL_CONF 0x108 +#define QCA953X_DDR_REG_CONFIG3 0x15c + +/* +* PLL block +*/ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLK_CTRL_REG 0x08 +#define AR933X_PLL_DITHER_FRAC_REG 0x10 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 +#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CONFIG_PWD BIT(30) + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DIT_FRAC_EN BIT(31) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* +* USB_CONFIG block +*/ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* +* RESET block +*/ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_DDR2 BIT(13) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 + +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 +#define AR71XX_REV_ID_REVISION2_MASK 0xf + +/* +* RTC block +*/ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +#define QCA953X_RTC_REG_SYNC_RESET 0x40 +#define QCA953X_RTC_REG_SYNC_STATUS 0x44 + +/* +* SPI block +*/ +#define AR71XX_SPI_REG_FS 0x00 +#define AR71XX_SPI_REG_CTRL 0x04 +#define AR71XX_SPI_REG_IOC 0x08 +#define AR71XX_SPI_REG_RDS 0x0c + +#define AR71XX_SPI_FS_GPIO BIT(0) + +#define AR71XX_SPI_CTRL_RD BIT(6) +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) +#define AR71XX_SPI_IOC_CLK BIT(8) +#define AR71XX_SPI_IOC_CS (n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL \ + (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) + +/* +* GPIO block +*/ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO (x) BIT(x) +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA953X_GPIO (x) BIT(x) +#define QCA953X_GPIO_MUX_MASK (x) (0xff << (x)) +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 +#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* +* SRIF block +*/ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_BB_DPLL1_REG 0x180 +#define QCA953X_SRIF_BB_DPLL2_REG 0x184 +#define QCA953X_SRIF_BB_DPLL3_REG 0x188 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 +#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 +#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 + +#define QCA953X_SRIF_PMU1_REG 0xc40 +#define QCA953X_SRIF_PMU2_REG 0xc44 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f + +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) + +#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 +#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 + +#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 +#define QCA953X_SRIF_DPLL2_KD_MASK 0xf + +#define QCA953X_SRIF_DPLL2_PWD BIT(22) + +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +/* +* MII_CTRL block +*/ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* +* AR933X GMAC interface +*/ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* +* AR934X GMAC Interface +*/ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* +* QCA953X GMAC Interface +*/ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* +* QCA955X GMAC Interface +*/ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ arch/mips/mach-ath79/include/mach/ath79.h new file +143
-0@@ -0,0 +1,143 @@ +/* +* Atheros AR71XX/AR724X/AR913X common definitions +* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* Copyright (C) 2008-2011 Gabor Juhos <[email protected]> +* Copyright (C) 2008 Imre Kaloz <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +DECLARE_GLOBAL_DATA_PTR ; + +enum ath79_soc_type { +ATH79_SOC_UNKNOWN , +ATH79_SOC_AR7130 , +ATH79_SOC_AR7141 , +ATH79_SOC_AR7161 , +ATH79_SOC_AR7240 , +ATH79_SOC_AR7241 , +ATH79_SOC_AR7242 , +ATH79_SOC_AR9130 , +ATH79_SOC_AR9132 , +ATH79_SOC_AR9330 , +ATH79_SOC_AR9331 , +ATH79_SOC_AR9341 , +ATH79_SOC_AR9342 , +ATH79_SOC_AR9344 , +ATH79_SOC_QCA9533 , +ATH79_SOC_QCA9556 , +ATH79_SOC_QCA9558 , +ATH79_SOC_TP9343 , +ATH79_SOC_QCA9561 , +}; + +static inline int soc_is_ar71xx (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR7130 || + gd->arch.soc ==ATH79_SOC_AR7141 || + gd->arch.soc ==ATH79_SOC_AR7161 ; +} + +static inline int soc_is_ar724x (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR7240 || + gd->arch.soc ==ATH79_SOC_AR7241 || + gd->arch.soc ==ATH79_SOC_AR7242 ; +} + +static inline int soc_is_ar7240 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR7240 ; +} + +static inline int soc_is_ar7241 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR7241 ; +} + +static inline int soc_is_ar7242 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR7242 ; +} + +static inline int soc_is_ar913x (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR9130 || + gd->arch.soc ==ATH79_SOC_AR9132 ; +} + +static inline int soc_is_ar933x (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR9330 || + gd->arch.soc ==ATH79_SOC_AR9331 ; +} + +static inline int soc_is_ar9341 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR9341 ; +} + +static inline int soc_is_ar9342 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR9342 ; +} + +static inline int soc_is_ar9344 (void ) +{ +return gd->arch.soc ==ATH79_SOC_AR9344 ; +} + +static inline int soc_is_ar934x (void ) +{ +return soc_is_ar9341 () || +soc_is_ar9342 () || +soc_is_ar9344 (); +} + +static inline int soc_is_qca9533 (void ) +{ +return gd->arch.soc ==ATH79_SOC_QCA9533 ; +} + +static inline int soc_is_qca953x (void ) +{ +return soc_is_qca9533 (); +} + +static inline int soc_is_qca9556 (void ) +{ +return gd->arch.soc ==ATH79_SOC_QCA9556 ; +} + +static inline int soc_is_qca9558 (void ) +{ +return gd->arch.soc ==ATH79_SOC_QCA9558 ; +} + +static inline int soc_is_qca955x (void ) +{ +return soc_is_qca9556 () ||soc_is_qca9558 (); +} + +static inline int soc_is_tp9343 (void ) +{ +return gd->arch.soc ==ATH79_SOC_TP9343 ; +} + +static inline int soc_is_qca9561 (void ) +{ +return gd->arch.soc ==ATH79_SOC_QCA9561 ; +} + +static inline int soc_is_qca956x (void ) +{ +return soc_is_tp9343 () ||soc_is_qca9561 (); +} + +#endif /* __ASM_MACH_ATH79_H */ arch/mips/mach-ath79/include/mach/ddr.h new file +13
-0@@ -0,0 +1,13 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_init (void ); +void ddr_tap_tuning (void ); + +#endif /* __ASM_MACH_DDR_H */ arch/mips/mach-ath79/include/mach/reset.h new file +14
-0@@ -0,0 +1,14 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_MACH_RESET_H +#define __ASM_MACH_RESET_H + +#include <linux/types.h> + +u32 get_bootstrap (void ); + +#endif /* __ASM_MACH_RESET_H */ arch/mips/mach-ath79/reset.c new file +71
-0@@ -0,0 +1,71 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> + +void _machine_restart (void ) +{ +void __iomem *base; +u32 reg =0 ; + + base =map_physmem (AR71XX_RESET_BASE ,AR71XX_RESET_SIZE , +MAP_NOCACHE ); +if (soc_is_ar71xx ()) + reg =AR71XX_RESET_REG_RESET_MODULE ; +else if (soc_is_ar724x ()) + reg =AR724X_RESET_REG_RESET_MODULE ; +else if (soc_is_ar913x ()) + reg =AR913X_RESET_REG_RESET_MODULE ; +else if (soc_is_ar933x ()) + reg =AR933X_RESET_REG_RESET_MODULE ; +else if (soc_is_ar934x ()) + reg =AR934X_RESET_REG_RESET_MODULE ; +else if (soc_is_qca953x ()) + reg =QCA953X_RESET_REG_RESET_MODULE ; +else if (soc_is_qca955x ()) + reg =QCA955X_RESET_REG_RESET_MODULE ; +else if (soc_is_qca956x ()) + reg =QCA956X_RESET_REG_RESET_MODULE ; +else +puts ("Reset register not defined for this SOC\n" ); + +if (reg) +setbits_be32 (base + reg,AR71XX_RESET_FULL_CHIP ); + +while (1 ) +/* NOP */ ; +} + +u32 get_bootstrap (void ) +{ +const void __iomem *base; +u32 reg =0 ; + + base =map_physmem (AR71XX_RESET_BASE ,AR71XX_RESET_SIZE , +MAP_NOCACHE ); +if (soc_is_ar933x ()) + reg =AR933X_RESET_REG_BOOTSTRAP ; +else if (soc_is_ar934x ()) + reg =AR934X_RESET_REG_BOOTSTRAP ; +else if (soc_is_qca953x ()) + reg =QCA953X_RESET_REG_BOOTSTRAP ; +else if (soc_is_qca955x ()) + reg =QCA955X_RESET_REG_BOOTSTRAP ; +else if (soc_is_qca956x ()) + reg =QCA956X_RESET_REG_BOOTSTRAP ; +else +puts ("Bootstrap register not defined for this SOC\n" ); + +if (reg) +return readl (base + reg); + +return 0 ; +}
Signature · 9 lines
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PATCH v8 2/9 mips: ath79: add support for AR933x SOCs
In reply to a message not in the archiveThis patch enable work for ar933x SOC.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Fix multi-line comment for ar933x
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for ar933x
Changes in v6:
- Remove board.c
- Define magic value in ddr.c
Changes in v5:
- Add ddr.c for ar933x
Changes in v4:
- Add clk.c for ar933x
Changes in v3: None
Changes in v2: None
arch/mips/mach-ath79/Kconfig | 9 + arch/mips/mach-ath79/Makefile | 2 + arch/mips/mach-ath79/ar933x/Makefile | 7 + arch/mips/mach-ath79/ar933x/clk.c | 89 ++++++++ arch/mips/mach-ath79/ar933x/ddr.c | 333 ++++++++++++++++++++++++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 280 +++++++++++++++++++++++ 6 files changed, 720 insertions(+) create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S
arch/mips/mach-ath79/Kconfig +9 -0
@@ -4,4 +4,13 @@ menu "QCA/Atheros 7xxx/9xxx platforms" config SYS_SOC default "ath79" +config SOC_AR933X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_24KC + help + This supports QCA/Atheros ar933x family SOCs. + endmenu
arch/mips/mach-ath79/Makefile +2 -0
@@ -5,3 +5,5 @@ obj-y += reset.o obj-y += cpu.o obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/
arch/mips/mach-ath79/ar933x/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk.o +obj-y += ddr.o +obj-y += lowlevel_init.o
arch/mips/mach-ath79/ar933x/clk.c new file +89 -0
89 lines not on this page · raw message
arch/mips/mach-ath79/ar933x/ddr.c new file +333 -0
333 lines not on this page · raw message
arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +280 -0
280 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v8 2/9 mips: ath79: add support for AR933x SOCs
Quoted 23 lines · Wills Wang
This patch enable work for ar933x SOC.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Fix multi-line comment for ar933xChanges in v7:
- Use CKSEGxADDR instead of KSEGxADDR for ar933xChanges in v6:
- Removeboard.c
- Define magic value inddr.cChanges in v5:
- Addddr.cfor ar933xChanges in v4:
- Addclk.cfor ar933xChanges in v3: None
Changes in v2: None
[...]
Quoted 18 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +18
-0+#define DDR_REFRESH_EN (1 << 14) +#define DDR_REFRESH_M 0x3ff +#define DDR_REFRESH (x) ((x) & 0x3ff) +#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390)) +#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624)) + +#define DDR_TRAS_S 0 +#define DDR_TRAS_M 0x1f +#define DDR_TRAS (x) ((x) << DDR_TRAS_S) +#define DDR_TRCD_M 0xf +#define DDR_TRCD_S 5 +#define DDR_TRCD (x) ((x) << DDR_TRCD_S) +#define DDR_TRP_M 0xf +#define DDR_TRP_S 9 +#define DDR_TRP (x) ((x) << DDR_TRP_S) +#define DDR_TRRD_M 0xf +#define DDR_TRRD_S 13 +#define DDR_TRRD (x) ((x) << DDR_TRRD_S)
arch/mips/mach-ath79/ar933x/ddr.c line 51
Quoted 10 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +10
-0+#define DDR_TRFC_M 0x7f +#define DDR_TRFC_S 17 +#define DDR_TRFC (x) ((x) << DDR_TRFC_S) +#define DDR_TMRD_M 0xf +#define DDR_TMRD_S 23 +#define DDR_TMRD (x) ((x) << DDR_TMRD_S) +#define DDR_CAS_L_M 0x17 +#define DDR_CAS_L_S 27 +#define DDR_CAS_L (x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) +#define DDR_OPEN (1 << 30)
Use the BIT() macro consistently ;-)
Quoted 5 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +5
-0+#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ + DDR_TRP(6) | DDR_TRRD(4) | \ + DDR_TRFC(30) | DDR_TMRD(15) | \ + DDR_CAS_L(7) | DDR_OPEN) +
[...]
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 2/9 mips: ath79: add support for AR933x SOCs
Quoted 47 lines · Marek Vasut
Quoted 23 lines · Wills Wang
This patch enable work for ar933x SOC.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Fix multi-line comment for ar933xChanges in v7:
- Use CKSEGxADDR instead of KSEGxADDR for ar933xChanges in v6:
- Removeboard.c
- Define magic value inddr.cChanges in v5:
- Addddr.cfor ar933xChanges in v4:
- Addclk.cfor ar933xChanges in v3: None
Changes in v2: None[...]
Quoted 21 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +21
-0+#define DDR_REFRESH_EN (1 << 14) +#define DDR_REFRESH_M 0x3ff +#define DDR_REFRESH (x) ((x) & 0x3ff) +#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390)) +#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624)) + +#define DDR_TRAS_S 0 +#define DDR_TRAS_M 0x1f +#define DDR_TRAS (x) ((x) << DDR_TRAS_S) +#define DDR_TRCD_M 0xf +#define DDR_TRCD_S 5 +#define DDR_TRCD (x) ((x) << DDR_TRCD_S) +#define DDR_TRP_M 0xf +#define DDR_TRP_S 9 +#define DDR_TRP (x) ((x) << DDR_TRP_S) +#define DDR_TRRD_M 0xf +#define DDR_TRRD_S 13 +#define DDR_TRRD (x) ((x) << DDR_TRRD_S) +#define DDR_TRFC_M 0x7f +#define DDR_TRFC_S 17 +#define DDR_TRFC (x) ((x) << DDR_TRFC_S)
Quoted 9 lines
arch/mips/mach-ath79/ar933x/ddr.c line 51
Quoted 7 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +7
-0+#define DDR_TMRD_M 0xf +#define DDR_TMRD_S 23 +#define DDR_TMRD (x) ((x) << DDR_TMRD_S) +#define DDR_CAS_L_M 0x17 +#define DDR_CAS_L_S 27 +#define DDR_CAS_L (x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) +#define DDR_OPEN (1 << 30)Use the
BIT()macro consistently ;-)
OK.
Quoted 7 lines
Quoted 5 lines
arch/mips/mach-ath79/ar933x/ddr.c new file +5
-0+#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ + DDR_TRP(6) | DDR_TRRD(4) | \ + DDR_TRFC(30) | DDR_TMRD(15) | \ + DDR_CAS_L(7) | DDR_OPEN) +[...]
Signature · 2 lines
Best Regards Wills
PATCH v8 3/9 mips: ath79: add support for QCA953x SOCs
In reply to a message not in the archiveThis patch enable work for qca953x SOC.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Fix multi-line comment for qca953x
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x
Changes in v6:
- Initial support for qca953x
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/mach-ath79/Kconfig | 9 + arch/mips/mach-ath79/Makefile | 3 +- arch/mips/mach-ath79/qca953x/Makefile | 7 + arch/mips/mach-ath79/qca953x/clk.c | 111 +++++++ arch/mips/mach-ath79/qca953x/ddr.c | 472 +++++++++++++++++++++++++++ arch/mips/mach-ath79/qca953x/lowlevel_init.S | 186 +++++++++++ 6 files changed, 787 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-ath79/qca953x/Makefile create mode 100644 arch/mips/mach-ath79/qca953x/clk.c create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S
arch/mips/mach-ath79/Kconfig +9 -0
@@ -13,4 +13,13 @@ config SOC_AR933X help This supports QCA/Atheros ar933x family SOCs. +config SOC_QCA953X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_24KC + help + This supports QCA/Atheros qca953x family SOCs. + endmenu
arch/mips/mach-ath79/Makefile +2 -1
@@ -6,4 +6,5 @@ obj-y += reset.o obj-y += cpu.o obj-y += dram.o -obj-$(CONFIG_SOC_AR933X) += ar933x/ +obj-$(CONFIG_SOC_AR933X) += ar933x/ +obj-$(CONFIG_SOC_QCA953X) += qca953x/
arch/mips/mach-ath79/qca953x/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk.o +obj-y += ddr.o +obj-y += lowlevel_init.o
arch/mips/mach-ath79/qca953x/clk.c new file +111 -0
111 lines not on this page · raw message
arch/mips/mach-ath79/qca953x/ddr.c new file +472 -0
472 lines not on this page · raw message
arch/mips/mach-ath79/qca953x/lowlevel_init.S new file +186 -0
186 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v8 3/9 mips: ath79: add support for QCA953x SOCs
Quoted 5 lines · Wills Wang
This patch enable work for qca953x SOC.
Signed-off-by Wills Wang <[email protected]>---
Quoted 8 lines
Changes in v8:
- Fix multi-line comment for qca953xChanges in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953xChanges in v6:
- Initial support for qca953x
Same comment about the BIT() macro as ar933x support. Did you ever test the QCA953x ?
Best regards,
Marek Vasut
PATCH v8 3/9 mips: ath79: add support for QCA953x SOCs
Quoted 9 lines · Marek Vasut
Quoted 8 lines · Wills Wang
This patch enable work for qca953x SOC.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Fix multi-line comment for qca953x
Quoted 7 lines
Quoted 5 lines
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953xChanges in v6:
- Initial support for qca953xSame comment about the
BIT()macro as ar933x support. Did you ever test the QCA953x ?
Yes, i have a qca9531 board that is compatible with AP143.
Quoted 2 lines
Best regards,
Marek Vasut
Signature · 2 lines
Best Regards Wills
PATCH v8 3/9 mips: ath79: add support for QCA953x SOCs
Quoted 12 lines · Wills Wang
Quoted 9 lines · Marek Vasut
Quoted 8 lines · Wills Wang
This patch enable work for qca953x SOC.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8:
- Fix multi-line comment for qca953x
Quoted 8 lines
Quoted 7 lines
Quoted 5 lines
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953xChanges in v6:
- Initial support for qca953xSame comment about the
BIT()macro as ar933x support. Did you ever test the QCA953x ?Yes, i have a qca9531 board that is compatible with AP143.
Cool, thanks for confirming :-)
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 4/9 drivers: pinctrl: Add simple pinctrl driver for QCA/Athores ar933x.
In reply to a message not in the archiveThis is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 9 +++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/ath79/Makefile | 5 ++ drivers/pinctrl/ath79/pinctrl_ar933x.c | 136 +++++++++++++++++++++++++++++++++ 4 files changed, 151 insertions(+) create mode 100644 drivers/pinctrl/ath79/Makefile create mode 100644 drivers/pinctrl/ath79/pinctrl_ar933x.c
drivers/pinctrl/Kconfig +9 -0
@@ -105,6 +105,15 @@ config SPL_PINCONF if PINCTRL || SPL_PINCTRL +config AR933X_PINCTRL + bool "QCA/Athores ar933x pin control driver" + depends on DM && SOC_AR933X + help + Support pin multiplexing control on QCA/Athores ar933x SoCs. + The driver is controlled by a device tree node which contains + both the GPIO definitions and pin control functions for each + available multiplex function. + config ROCKCHIP_PINCTRL bool "Rockchip pin control driver" depends on DM
drivers/pinctrl/Makefile +1 -0
@@ -6,6 +6,7 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-y += nxp/ +obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
drivers/pinctrl/ath79/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
drivers/pinctrl/ath79/pinctrl_ar933x.c new file +136 -0
136 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v8 4/9 drivers: pinctrl: Add simple pinctrl driver for QCA/Athores ar933x.
Quoted 13 lines · Wills Wang
This is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Quoted 7 lines
drivers/pinctrl/Kconfig | 9 +++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/ath79/Makefile | 5 ++ drivers/pinctrl/ath79/pinctrl_ar933x.c | 136 +++++++++++++++++++++++++++++++++ 4 files changed, 151 insertions(+) create mode 100644 drivers/pinctrl/ath79/Makefile create mode 100644 drivers/pinctrl/ath79/pinctrl_ar933x.c
Reviewed-by Simon Glass <[email protected]>
PATCH v8 5/9 drivers: pinctrl: Add simple pinctrl driver for QCA/Athores qca953x.
In reply to a message not in the archiveThis is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 9 ++ drivers/pinctrl/ath79/Makefile | 1 + drivers/pinctrl/ath79/pinctrl_qca953x.c | 156 ++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/pinctrl/ath79/pinctrl_qca953x.c
drivers/pinctrl/Kconfig +9 -0
@@ -114,6 +114,15 @@ config AR933X_PINCTRL both the GPIO definitions and pin control functions for each available multiplex function. +config QCA953X_PINCTRL + bool "QCA/Athores qca953x pin control driver" + depends on DM && SOC_QCA953X + help + Support pin multiplexing control on QCA/Athores qca953x SoCs. + The driver is controlled by a device tree node which contains + both the GPIO definitions and pin control functions for each + available multiplex function. + config ROCKCHIP_PINCTRL bool "Rockchip pin control driver" depends on DM
drivers/pinctrl/ath79/Makefile +1 -0
@@ -3,3 +3,4 @@ # obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o +obj-$(CONFIG_QCA953x_PINCTRL) += pinctrl_qca953x.o
drivers/pinctrl/ath79/pinctrl_qca953x.c new file +156 -0
156 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v8 5/9 drivers: pinctrl: Add simple pinctrl driver for QCA/Athores qca953x.
Quoted 13 lines · Wills Wang
This is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by Wills Wang <[email protected]>---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Quoted 5 lines
drivers/pinctrl/Kconfig | 9 ++ drivers/pinctrl/ath79/Makefile | 1 + drivers/pinctrl/ath79/pinctrl_qca953x.c | 156 ++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/pinctrl/ath79/pinctrl_qca953x.c
Reviewed-by Simon Glass <[email protected]>
PATCH v8 6/9 drivers: serial: add serial driver for ar933x SOC
In reply to a message not in the archiveThis patch add support for ar933x serial.
Reviewed-by Thomas Chou <[email protected]>
Reviewed-by Daniel Schwierzeck <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Remove ath79_serial_write/read
- Use pinctrl for serial
- Add Kconfig dependence for serial option
Changes in v7:
- remove map_physmem for debug port
Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
Changes in v5:
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART
Changes in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source
Changes in v3:
- Convert serial driver to driver model
Changes in v2:
- Move serial driver code into drivers/serial
.../serial/qca,ar9330-uart.txt | 24 ++ drivers/serial/Kconfig | 18 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 255 +++++++++++++++++++++ 4 files changed, 298 insertions(+) create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 drivers/serial/serial_ar933x.c
doc/device-tree-bindings/serial/qca,ar9330-uart.txt new file +24 -0
@@ -0,0 +1,24 @@ +* Qualcomm Atheros AR9330 High-Speed UART + +Required properties: + +- compatible: Must be "qca,ar9330-uart" + +- reg: Specifies the physical base address of the controller and + the length of the memory mapped region. + +Additional requirements: + + Each UART port must have an alias correctly numbered in "aliases" + node. + +Example: + + aliases { + serial0 = &uart0; + }; + + uart0: uart at 18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + };
drivers/serial/Kconfig +18 -0
@@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_AR933X + bool "QCA/Atheros ar933x" + depends on AR933X_UART + help + Select this to enable a debug UART using the ar933x uart driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + config DEBUG_UART_NS16550 bool "ns16550" help
@@ -254,6 +263,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config AR933X_UART + bool "QCA/Atheros ar933x UART support" + depends on DM_SERIAL && SOC_AR933X + help + Select this to enable UART support for QCA/Atheros ar933x + devices. This driver uses driver model and requires a device + tree binding to operate, please refer to the document at + doc/device-tree-bindings/serial/qca,ar9330-uart.txt. + config FSL_LPUART bool "Freescale LPUART support" help
drivers/serial/Makefile +1 -0
@@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o
drivers/serial/serial_ar933x.c new file +255 -0
255 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v8 6/9 drivers: serial: add serial driver for ar933x SOC
Hi Wills,
Quoted 7 lines · Wills Wang
This patch add support for ar933x serial.
Reviewed-by Thomas Chou <[email protected]>Reviewed-by Daniel Schwierzeck <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Wills Wang <[email protected]>
Reviewed-by Simon Glass <[email protected]>
But please see a comment below.
Quoted 273 lines
---
Changes in v8:
- Remove ath79_serial_write/read
- Use pinctrl for serial
- AddKconfigdependence for serial optionChanges in v7:
- removemap_physmemfor debug portChanges in v6:
- Remove wait loop in putc and getc
- Usemap_physmeminstead of KSEG1ADDRChanges in v5:
- removear933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UARTChanges in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver intoarch/mips/mach-ath79
- Useget_serial_clockto serial clock sourceChanges in v3:
- Convert serial driver to driver modelChanges in v2:
- Move serial driver code intodrivers/serial.../serial/qca,ar9330-uart.txt | 24 ++ drivers/serial/Kconfig | 18 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 255 +++++++++++++++++++++ 4 files changed, 298 insertions(+) create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 drivers/serial/serial_ar933x.cdoc/device-tree-bindings/serial/qca,ar9330-uart.txt new file +24
-0@@ -0,0 +1,24 @@ +* Qualcomm Atheros AR9330 High-Speed UART + +Required properties: + +- compatible: Must be "qca,ar9330-uart" + +- reg: Specifies the physical base address of the controller and + the length of the memory mapped region. + +Additional requirements: + + Each UART port must have an alias correctly numbered in "aliases" + node. + +Example: + + aliases { + serial0 = &uart0; + }; + + uart0: uart at 18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + };drivers/serial/Kconfig +18
-0@@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_AR933X + bool "QCA/Atheros ar933x" + depends on AR933X_UART + help + Select this to enable a debug UART using the ar933x uart driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + config DEBUG_UART_NS16550 bool "ns16550" help@@ -254,6 +263,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config AR933X_UART + bool "QCA/Atheros ar933x UART support" + depends on DM_SERIAL && SOC_AR933X + help + Select this to enable UART support for QCA/Atheros ar933x + devices. This driver uses driver model and requires a device + tree binding to operate, please refer to the document at + doc/device-tree-bindings/serial/qca,ar9330-uart.txt. + config FSL_LPUART bool "Freescale LPUART support" helpdrivers/serial/Makefile +1
-0@@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.odrivers/serial/serial_ar933x.c new file +151
-0@@ -0,0 +1,255 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <dm/pinctrl.h> +#include <mach/ar71xx_regs.h> + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLK_REG 0x08 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8) +#define AR933X_UART_CLK_STEP_M 0xffff +#define AR933X_UART_CLK_SCALE_M 0xfff +#define AR933X_UART_CLK_SCALE_S 16 +#define AR933X_UART_CLK_STEP_S 0 + +struct ar933x_serial_priv { +void __iomem *regs; +}; + +/* +* baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) +*/ +static u32 ar933x_serial_get_baud (u32 clk,u32 scale,u32 step) +{ +u64 t; +u32 div; + + div = (2 <<16 ) * (scale +1 ); + t = clk; + t *= step; + t += (div /2 ); +do_div (t, div); + +return t; +} + +static void ar933x_serial_get_scale_step (u32 clk,u32 baud, +u32 *scale,u32 *step) +{ +u32 tscale, baudrate; +long min_diff; + + *scale =0 ; + *step =0 ; + + min_diff = baud; +for (tscale =0 ; tscale <AR933X_UART_CLK_SCALE_M ; tscale++) { +u64 tstep; +int diff; + + tstep = baud * (tscale +1 ); + tstep *= (2 <<16 ); +do_div (tstep, clk); + +if (tstep >AR933X_UART_CLK_STEP_M ) +break ; + + baudrate =ar933x_serial_get_baud (clk, tscale, tstep); + diff =abs (baudrate - baud); +if (diff < min_diff) { + min_diff = diff; + *scale = tscale; + *step = tstep; + } + } +} + +static int ar933x_serial_setbrg (struct udevice *dev,int baudrate) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 val, scale, step; + + val =get_serial_clock (); +ar933x_serial_get_scale_step (val, baudrate, &scale, &step); + + val = (scale &AR933X_UART_CLK_SCALE_M ) + <<AR933X_UART_CLK_SCALE_S ; + val |= (step &AR933X_UART_CLK_STEP_M ) + <<AR933X_UART_CLK_STEP_S ; +writel (val, priv->regs +AR933X_UART_CLK_REG ); + +return 0 ; +} + +static int ar933x_serial_putc (struct udevice *dev,const char c) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_TX_CSR )) +return -EAGAIN ; + + data = (u32 )c |AR933X_UART_DATA_TX_CSR ; +writel (data, priv->regs +AR933X_UART_DATA_REG ); + +return 0 ; +} + +static int ar933x_serial_getc (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_RX_CSR )) +return -EAGAIN ; + +writel (AR933X_UART_DATA_RX_CSR , priv->regs +AR933X_UART_DATA_REG ); +return data &AR933X_UART_DATA_TX_RX_MASK ; +} + +static int ar933x_serial_pending (struct udevice *dev,bool input) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (input) +return (data &AR933X_UART_DATA_RX_CSR ) ?1 :0 ; +else +return (data &AR933X_UART_DATA_TX_CSR ) ?0 :1 ; +} + +static int ar933x_serial_probe (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +struct udevice *pinctrl; +fdt_addr_t addr; +u32 val; +int ret;
drivers/serial/serial_ar933x.c line 161
Quoted 10 lines
drivers/serial/serial_ar933x.c new file +10
-0+ + ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pinctrl); +if (ret) +return ret; + ret =pinctrl_get_periph_id (pinctrl, dev); +if (ret <0 ) +return ret; + ret =pinctrl_request (pinctrl, ret,0 ); +if (ret <0 ) +return ret;
().Can you check if you need this? It should be called automatically by device_probe() which calls pinctrl_select_state().
drivers/serial/serial_ar933x.c line 169
Quoted 8 lines
drivers/serial/serial_ar933x.c new file +8
-0+ + addr =dev_get_addr (dev); +if (addr ==FDT_ADDR_T_NONE ) +return -EINVAL ; + + priv->regs =map_physmem (addr, +AR933X_UART_SIZE , +MAP_NOCACHE );
can you fill this out to 80cols?
Quoted 87 lines
drivers/serial/serial_ar933x.c new file +86
-1+ +/* +* UART controller configuration: +* - no DMA +* - no interrupt +* - DCE mode +* - no flow control +* - set RX ready oride +* - set TX ready oride +*/ + val = (AR933X_UART_CS_IF_MODE_DCE <<AR933X_UART_CS_IF_MODE_S ) | +AR933X_UART_CS_TX_RDY_ORIDE |AR933X_UART_CS_RX_RDY_ORIDE ; +writel (val, priv->regs +AR933X_UART_CS_REG ); +return 0 ; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible ="qca,ar9330-uart" }, + { } +}; + +U_BOOT_DRIVER (serial_ar933x) = { + .name ="serial_ar933x" , + .id =UCLASS_SERIAL , + .of_match = ar933x_serial_ids, + .priv_auto_alloc_size =sizeof (struct ar933x_serial_priv ), + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags =DM_FLAG_PRE_RELOC , +}; + +#ifdef CONFIG_DEBUG_UART_AR933X + +#include <debug_uart.h> + +static inline void _debug_uart_init (void ) +{ +void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE ; +u32 val, scale, step; + +/* +* UART controller configuration: +* - no DMA +* - no interrupt +* - DCE mode +* - no flow control +* - set RX ready oride +* - set TX ready oride +*/ + val = (AR933X_UART_CS_IF_MODE_DCE <<AR933X_UART_CS_IF_MODE_S ) | +AR933X_UART_CS_TX_RDY_ORIDE |AR933X_UART_CS_RX_RDY_ORIDE ; +writel (val, regs +AR933X_UART_CS_REG ); + +ar933x_serial_get_scale_step (CONFIG_DEBUG_UART_CLOCK , +CONFIG_BAUDRATE , &scale, &step); + + val = (scale &AR933X_UART_CLK_SCALE_M ) + <<AR933X_UART_CLK_SCALE_S ; + val |= (step &AR933X_UART_CLK_STEP_M ) + <<AR933X_UART_CLK_STEP_S ; +writel (val, regs +AR933X_UART_CLK_REG ); +} + +static inline void _debug_uart_putc (int c) +{ +void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE ; +u32 data; + +do { + data =readl (regs +AR933X_UART_DATA_REG ); + }while (!(data &AR933X_UART_DATA_TX_CSR )); + + data = (u32 )c |AR933X_UART_DATA_TX_CSR ; +writel (data, regs +AR933X_UART_DATA_REG ); +} + +DEBUG_UART_FUNCS + +#endif --
Quoted 2 lines
1.9.1
Regards,
Simon
PATCH v8 6/9 drivers: serial: add serial driver for ar933x SOC
Quoted 291 lines · Simon Glass
Hi Wills,
Quoted 7 lines · Wills Wang
This patch add support for ar933x serial.
Reviewed-by Thomas Chou <[email protected]>Reviewed-by Daniel Schwierzeck <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Wills Wang <[email protected]>Reviewed-by Simon Glass <[email protected]>But please see a comment below.
Quoted 277 lines
---
Changes in v8:
- Remove ath79_serial_write/read
- Use pinctrl for serial
- AddKconfigdependence for serial optionChanges in v7:
- removemap_physmemfor debug portChanges in v6:
- Remove wait loop in putc and getc
- Usemap_physmeminstead of KSEG1ADDRChanges in v5:
- removear933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UARTChanges in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver intoarch/mips/mach-ath79
- Useget_serial_clockto serial clock sourceChanges in v3:
- Convert serial driver to driver modelChanges in v2:
- Move serial driver code intodrivers/serial.../serial/qca,ar9330-uart.txt | 24 ++ drivers/serial/Kconfig | 18 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 255 +++++++++++++++++++++ 4 files changed, 298 insertions(+)create mode 100644
doc/device-tree-bindings/serial/qca,ar9330-uart.txtcreate mode 100644drivers/serial/serial_ar933x.cdoc/device-tree-bindings/serial/qca,ar9330-uart.txt new file +24
-0@@ -0,0 +1,24 @@ +* Qualcomm Atheros AR9330 High-Speed UART + +Required properties: + +- compatible: Must be "qca,ar9330-uart" + +- reg: Specifies the physical base address of the controller and + the length of the memory mapped region. + +Additional requirements: + + Each UART port must have an alias correctly numbered in "aliases" + node. + +Example: + + aliases { + serial0 = &uart0; + }; + + uart0: uart at 18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + };drivers/serial/Kconfig +18
-0@@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_AR933X + bool "QCA/Atheros ar933x" + depends on AR933X_UART + help + Select this to enable a debug UART using the ar933x uart driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + config DEBUG_UART_NS16550 bool "ns16550" help@@ -254,6 +263,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config AR933X_UART + bool "QCA/Atheros ar933x UART support" + depends on DM_SERIAL && SOC_AR933X + help + Select this to enable UART support for QCA/Atheros ar933x + devices. This driver uses driver model and requires a device + tree binding to operate, please refer to the document at + doc/device-tree-bindings/serial/qca,ar9330-uart.txt. + config FSL_LPUART bool "Freescale LPUART support" helpdrivers/serial/Makefile +1
-0@@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.odrivers/serial/serial_ar933x.c new file +155
-0@@ -0,0 +1,255 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <dm/pinctrl.h> +#include <mach/ar71xx_regs.h> + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLK_REG 0x08 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8) +#define AR933X_UART_CLK_STEP_M 0xffff +#define AR933X_UART_CLK_SCALE_M 0xfff +#define AR933X_UART_CLK_SCALE_S 16 +#define AR933X_UART_CLK_STEP_S 0 + +struct ar933x_serial_priv { +void __iomem *regs; +}; + +/* +* baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) +*/ +static u32 ar933x_serial_get_baud (u32 clk,u32 scale,u32 step) +{ +u64 t; +u32 div; + + div = (2 <<16 ) * (scale +1 ); + t = clk; + t *= step; + t += (div /2 ); +do_div (t, div); + +return t; +} + +static void ar933x_serial_get_scale_step (u32 clk,u32 baud, +u32 *scale,u32 *step) +{ +u32 tscale, baudrate; +long min_diff; + + *scale =0 ; + *step =0 ; + + min_diff = baud; +for (tscale =0 ; tscale <AR933X_UART_CLK_SCALE_M ; tscale++) { +u64 tstep; +int diff; + + tstep = baud * (tscale +1 ); + tstep *= (2 <<16 ); +do_div (tstep, clk); + +if (tstep >AR933X_UART_CLK_STEP_M ) +break ; + + baudrate =ar933x_serial_get_baud (clk, tscale, tstep); + diff =abs (baudrate - baud); +if (diff < min_diff) { + min_diff = diff; + *scale = tscale; + *step = tstep; + } + } +} + +static int ar933x_serial_setbrg (struct udevice *dev,int baudrate) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 val, scale, step; + + val =get_serial_clock (); +ar933x_serial_get_scale_step (val, baudrate, &scale, &step); + + val = (scale &AR933X_UART_CLK_SCALE_M ) + <<AR933X_UART_CLK_SCALE_S ; + val |= (step &AR933X_UART_CLK_STEP_M ) + <<AR933X_UART_CLK_STEP_S ; +writel (val, priv->regs +AR933X_UART_CLK_REG ); + +return 0 ; +} + +static int ar933x_serial_putc (struct udevice *dev,const char c) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_TX_CSR )) +return -EAGAIN ; + + data = (u32 )c |AR933X_UART_DATA_TX_CSR ; +writel (data, priv->regs +AR933X_UART_DATA_REG ); + +return 0 ; +} + +static int ar933x_serial_getc (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_RX_CSR )) +return -EAGAIN ; + +writel (AR933X_UART_DATA_RX_CSR , priv->regs +AR933X_UART_DATA_REG ); +return data &AR933X_UART_DATA_TX_RX_MASK ; +} + +static int ar933x_serial_pending (struct udevice *dev,bool input) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (input) +return (data &AR933X_UART_DATA_RX_CSR ) ?1 :0 ; +else +return (data &AR933X_UART_DATA_TX_CSR ) ?0 :1 ; +} + +static int ar933x_serial_probe (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +struct udevice *pinctrl; +fdt_addr_t addr; +u32 val; +int ret; + + ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pinctrl); +if (ret) +return ret;
Quoted 8 lines
drivers/serial/serial_ar933x.c line 161
Quoted 6 lines
drivers/serial/serial_ar933x.c new file +6
-0+ ret =pinctrl_get_periph_id (pinctrl, dev); +if (ret <0 ) +return ret; + ret =pinctrl_request (pinctrl, ret,0 ); +if (ret <0 ) +return ret;().Can you check if you need this? It should be called automatically by
device_probe()which callspinctrl_select_state().
Ok, i will remove all explicit pinctrl setting from driver.
Quoted 9 lines
drivers/serial/serial_ar933x.c line 169
Quoted 8 lines
drivers/serial/serial_ar933x.c new file +8
-0+ + addr =dev_get_addr (dev); +if (addr ==FDT_ADDR_T_NONE ) +return -EINVAL ; + + priv->regs =map_physmem (addr, +AR933X_UART_SIZE , +MAP_NOCACHE );can you fill this out to 80cols?
Ok.
Quoted 91 lines
Quoted 87 lines
drivers/serial/serial_ar933x.c new file +86
-1+ +/* +* UART controller configuration: +* - no DMA +* - no interrupt +* - DCE mode +* - no flow control +* - set RX ready oride +* - set TX ready oride +*/ + val = (AR933X_UART_CS_IF_MODE_DCE <<AR933X_UART_CS_IF_MODE_S ) | +AR933X_UART_CS_TX_RDY_ORIDE |AR933X_UART_CS_RX_RDY_ORIDE ; +writel (val, priv->regs +AR933X_UART_CS_REG ); +return 0 ; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible ="qca,ar9330-uart" }, + { } +}; + +U_BOOT_DRIVER (serial_ar933x) = { + .name ="serial_ar933x" , + .id =UCLASS_SERIAL , + .of_match = ar933x_serial_ids, + .priv_auto_alloc_size =sizeof (struct ar933x_serial_priv ), + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags =DM_FLAG_PRE_RELOC , +}; + +#ifdef CONFIG_DEBUG_UART_AR933X + +#include <debug_uart.h> + +static inline void _debug_uart_init (void ) +{ +void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE ; +u32 val, scale, step; + +/* +* UART controller configuration: +* - no DMA +* - no interrupt +* - DCE mode +* - no flow control +* - set RX ready oride +* - set TX ready oride +*/ + val = (AR933X_UART_CS_IF_MODE_DCE <<AR933X_UART_CS_IF_MODE_S ) | +AR933X_UART_CS_TX_RDY_ORIDE |AR933X_UART_CS_RX_RDY_ORIDE ; +writel (val, regs +AR933X_UART_CS_REG ); + +ar933x_serial_get_scale_step (CONFIG_DEBUG_UART_CLOCK , +CONFIG_BAUDRATE , &scale, &step); + + val = (scale &AR933X_UART_CLK_SCALE_M ) + <<AR933X_UART_CLK_SCALE_S ; + val |= (step &AR933X_UART_CLK_STEP_M ) + <<AR933X_UART_CLK_STEP_S ; +writel (val, regs +AR933X_UART_CLK_REG ); +} + +static inline void _debug_uart_putc (int c) +{ +void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE ; +u32 data; + +do { + data =readl (regs +AR933X_UART_DATA_REG ); + }while (!(data &AR933X_UART_DATA_TX_CSR )); + + data = (u32 )c |AR933X_UART_DATA_TX_CSR ; +writel (data, regs +AR933X_UART_DATA_REG ); +} + +DEBUG_UART_FUNCS + +#endif --Quoted 2 lines
1.9.1
Regards,
Simon
Signature · 2 lines
Best Regards Wills
PATCH v8 6/9 drivers: serial: add serial driver for ar933x SOC
Quoted 319 lines · Wills Wang
Quoted 298 lines · Simon Glass
Hi Wills,
Quoted 7 lines · Wills Wang
This patch add support for ar933x serial.
Reviewed-by Thomas Chou <[email protected]>Reviewed-by Daniel Schwierzeck <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Wills Wang <[email protected]>Reviewed-by Simon Glass <[email protected]>But please see a comment below.
Quoted 284 lines
---
Changes in v8:
- Remove ath79_serial_write/read
- Use pinctrl for serial
- AddKconfigdependence for serial optionChanges in v7:
- removemap_physmemfor debug portChanges in v6:
- Remove wait loop in putc and getc
- Usemap_physmeminstead of KSEG1ADDRChanges in v5:
- removear933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UARTChanges in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver intoarch/mips/mach-ath79
- Useget_serial_clockto serial clock sourceChanges in v3:
- Convert serial driver to driver modelChanges in v2:
- Move serial driver code intodrivers/serial.../serial/qca,ar9330-uart.txt | 24 ++ drivers/serial/Kconfig | 18 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 255 +++++++++++++++++++++ 4 files changed, 298 insertions(+)create mode 100644
doc/device-tree-bindings/serial/qca,ar9330-uart.txtcreate mode 100644drivers/serial/serial_ar933x.cdoc/device-tree-bindings/serial/qca,ar9330-uart.txt new file +24
-0@@ -0,0 +1,24 @@ +* Qualcomm Atheros AR9330 High-Speed UART + +Required properties: + +- compatible: Must be "qca,ar9330-uart" + +- reg: Specifies the physical base address of the controller and + the length of the memory mapped region. + +Additional requirements: + + Each UART port must have an alias correctly numbered in "aliases" + node. + +Example: + + aliases { + serial0 = &uart0; + }; + + uart0: uart at 18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + };drivers/serial/Kconfig +0
-0@@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART You will need to provide parameters to make this work. Thedriver will
be available until the real driver model serial is running.drivers/serial/Kconfig +5
-0+config DEBUG_UART_AR933X + bool "QCA/Atheros ar933x" + depends on AR933X_UART + help + Select this to enable a debug UART using the ar933x uartdriver.
drivers/serial/Kconfig +4
-0+ You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + config DEBUG_UART_NS16550 bool "ns16550" help@@ -254,6 +263,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" ofAltera.
drivers/serial/Kconfig +9
-0+config AR933X_UART + bool "QCA/Atheros ar933x UART support" + depends on DM_SERIAL && SOC_AR933X + help + Select this to enable UART support for QCA/Atheros ar933x + devices. This driver uses driver model and requires a device + tree binding to operate, please refer to the document at + doc/device-tree-bindings/serial/qca,ar9330-uart.txt. + config FSL_LPUART bool "Freescale LPUART support" helpdrivers/serial/Makefile +1
-0@@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.odrivers/serial/serial_ar933x.c new file +129
-0@@ -0,0 +1,255 @@ +/* +* Copyright (C) 2015-2016 Wills Wang <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <dm/pinctrl.h> +#include <mach/ar71xx_regs.h> + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLK_REG 0x08 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8) +#define AR933X_UART_CLK_STEP_M 0xffff +#define AR933X_UART_CLK_SCALE_M 0xfff +#define AR933X_UART_CLK_SCALE_S 16 +#define AR933X_UART_CLK_STEP_S 0 + +struct ar933x_serial_priv { +void __iomem *regs; +}; + +/* +* baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) +*/ +static u32 ar933x_serial_get_baud (u32 clk,u32 scale,u32 step) +{ +u64 t; +u32 div; + + div = (2 <<16 ) * (scale +1 ); + t = clk; + t *= step; + t += (div /2 ); +do_div (t, div); + +return t; +} + +static void ar933x_serial_get_scale_step (u32 clk,u32 baud, +u32 *scale,u32 *step) +{ +u32 tscale, baudrate; +long min_diff; + + *scale =0 ; + *step =0 ; + + min_diff = baud; +for (tscale =0 ; tscale <AR933X_UART_CLK_SCALE_M ; tscale++) { +u64 tstep; +int diff; + + tstep = baud * (tscale +1 ); + tstep *= (2 <<16 ); +do_div (tstep, clk); + +if (tstep >AR933X_UART_CLK_STEP_M ) +break ; + + baudrate =ar933x_serial_get_baud (clk, tscale, tstep); + diff =abs (baudrate - baud); +if (diff < min_diff) { + min_diff = diff; + *scale = tscale; + *step = tstep; + } + } +} + +static int ar933x_serial_setbrg (struct udevice *dev,int baudrate) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 val, scale, step; + + val =get_serial_clock (); +ar933x_serial_get_scale_step (val, baudrate, &scale, &step); + + val = (scale &AR933X_UART_CLK_SCALE_M ) + <<AR933X_UART_CLK_SCALE_S ; + val |= (step &AR933X_UART_CLK_STEP_M ) + <<AR933X_UART_CLK_STEP_S ; +writel (val, priv->regs +AR933X_UART_CLK_REG ); + +return 0 ; +} + +static int ar933x_serial_putc (struct udevice *dev,const char c) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_TX_CSR )) +return -EAGAIN ; + + data = (u32 )c |AR933X_UART_DATA_TX_CSR ; +writel (data, priv->regs +AR933X_UART_DATA_REG ); + +return 0 ; +} + +static int ar933x_serial_getc (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (!(data &AR933X_UART_DATA_RX_CSR )) +return -EAGAIN ; + + writel(AR933X_UART_DATA_RX_CSR, priv->regs +
AR933X_UART_DATA_REG);drivers/serial/serial_ar933x.c new file +26
-0+return data &AR933X_UART_DATA_TX_RX_MASK ; +} + +static int ar933x_serial_pending (struct udevice *dev,bool input) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +u32 data; + + data =readl (priv->regs +AR933X_UART_DATA_REG ); +if (input) +return (data &AR933X_UART_DATA_RX_CSR ) ?1 :0 ; +else +return (data &AR933X_UART_DATA_TX_CSR ) ?0 :1 ; +} + +static int ar933x_serial_probe (struct udevice *dev) +{ +struct ar933x_serial_priv *priv =dev_get_priv (dev); +struct udevice *pinctrl; +fdt_addr_t addr; +u32 val; +int ret; + + ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pinctrl); +if (ret) +return ret;Quoted 8 lines
drivers/serial/serial_ar933x.c line 161
Quoted 6 lines
drivers/serial/serial_ar933x.c new file +6
-0+ ret =pinctrl_get_periph_id (pinctrl, dev); +if (ret <0 ) +return ret; + ret =pinctrl_request (pinctrl, ret,0 ); +if (ret <0 ) +return ret;().Can you check if you need this? It should be called automatically by
device_probe()which callspinctrl_select_state().Ok, i will remove all explicit pinctrl setting from driver.
Quoted 9 lines
drivers/serial/serial_ar933x.c line 169
Quoted 8 lines
drivers/serial/serial_ar933x.c new file +8
-0+ + addr =dev_get_addr (dev); +if (addr ==FDT_ADDR_T_NONE ) +return -EINVAL ; + + priv->regs =map_physmem (addr, +AR933X_UART_SIZE , +MAP_NOCACHE );can you fill this out to 80cols?
Quoted 1 line
Ok.
Please send subsequent patches on top of mips/next :)
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/next
Signature · 2 lines
Best regards, Marek Vasut
PATCH v8 7/9 drivers: spi: add spi support for QCA/Atheros ath79 SOCs
In reply to a message not in the archiveThis patch add a compatible spi driver for ath79 series SOC.
Reviewed-by Thomas Chou <[email protected]>
Reviewed-by Daniel Schwierzeck <[email protected]>
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Remove ath79_spi_write/read
- Use pinctrl for spi
- Add Kconfig dependence for spi option
- Use dev_get_parent
Changes in v7:
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32
Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed
Changes in v5:
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation
Changes in v4:
- Use get_bus_freq instead of hardcode in SPI driver
Changes in v3:
- Convert spi driver to driver model
Changes in v2:
- Add a compatible spi driver
doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 240 +++++++++++++++++++++++++++++ 4 files changed, 269 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c
doc/device-tree-bindings/spi/spi-ath79.txt new file +19 -0
@@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi at 1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + };
drivers/spi/Kconfig +9 -0
@@ -23,6 +23,15 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + depends on ARCH_ATH79 + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help
drivers/spi/Makefile +1 -0
@@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
drivers/spi/ath79_spi.c new file +240 -0
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Signature · 1 line
1.9.1
PATCH v8 8/9 mips: ath79: add AP121 reference board
In reply to a message not in the archiveThis patch add board-level code and base DT for AP121.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Move board/ath79/ap121 into board/qca/ap121
- Move SYS_VENDOR into board-level for ap121
Changes in v7:
- Use KSEG1 address for debug port in ap121
Changes in v6:
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig
Changes in v5:
- Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
- Remove useless README file
- Remove useless checkboard function
Changes in v4: None
Changes in v3:
- Add support for device tree
Changes in v2:
- Add a reference board implemention
arch/mips/dts/Makefile | 1 + arch/mips/dts/ap121.dts | 43 ++++++++++++++++++++++ arch/mips/dts/ar933x.dtsi | 82 +++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 11 ++++++ board/qca/ap121/Kconfig | 12 ++++++ board/qca/ap121/MAINTAINERS | 6 +++ board/qca/ap121/Makefile | 5 +++ board/qca/ap121/ap121.c | 50 +++++++++++++++++++++++++ configs/ap121_defconfig | 46 +++++++++++++++++++++++ include/configs/ap121.h | 87 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 343 insertions(+) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 board/qca/ap121/Kconfig create mode 100644 board/qca/ap121/MAINTAINERS create mode 100644 board/qca/ap121/Makefile create mode 100644 board/qca/ap121/ap121.c create mode 100644 configs/ap121_defconfig create mode 100644 include/configs/ap121.h
arch/mips/dts/Makefile +1 -0
@@ -2,6 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y)
arch/mips/dts/ap121.dts new file +43 -0
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arch/mips/dts/ar933x.dtsi new file +82 -0
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arch/mips/mach-ath79/Kconfig +11 -0
@@ -22,4 +22,15 @@ config SOC_QCA953X help This supports QCA/Atheros qca953x family SOCs. +choice + prompt "Board select" + +config TARGET_AP121 + bool "AP121 Reference Board" + select SOC_AR933X + +endchoice + +source "board/qca/ap121/Kconfig" + endmenu
board/qca/ap121/Kconfig new file +12 -0
@@ -0,0 +1,12 @@ +if TARGET_AP121 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap121" + +config SYS_CONFIG_NAME + default "ap121" + +endif
board/qca/ap121/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang <[email protected]> +S: Maintained +F: board/qca/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig
board/qca/ap121/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o
board/qca/ap121/ap121.c new file +50 -0
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configs/ap121_defconfig new file +46 -0
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include/configs/ap121.h new file +87 -0
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Signature · 1 line
1.9.1
PATCH v8 9/9 mips: ath79: add AP143 reference board
In reply to a message not in the archiveThis patch add board-level code and base DT for AP143.
Signed-off-by Wills Wang <[email protected]>
---
Changes in v8:
- Move board/ath79/ap143 into board/qca/ap143
- Move SYS_VENDOR into board-level for ap143
Changes in v7:
- Use KSEG1 address for debug port in ap143
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/dts/Makefile | 1 + arch/mips/dts/ap143.dts | 43 +++++++++++++++++++++ arch/mips/dts/qca953x.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/qca/ap143/Kconfig | 12 ++++++ board/qca/ap143/MAINTAINERS | 6 +++ board/qca/ap143/Makefile | 5 +++ board/qca/ap143/ap143.c | 66 ++++++++++++++++++++++++++++++++ configs/ap143_defconfig | 45 ++++++++++++++++++++++ include/configs/ap143.h | 91 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 358 insertions(+) create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 board/qca/ap143/Kconfig create mode 100644 board/qca/ap143/MAINTAINERS create mode 100644 board/qca/ap143/Makefile create mode 100644 board/qca/ap143/ap143.c create mode 100644 configs/ap143_defconfig create mode 100644 include/configs/ap143.h
arch/mips/dts/Makefile +1 -0
@@ -3,6 +3,7 @@ # dtb-$(CONFIG_TARGET_AP121) += ap121.dtb +dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y)
arch/mips/dts/ap143.dts new file +43 -0
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arch/mips/dts/qca953x.dtsi new file +84 -0
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arch/mips/mach-ath79/Kconfig +5 -0
@@ -29,8 +29,13 @@ config TARGET_AP121 bool "AP121 Reference Board" select SOC_AR933X +config TARGET_AP143 + bool "AP143 Reference Board" + select SOC_QCA953X + endchoice source "board/qca/ap121/Kconfig" +source "board/qca/ap143/Kconfig" endmenu
board/qca/ap143/Kconfig new file +12 -0
@@ -0,0 +1,12 @@ +if TARGET_AP143 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap143" + +config SYS_CONFIG_NAME + default "ap143" + +endif
board/qca/ap143/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +AP143 BOARD +M: Wills Wang <[email protected]> +S: Maintained +F: board/qca/ap143/ +F: include/configs/ap143.h +F: configs/ap143_defconfig
board/qca/ap143/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap143.o
board/qca/ap143/ap143.c new file +66 -0
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configs/ap143_defconfig new file +45 -0
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include/configs/ap143.h new file +91 -0
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Signature · 1 line
1.9.1