Add ACPI table support on Minnowmax
cover Add ACPI table support on Minnowmax
This series adds ACPI table support on Minnowmax.
Saket Sinha (2):
x86: Add ACPI table support to Minnowmax
x86: Add DSDT table for supporting ACPI on Minnowmax
board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++ board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 10 files changed, 884 insertions(+) create mode 100644 board/intel/minnowmax/acpi.c create mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl
Signature · 1 line
2.1.4
PATCH 1/2 x86: Add ACPI table support to Minnowmax
This patch mainly adds ACPI support to Minnowmax.
---
board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 235 insertions(+) create mode 100644 board/intel/minnowmax/acpi.c
board/intel/minnowmax/Makefile +1 -0
@@ -5,3 +5,4 @@ # obj-y += minnowmax.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
board/intel/minnowmax/acpi.c new file +234 -0
234 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH 1/2 x86: Add ACPI table support to Minnowmax
Hi Saket,
Quoted 27 lines · Saket Sinha
This patch mainly adds ACPI support to Minnowmax.
Signed-off-by Saket Sinha <[email protected]>---
board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 235 insertions(+) create mode 100644 board/intel/minnowmax/acpi.cboard/intel/minnowmax/Makefile +1
-0@@ -5,3 +5,4 @@ # obj-y += minnowmax.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.oboard/intel/minnowmax/acpi.c new file +2
-0@@ -0,0 +1,234 @@ +/* +* Copyright (C) 2015, Saket Sinha <[email protected]>
board/intel/minnowmax/acpi.c line 12
Quoted 10 lines
board/intel/minnowmax/acpi.c new file +10
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/acpi_table.h> +#include <asm/ioapic.h> +#include <asm/tables.h> + +#define ILB_BASE_ADDRESS 0xfed08000
Please don't hardcode this. Instead, read its value from the configuration space.
board/intel/minnowmax/acpi.c line 14
Quoted 2 lines
board/intel/minnowmax/acpi.c new file +2
-0+/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00
See arch/x86/include/asm/arch-baytrail/baytrail.h, we have struct byt_ibase already.
board/intel/minnowmax/acpi.c line 22
Quoted 8 lines
board/intel/minnowmax/acpi.c new file +8
-0+#define SCIS_MASK 0x07 +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07
Please move these to arch/x86/include/asm/arch-baytrail/baytrail.h
board/intel/minnowmax/acpi.c line 28
Quoted 6 lines
board/intel/minnowmax/acpi.c new file +6
-0+ +static inline uint32_t read_address (const void *addr) +{ +return *(volatile uint32_t *)addr; +} +
It looks like debug codes. Please remove.
board/intel/minnowmax/acpi.c line 31
Quoted 3 lines
board/intel/minnowmax/acpi.c new file +3
-0+int acpi_sci_irq (void ) +{ +u32 *actl = (u32 *)(ILB_BASE_ADDRESS +ACTL );
Please convert to use C struct to access ACTL.
Quoted 50 lines
board/intel/minnowmax/acpi.c new file +50
-0+int scis; +static int sci_irq; + +if (sci_irq) +return sci_irq; + +/* Determine how SCI is routed. */ + scis =read_address (actl) &SCIS_MASK ; +switch (scis) { +case SCIS_IRQ9 : +case SCIS_IRQ10 : +case SCIS_IRQ11 : + sci_irq = scis -SCIS_IRQ9 +9 ; +break ; +case SCIS_IRQ20 : +case SCIS_IRQ21 : +case SCIS_IRQ22 : +case SCIS_IRQ23 : + sci_irq = scis -SCIS_IRQ20 +20 ; +break ; +default : +debug ("Invalid SCI route! Defaulting to IRQ9.\n" ); + sci_irq =9 ; +break ; + } + +debug ("SCI is IRQ%d\n" , sci_irq); +return sci_irq; +} + +unsigned long acpi_madt_irq_overrides (unsigned long current) +{ +int sci_irq =acpi_sci_irq (); +struct acpi_madt_irqoverride *irqovr; +uint16_t sci_flags =MP_IRQ_TRIGGER_LEVEL ; + +/* INT_SRC_OVR */ + irqovr = (void *)current; + current +=acpi_create_madt_irqoverride (irqovr,0 ,0 ,2 ,0 ); + +if (sci_irq >=20 ) + sci_flags |=MP_IRQ_POLARITY_LOW ; +else + sci_flags |=MP_IRQ_POLARITY_HIGH ; + + irqovr = (void *)current; + current +=acpi_create_madt_irqoverride (irqovr,0 , sci_irq, sci_irq, + sci_flags); + +return current;
board/intel/minnowmax/acpi.c line 91
Quoted 10 lines
board/intel/minnowmax/acpi.c new file +10
-0+} + +void acpi_create_fadt (struct acpi_fadt *fadt,struct acpi_facs *facs, +void *dsdt) +{ +acpi_header_t *header = &(fadt->header); +u16 pm, pmbase; + +pci_dev_t bdf =PCI_BDF (0 ,0x1f ,0 ); +pci_read_config_word (bdf,0x40 , &pm);
Please define something meaningful for 0x40.
Quoted 134 lines
board/intel/minnowmax/acpi.c new file +134
-0+ pmbase = pm &0xfffe ; +memset ((void *)fadt,0 ,sizeof (struct acpi_fadt )); +memcpy (header->signature,"FACP" ,4 ); + header->length =sizeof (struct acpi_fadt ); + header->revision =3 ; +memcpy (header->oem_id,OEM_ID ,6 ); +memcpy (header->oem_table_id,ACPI_TABLE_CREATOR ,8 ); +memcpy (header->asl_compiler_id,ASLC ,4 ); + header->asl_compiler_revision =0 ; + + fadt->firmware_ctrl = (unsigned long ) facs; + fadt->dsdt = (unsigned long ) dsdt; + fadt->model =0x00 ; + fadt->preferred_pm_profile =PM_MOBILE ; + fadt->sci_int =0x9 ; + fadt->smi_cmd =0 ; + fadt->acpi_enable =0 ; + fadt->acpi_disable =0 ; + fadt->s4bios_req =0x0 ; + fadt->pstate_cnt =0 ; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk =0x0 ; + fadt->pm1a_cnt_blk = pmbase +0x4 ; + fadt->pm1b_cnt_blk =0x0 ; + fadt->pm2_cnt_blk = pmbase +0x50 ; + fadt->pm_tmr_blk = pmbase +0x8 ; + fadt->gpe0_blk = pmbase +0x20 ; + fadt->gpe1_blk =0 ; + fadt->pm1_evt_len =4 ; + fadt->pm1_cnt_len =2 ; + fadt->pm2_cnt_len =1 ; + fadt->pm_tmr_len =4 ; + fadt->gpe0_blk_len =16 ; + fadt->gpe1_blk_len =0 ; + fadt->gpe1_base =0 ; + fadt->cst_cnt =0 ; + fadt->p_lvl3_lat =87 ; + fadt->flush_size =1024 ; + fadt->flush_stride =16 ; + fadt->duty_offset =1 ; + fadt->day_alrm =0xd ; + fadt->mon_alrm =0x00 ; + fadt->century =0x00 ; + fadt->iapc_boot_arch =ACPI_FADT_LEGACY_DEVICES |ACPI_FADT_8042 ; + + fadt->flags =ACPI_FADT_WBINVD | +ACPI_FADT_C1_SUPPORTED | +ACPI_FADT_SLEEP_BUTTON | +ACPI_FADT_RESET_REGISTER | +ACPI_FADT_SEALED_CASE | +ACPI_FADT_S4_RTC_WAKE | +ACPI_FADT_PLATFORM_CLOCK ; + fadt->reset_reg.space_id =1 ; + fadt->reset_reg.bit_width =8 ; + fadt->reset_reg.bit_offset =0 ; + fadt->reset_reg.access_size =ACPI_ACCESS_SIZE_BYTE_ACCESS ; + fadt->reset_reg.addrl =0xcf9 ; + fadt->reset_reg.addrh =0 ; + fadt->reset_value =6 ; + fadt->x_firmware_ctl_l = (unsigned long )facs; + fadt->x_firmware_ctl_h =0 ; + fadt->x_dsdt_l = (unsigned long )dsdt; + fadt->x_dsdt_h =0 ; + + fadt->x_pm1a_evt_blk.space_id =1 ; + fadt->x_pm1a_evt_blk.bit_width =32 ; + fadt->x_pm1a_evt_blk.bit_offset =0 ; + fadt->x_pm1a_evt_blk.access_size =ACPI_ACCESS_SIZE_DWORD_ACCESS ; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh =0x0 ; + + fadt->x_pm1b_evt_blk.space_id =1 ; + fadt->x_pm1b_evt_blk.bit_width =0 ; + fadt->x_pm1b_evt_blk.bit_offset =0 ; + fadt->x_pm1b_evt_blk.access_size =0 ; + fadt->x_pm1b_evt_blk.addrl =0x0 ; + fadt->x_pm1b_evt_blk.addrh =0x0 ; + + fadt->x_pm1a_cnt_blk.space_id =1 ; + fadt->x_pm1a_cnt_blk.bit_width =16 ; + fadt->x_pm1a_cnt_blk.bit_offset =0 ; + fadt->x_pm1a_cnt_blk.access_size =ACPI_ACCESS_SIZE_WORD_ACCESS ; + fadt->x_pm1a_cnt_blk.addrl = pmbase +0x4 ; + fadt->x_pm1a_cnt_blk.addrh =0x0 ; + + fadt->x_pm1b_cnt_blk.space_id =1 ; + fadt->x_pm1b_cnt_blk.bit_width =0 ; + fadt->x_pm1b_cnt_blk.bit_offset =0 ; + fadt->x_pm1b_cnt_blk.access_size =0 ; + fadt->x_pm1b_cnt_blk.addrl =0x0 ; + fadt->x_pm1b_cnt_blk.addrh =0x0 ; + + fadt->x_pm2_cnt_blk.space_id =1 ; + fadt->x_pm2_cnt_blk.bit_width =8 ; + fadt->x_pm2_cnt_blk.bit_offset =0 ; + fadt->x_pm2_cnt_blk.access_size =ACPI_ACCESS_SIZE_BYTE_ACCESS ; + fadt->x_pm2_cnt_blk.addrl = pmbase +0x50 ; + fadt->x_pm2_cnt_blk.addrh =0x0 ; + + fadt->x_pm_tmr_blk.space_id =1 ; + fadt->x_pm_tmr_blk.bit_width =32 ; + fadt->x_pm_tmr_blk.bit_offset =0 ; + fadt->x_pm_tmr_blk.access_size =ACPI_ACCESS_SIZE_DWORD_ACCESS ; + fadt->x_pm_tmr_blk.addrl = pmbase +0x8 ; + fadt->x_pm_tmr_blk.addrh =0x0 ; + + fadt->x_gpe0_blk.space_id =1 ; + fadt->x_gpe0_blk.bit_width =128 ; + fadt->x_gpe0_blk.bit_offset =0 ; + fadt->x_gpe0_blk.access_size =ACPI_ACCESS_SIZE_DWORD_ACCESS ; + fadt->x_gpe0_blk.addrl = pmbase +0x20 ; + fadt->x_gpe0_blk.addrh =0x0 ; + + fadt->x_gpe1_blk.space_id =1 ; + fadt->x_gpe1_blk.bit_width =0 ; + fadt->x_gpe1_blk.bit_offset =0 ; + fadt->x_gpe1_blk.access_size =0 ; + fadt->x_gpe1_blk.addrl =0x0 ; + fadt->x_gpe1_blk.addrh =0x0 ; + + header->checksum = +table_compute_checksum ((void *)fadt, header->length); +} + +unsigned long acpi_fill_madt (unsigned long current) +{ +/* create all subtables for processors */ + current =acpi_create_madt_lapics (current); + +/* IOAPIC */ + current +=acpi_create_madt_ioapic ((struct acpi_madt_ioapic *)current, +2 ,IO_APIC_ADDR ,0 ); + + current =acpi_madt_irq_overrides (current);
board/intel/minnowmax/acpi.c
Quoted 10 lines
board/intel/minnowmax/acpi.c new file +9
-1+ +return current; +} + +unsigned long acpi_fill_mcfg (unsigned long current) +{ +return current; +} + --
Regards,
Bin
PATCH 2/2 x86: Add DSDT table for supporting ACPI on Minnowmax
In reply to Saket SinhaThe DSDT table contains a bytecode that is executed by a driver in the kernel.
---
board/intel/minnowmax/Makefile | 2 +- board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 9 files changed, 650 insertions(+), 1 deletion(-) create mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl
board/intel/minnowmax/Makefile +1 -1
@@ -5,4 +5,4 @@ # obj-y += minnowmax.o start.o -obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
board/intel/minnowmax/acpi/cpu.asl new file +65 -0
65 lines not on this page · raw message
board/intel/minnowmax/acpi/device_nvs.asl new file +75 -0
75 lines not on this page · raw message
board/intel/minnowmax/acpi/globalnvs.asl new file +88 -0
88 lines not on this page · raw message
board/intel/minnowmax/acpi/mainboard.asl new file +13 -0
@@ -0,0 +1,13 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +}
board/intel/minnowmax/acpi/platform.asl new file +62 -0
62 lines not on this page · raw message
board/intel/minnowmax/acpi/sleepstates.asl new file +14 -0
@@ -0,0 +1,14 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0})
board/intel/minnowmax/acpi/southcluster.asl new file +286 -0
286 lines not on this page · raw message
board/intel/minnowmax/dsdt.asl new file +46 -0
46 lines not on this page · raw message
Signature · 1 line
2.1.4
PATCH 2/2 x86: Add DSDT table for supporting ACPI on Minnowmax
Hi Saket,
Quoted 5 lines · Saket Sinha
The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by Saket Sinha <[email protected]>---
What tests have you run with ACPI on MinnowMax? And any errors did you see?
[snip]
Regards,
Bin
PATCH 2/2 x86: Add DSDT table for supporting ACPI on Minnowmax
Hi Bin,
Quoted 11 lines · Bin Meng
Hi Saket,
Quoted 5 lines · Saket Sinha
The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by Saket Sinha <[email protected]>---
And any errors did you see?
I am getting PCI configuration errors on Minnowmax similar to those we have on QEMU. I am trying to solve them.
Quoted 2 lines
What tests have you run with ACPI on MinnowMax?
I am fixing the errors first before going into testing. The first step is to let Linux parse the ACPI table without any errors. Then we can go into the testing aspect for different power stages.
Regards,
Saket Sinha
cover Add ACPI table support on Minnowmax
In reply to Saket SinhaHi Saket,
Quoted 17 lines · Saket Sinha
This series adds ACPI table support on Minnowmax.
Saket Sinha (2):
x86: Add ACPI table support to Minnowmax
x86: Add DSDT table for supporting ACPI on Minnowmaxboard/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++ board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 10 files changed, 884 insertions(+)
Quoted 9 lines
create mode 100644
board/intel/minnowmax/acpi.ccreate mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl
I'm interested in ACPI support for BayTrail (e.g. MinnowMAX). And noticed that you didn't follow up on this MinnowMAX ACPI support thread. In another patchset by Miao (added to Cc), ACPI support has now been added for QEMU already:
https://www.mail-archive.com/u-boot at lists.denx.de/msg200312.html
So what is the current status of ACPI for x86 in U-Boot? Is someone currently working on BayTrail / MinnowMAX ACPI support? If yes, please let me know so that we can combine our efforts. If not, please give me some hints on how to best start / continue here. Why did this patchset from Saket not make it into mainline? What are the main flaws / problems?
Any hints or suggestions welcome! :)
Thanks,
Stefan
cover Add ACPI table support on Minnowmax
Hi Stefan,
Quoted 35 lines · Stefan Roese
Hi Saket,
Quoted 20 lines · Saket Sinha
This series adds ACPI table support on Minnowmax.
Saket Sinha (2):
x86: Add ACPI table support to Minnowmax
x86: Add DSDT table for supporting ACPI on Minnowmaxboard/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++ board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 10 files changed, 884 insertions(+)Quoted 9 lines
create mode 100644
board/intel/minnowmax/acpi.ccreate mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl
Quoted 8 lines
I'm interested in ACPI support for BayTrail (e.g. MinnowMAX). And noticed that you didn't follow up on this MinnowMAX ACPI support thread. In another patchset by Miao (added to Cc), ACPI support has now been added for QEMU already:
https://www.mail-archive.com/u-boot at lists.denx.de/msg200312.html
So what is the current status of ACPI for x86 in U-Boot? Is someone
So far the only working ACPI support for x86 in U-Boot is QEMU, with fw_cfg.
Quoted 5 lines
currently working on BayTrail / MinnowMAX ACPI support? If yes, please let me know so that we can combine our efforts. If not, please give me some hints on how to best start / continue here. Why did this patchset from Saket not make it into mainline? What are the main flaws / problems?
Saket's patch does not get ACPI fully working on MinnowMAX. And I guess he has stopped working on this, Simon?
Quoted 3 lines
Any hints or suggestions welcome! :)
To support ACPI on real boards, the main task is to write ASL files to describe the on-board devices, using AML language. We can take most of these from coreboot though. The other part is to program these ACPI registers as required by the spec.
Regards,
Bin