Update gdsys board support

index d35aee0..54e7f63 100644
@@ -12,6 +12,16 @@
 #include <errno.h>
 #include <i2c.h>
 
+#define DP501_I2C_ADDR 0x08
+
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
+
 static void dp501_setbits(u8 addr, u8 reg, u8 mask)
 {
 	u8 val;

@@ -125,3 +135,24 @@ void dp501_powerdown(u8 addr)
 {
 	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
 }
+
+
+int dp501_probe(unsigned screen, bool power)
+{
+#ifdef CONFIG_SYS_DP501_BASE
+	uint8_t dp501_addr = dp501_base[screen];
+#else
+	uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+	i2c_set_bus_num(dp501_i2c[screen]);
+#endif
+
+	if (i2c_probe(dp501_addr))
+		return -1;
+
+	dp501_powerup(dp501_addr);
+
+	return 0;
+}

index 8dc3215..b98b54e 100644
@@ -26,5 +26,6 @@
 
 void dp501_powerup(u8 addr);
 void dp501_powerdown(u8 addr);
+int dp501_probe(unsigned screen, bool power);
 
 #endif

index 7444bee..4e292f5 100644
@@ -24,8 +24,6 @@
 #define SIL1178_MASTER_I2C_ADDRESS 0x38
 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
 
-#define DP501_I2C_ADDR 0x08
-
 #define PIXCLK_640_480_60 25180000
 #define MAX_X_CHARS 53
 #define MAX_Y_CHARS 26

@@ -78,14 +76,6 @@ int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
 int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
 #endif
 
-#ifdef CONFIG_SYS_DP501_I2C
-int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
-#endif
-
-#ifdef CONFIG_SYS_DP501_BASE
-int dp501_base[] = CONFIG_SYS_DP501_BASE;
-#endif
-
 #ifdef CONFIG_SYS_MPC92469AC
 static void mpc92469ac_calc_parameters(unsigned int fout,
 	unsigned int *post_div, unsigned int *feedback_div)

@@ -317,13 +307,6 @@ int osd_probe(unsigned screen)
 	int old_bus = i2c_get_bus_num();
 	bool pixclock_present = false;
 	bool output_driver_present = false;
-#ifdef CONFIG_SYS_DP501_I2C
-#ifdef CONFIG_SYS_DP501_BASE
-	uint8_t dp501_addr = dp501_base[screen];
-#else
-	uint8_t dp501_addr = DP501_I2C_ADDR;
-#endif
-#endif
 
 	OSD_GET_REG(0, version, &version);
 	OSD_GET_REG(0, features, &features);

@@ -393,11 +376,8 @@ int osd_probe(unsigned screen)
 #endif
 
 #ifdef CONFIG_SYS_DP501_I2C
-	i2c_set_bus_num(dp501_i2c[screen]);
-	if (!i2c_probe(dp501_addr)) {
-		dp501_powerup(dp501_addr);
+	if (!dp501_probe(screen, true))
 		output_driver_present = true;
-	}
 #endif
 
 	if (!output_driver_present)

index ef5b6c0..eee582b 100644
@@ -24,6 +24,7 @@
 
 #include "../common/adv7611.h"
 #include "../common/ch7301.h"
+#include "../common/dp501.h"
 #include "../common/ioep-fpga.h"
 #include "../common/mclink.h"
 #include "../common/osd.h"

@@ -127,7 +128,10 @@ int last_stage_init(void)
 	int slaves;
 	unsigned int k;
 	unsigned int mux_ch;
-	unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+	unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
+#ifdef CONFIG_STRIDER_CPU
+	unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
+#endif
 	bool hw_type_cat = pca9698_get_value(0x20, 18);
 	bool ch0_sgmii2_present = false;
 

@@ -135,17 +139,25 @@ int last_stage_init(void)
 	pca9698_direction_output(0x20, 8, 0);
 
 	/* Turn on Parade DP501 */
-	pca9698_direction_output(0x20, 9, 1);
+	pca9698_direction_output(0x20, 10, 1);
 
 	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
 
 	/* wait for FPGA done, then reset FPGA */
-	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+	for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
 		unsigned int ctr = 0;
+		unsigned char *mclink_controllers = mclink_controllers_dvi;
 
+#ifdef CONFIG_STRIDER_CPU
+		if (i2c_probe(mclink_controllers[k])) {
+			mclink_controllers = mclink_controllers_dp;
+			if (i2c_probe(mclink_controllers[k]))
+				continue;
+		}
+#else
 		if (i2c_probe(mclink_controllers[k]))
 			continue;
-
+#endif
 		while (!(pca953x_get_val(mclink_controllers[k])
 		       & MCFPGA_DONE)) {
 			udelay(100000);

@@ -192,6 +204,7 @@ int last_stage_init(void)
 
 #ifdef CONFIG_STRIDER_CPU
 	ch7301_probe(0, false);
+	dp501_probe(0, false);
 #endif
 
 	if (slaves <= 0)

@@ -199,6 +212,14 @@ int last_stage_init(void)
 
 	mclink_fpgacount = slaves;
 
+#ifdef CONFIG_STRIDER_CPU
+	/* get ADV7611 out of reset, power up DP501, give some time to wakeup */
+	for (k = 1; k <= slaves; ++k)
+		FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
+
+	udelay(500000);
+#endif
+
 	for (k = 1; k <= slaves; ++k) {
 		ioep_fpga_print_info(k);
 #ifdef CONFIG_STRIDER_CON

@@ -206,10 +227,10 @@ int last_stage_init(void)
 			osd_probe(k);
 #endif
 #ifdef CONFIG_STRIDER_CPU
-		FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
 		if (!adv7611_probe(k))
 			printf("       Advantiv ADV7611 HDMI Receiver\n");
 		ch7301_probe(k, false);
+		dp501_probe(k, false);
 #endif
 		if (hw_type_cat) {
 			miiphy_register(bb_miiphy_buses[k].name,

index 8771cdc..1cae9ab 100644
@@ -334,6 +334,11 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 
 #define CONFIG_PCA953X			/* NXP PCA9554 */
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
+					  {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
+
 #define CONFIG_PCA9698			/* NXP PCA9698 */
 
 #define CONFIG_SYS_I2C_IHS

index 1cae9ab..737c2ed 100644
@@ -283,14 +283,13 @@
 				| BR_PS_16	/* 16 bit port */ \
 				| BR_MS_GPCM	/* MSEL = GPCM */ \
 				| BR_V)		/* valid */
-#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+
+#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET)
+				| OR_GPCM_SCY_5 \
+				| OR_GPCM_TRLX_CLEAR \
+				| OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
 #define CONFIG_SYS_FPGA_DONE(k)		0x0010