Split pinctrl device for Meson8 / Meson8b and update docs
Subsystems (3)
v3 cover Split pinctrl device for Meson8 / Meson8b and update docs
From: Carlo Caione <[email protected]>
With http://www.spinics.net/lists/devicetree/msg116771.html we split / refactor the pinctrl driver to have two different pinctrl devices for each bus.
Unfortunately these two patches still haven't found their way to mainline. Reposting them as standalone patchset. Hopefully they can be ACKed as soon as possible.
Carlo Caione (2):
ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
documentation: Fix pinctrl documentation for Meson8 / Meson8b
.../devicetree/bindings/pinctrl/meson,pinctrl.txt | 38 +++------------ arch/arm/boot/dts/meson8.dtsi | 57 ++++++++++++---------- arch/arm/boot/dts/meson8b.dtsi | 12 ++++- 3 files changed, 49 insertions(+), 58 deletions(-)
Signature · 1 line
2.5.0
PATCH v3 1/2 ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
From: Carlo Caione <[email protected]>
--- arch/arm/boot/dts/meson8.dtsi | 57 ++++++++++++++++++++++++------------------ arch/arm/boot/dts/meson8b.dtsi | 12 +++++++-- 2 files changed, 42 insertions(+), 27 deletions(-)
arch/arm/boot/dts/meson8.dtsi +32 -25
@@ -91,8 +91,8 @@ clock-frequency = <141666666>; }; - pinctrl: pinctrl at c1109880 { - compatible = "amlogic,meson8-pinctrl"; + pinctrl_cbus: pinctrl at c1109880 { + compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0xc1109880 0x10>; #address-cells = <1>; #size-cells = <1>;
@@ -108,29 +108,6 @@ #gpio-cells = <2>; }; - gpio_ao: ao-bank at c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - }; - }; - spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@@ -157,4 +134,34 @@ }; }; + pinctrl_aobus: pinctrl at c8100084 { + compatible = "amlogic,meson8-aobus-pinctrl"; + reg = <0xc8100084 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank at c1108030 { + reg = <0xc8100014 0x4>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + }; }; /* end of / */
arch/arm/boot/dts/meson8b.dtsi +10 -2
@@ -155,8 +155,8 @@ reg = <0xc1108000 0x4>, <0xc1104000 0x460>; }; - pinctrl: pinctrl at c1109880 { - compatible = "amlogic,meson8b-pinctrl"; + pinctrl_cbus: pinctrl at c1109880 { + compatible = "amlogic,meson8b-cbus-pinctrl"; reg = <0xc1109880 0x10>; #address-cells = <1>; #size-cells = <1>;
@@ -171,6 +171,14 @@ gpio-controller; #gpio-cells = <2>; }; + }; + + pinctrl_aobus: pinctrl at c8100084 { + compatible = "amlogic,meson8b-aobus-pinctrl"; + reg = <0xc8100084 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; gpio_ao: ao-bank at c1108030 { reg = <0xc8100014 0x4>,
Signature · 1 line
2.5.0
PATCH v3 1/2 ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
Quoted 4 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Signed-off-by Carlo Caione <[email protected]>Reviewed-by Andreas F?rber <[email protected]>
Please merge this as a fix through the ARM SoC tree.
Yours,
Linus Walleij
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
In reply to Carlo CaioneFrom: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
--- .../devicetree/bindings/pinctrl/meson,pinctrl.txt | 38 ++++------------------ 1 file changed, 7 insertions(+), 31 deletions(-)
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +7 -31
@@ -1,13 +1,16 @@ == Amlogic Meson pinmux controller == Required properties for the root node: - - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl" + - compatible: one of "amlogic,meson8-cbus-pinctrl" + "amlogic,meson8b-cbus-pinctrl" + "amlogic,meson8-aobus-pinctrl" + "amlogic,meson8b-aobus-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === -The 2 power domains of the controller (regular and always-on) are -represented as sub-nodes and each of them acts as a GPIO controller. +The GPIO bank for the controller is represented as a sub-node and it acts as a +GPIO controller. Required properties for sub-nodes are: - reg: should contain address and size for mux, pull-enable, pull and
@@ -18,10 +21,6 @@ Required properties for sub-nodes are: - gpio-controller: identifies the node as a gpio controller - #gpio-cells: must be 2 -Valid sub-node names are: - - "banks" for the regular domain - - "ao-bank" for the always-on domain - === Other sub-nodes === Child nodes without the "gpio-controller" represent some desired
@@ -45,7 +44,7 @@ pinctrl-bindings.txt === Example === pinctrl: pinctrl at c1109880 { - compatible = "amlogic,meson8-pinctrl"; + compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0xc1109880 0x10>; #address-cells = <1>; #size-cells = <1>;
@@ -61,15 +60,6 @@ pinctrl-bindings.txt #gpio-cells = <2>; }; - gpio_ao: ao-bank at c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - nand { mux { groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
@@ -79,18 +69,4 @@ pinctrl-bindings.txt function = "nand"; }; }; - - uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a", - "uart_cts_ao_a", "uart_rts_ao_a"; - function = "uart_ao"; - }; - - conf { - pins = "GPIOAO_0", "GPIOAO_1", - "GPIOAO_2", "GPIOAO_3"; - bias-disable; - }; - }; };
Signature · 1 line
2.5.0
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
Am 23.03.2016 um 10:14 schrieb Carlo Caione:
Quoted 10 lines
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Quoted 4 lines
Signed-off-by Carlo Caione <[email protected]>--- .../devicetree/bindings/pinctrl/meson,pinctrl.txt | 38 ++++------------------ 1 file changed, 7 insertions(+), 31 deletions(-)
Thanks,
Andreas
Signature · 2 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton; HRB 21284 (AG N?rnberg)
Rob Herring
maintainerPATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
In reply to Carlo CaioneQuoted 9 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Aren't you breaking compatibility with old DTs here? If so, you need to be clear that you are and why you think that is okay.
Quoted 4 lines
Signed-off-by Carlo Caione <[email protected]>--- .../devicetree/bindings/pinctrl/meson,pinctrl.txt | 38 ++++------------------ 1 file changed, 7 insertions(+), 31 deletions(-)
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
Quoted 6 lines · Rob Herring
Quoted 5 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
Quoted 7 lines
Quoted 4 lines
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Aren't you breaking compatibility with old DTs here? If so, you need to be clear that you are and why you think that is okay.
Rob,
It's a bit too late to worry about breaking compatibility since the driver changes are already landed in mainline and currently Meson8 and Meson8b platforms are broken because of this.
You can read the whole discussion here [1] and here [2]. Driver and DT changes were supposed to go in together but a bit of general misunderstanding caused this issue.
We decided to break compatibility with the old DTs since the the platform support is still in the really early stage so I really don't think this is going to cause any problem and we have a lot of good reasons to split the pinctrl driver. First of all it makes sense from the hardware prospective, since we actually have two different pin controllers on two different buses. Splitting the driver allows us to introduce in the DTS both CBUS and AOBUS as simple buses. We need a clear description of the two buses in the DTS since several devices have a different register mapping depending on which bus they are attached to. Also as you can read here [3] we want to map the whole CBUS as a syscon device to be able to access several registers scattered inside CBUS.
As Andreas pointed out gxbb arch already models CBUS and AOBUS as simple-buses so we could reuse this driver also for that architecture.
Thanks,
[1] http://www.spinics.net/lists/arm-kernel/msg489730.html
[2] http://www.spinics.net/lists/devicetree/msg116771.html
[3] http://www.spinics.net/lists/devicetree/msg115019.html
Signature · 1 line
Carlo Caione | +39.340.80.30.096 | Endless
Rob Herring
maintainerPATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
Quoted 15 lines · Carlo Caione
Quoted 6 lines · Rob Herring
Quoted 5 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
Quoted 7 lines
Quoted 4 lines
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Aren't you breaking compatibility with old DTs here? If so, you need to be clear that you are and why you think that is okay.
Quoted 7 lines
Rob,
It's a bit too late to worry about breaking compatibility since the driver changes are already landed in mainline and currently Meson8 and Meson8b platforms are broken because of this.
You can read the whole discussion here [1] and here [2]. Driver and DT changes were supposed to go in together but a bit of general misunderstanding caused this issue.
My comment was the commit message needs to be clear that you are breaking compatibility. That was true before part of this went in.
Quoted 13 lines
We decided to break compatibility with the old DTs since the the platform support is still in the really early stage so I really don't think this is going to cause any problem and we have a lot of good reasons to split the pinctrl driver. First of all it makes sense from the hardware prospective, since we actually have two different pin controllers on two different buses. Splitting the driver allows us to introduce in the DTS both CBUS and AOBUS as simple buses. We need a clear description of the two buses in the DTS since several devices have a different register mapping depending on which bus they are attached to. Also as you can read here [3] we want to map the whole CBUS as a syscon device to be able to access several registers scattered inside CBUS.
Quoted 1 line
From a quick glance, you mainly needed to keep the old compatible string
in the driver and just ignore ao-bank. Then only what depended on ao-bank would break. Maybe that's less broken than completely breaking the pinctrl driver...
Anyway, merge the fix:
Rob
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
In reply to Carlo CaioneQuoted 11 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Signed-off-by Carlo Caione <[email protected]>
This patch applied to the pinctrl tree with the tags.
It is just documentation so it's obviously not an urgent fix.
Please merge patch 1/2 through the ARM SoC tree.
Yours,
Linus Walleij
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
Quoted 12 lines · Linus Walleij
Quoted 10 lines · Carlo Caione
From: Carlo Caione <[email protected]>
Fix pin controller documentation introducing the new compatibles for the pinctrl drivers specific for aobus / cbus.
This is needed because we have changed the pin controller driver: we have now a single specialized pinctrl driver / compatible for each bus the controller is attached to, instead of one single driver dealing with all the controllers we have on different buses.
Quoted 8 lines
Quoted 1 line
Signed-off-by Carlo Caione <[email protected]>This patch applied to the pinctrl tree with the tags.
It is just documentation so it's obviously not an urgent fix.
Please merge patch 1/2 through the ARM SoC tree.
Hey Linus,
I already submitted DT fix and Documentation in the PR to arm-soc here
http://www.spinics.net/lists/arm-kernel/msg493680.html
Cheers,
Signature · 1 line
Carlo Caione
PATCH v3 2/2 documentation: Fix pinctrl documentation for Meson8 / Meson8b
Quoted 5 lines · Carlo Caione
On Thu, Mar 31, 2016 at 11:38 AM, Linus Walleij
Hey Linus,
I already submitted DT fix and Documentation in the PR to arm-soc here
http://www.spinics.net/lists/arm-kernel/msg493680.html
Aha OK I will take the doc fix out of my tree then and expect this to be fixed through ARM SoC.
Yours,
Linus Walleij
Kevin Hilman
maintainerv3 cover Split pinctrl device for Meson8 / Meson8b and update docs
In reply to Carlo CaioneQuoted 8 lines · Carlo Caione
From: Carlo Caione <[email protected]>
With http://www.spinics.net/lists/devicetree/msg116771.html we split / refactor the pinctrl driver to have two different pinctrl devices for each bus.
Unfortunately these two patches still haven't found their way to mainline. Reposting them as standalone patchset. Hopefully they can be ACKed as soon as possible.
I confirm that this gets meson8b-odroidc1 booting again in mainline.
Kevin