ARM: keystone2: Fix missing privilege ID
Nishanth Menon
maintainercover ARM: keystone2: Fix missing privilege ID
Looks like Keystone2 platform may have quite a few missing configurations for various SoC variants. We need mark each of these id as shared in corresponding registers as well, without doing this, drivers fail inexplicably since the drivers seem to expect SoC wide coherency capability - which needs to be configured explicitly.
Bootlog:
k2g: http://pastebin.ubuntu.com/15480089/
k2hk: http://pastebin.ubuntu.com/15480090/
also tested on an slightly older bootloader on K2E/K2L as well:
k2g: http://pastebin.ubuntu.com/15475588/ k2hk: http://pastebin.ubuntu.com/15475589/ k2l: http://pastebin.ubuntu.com/15478358/ k2e: http://pastebin.ubuntu.com/15478332/
This series is based on:
master 0764f24ae6bc net: Move CONFIG_RTL8169 to Kconfig
NOTE: K2G still requires additional patches for fixing NAND to prevent data abort being registered early in the boot by u-boot wrong access to GPMC. (testing was performed using out-of-tree solution for this)
Nishanth Menon (2):
ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
ARM: keystone2: Add missing privilege ID settings
arch/arm/mach-keystone/include/mach/hardware-k2e.h | 3 - arch/arm/mach-keystone/include/mach/hardware-k2l.h | 3 - arch/arm/mach-keystone/include/mach/hardware.h | 50 ++++++++++++--- arch/arm/mach-keystone/init.c | 73 +++++++++++++++++++--- 4 files changed, 106 insertions(+), 23 deletions(-)
Signature · 1 line
2.8.0.rc3
Nishanth Menon
maintainerPATCH 1/2 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact.
--- arch/arm/mach-keystone/include/mach/hardware-k2e.h | 3 -- arch/arm/mach-keystone/include/mach/hardware-k2l.h | 3 -- arch/arm/mach-keystone/include/mach/hardware.h | 27 +++++++++----- arch/arm/mach-keystone/init.c | 43 ++++++++++++++++++---- 4 files changed, 53 insertions(+), 23 deletions(-)
arch/arm/mach-keystone/include/mach/hardware-k2e.h +0 -3
@@ -34,9 +34,6 @@#define KS2_LPSC_PCIE_1 27#define KS2_LPSC_XGE 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 13 -/* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1/* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1/* not defined in K2E */
arch/arm/mach-keystone/include/mach/hardware-k2l.h +0 -3
@@ -53,9 +53,6 @@#define KS2_LPSC_FFTC_B 49#define KS2_LPSC_IQN_AIL 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 14 -/* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
arch/arm/mach-keystone/include/mach/hardware.h +17 -10
@@ -215,16 +215,23 @@ typedef volatile unsigned int *dv_reg_p;/* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000#define KS2_MSMC_DATA_BASE 0x0c000000 -#ifndef CONFIG_SOC_K2G -#define KS2_MSMC_SEGMENT_TETRIS 8 -#define KS2_MSMC_SEGMENT_NETCP 9 -#define KS2_MSMC_SEGMENT_QM_PDSP 10 -#define KS2_MSMC_SEGMENT_PCIE0 11 -#else -#define KS2_MSMC_SEGMENT_TETRIS 1 -#define KS2_MSMC_SEGMENT_NETCP 4 -#define KS2_MSMC_SEGMENT_PCIE0 5 -#endif + +/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ +#define K2HKLE_MSMC_SEGMENT_ARM 8 +#define K2HKLE_MSMC_SEGMENT_NETCP 9 +#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10 +#define K2HKLE_MSMC_SEGMENT_PCIE0 11 + +/* K2L specific Privilege ID Settings */ +#define K2L_MSMC_SEGMENT_PCIE1 14 + +/* K2E specific Privilege ID Settings */ +#define K2E_MSMC_SEGMENT_PCIE1 13 + +/* K2G specific Privilege ID Settings */ +#define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_NSS 4 +#define K2G_MSMC_SEGMENT_PCIE 5/* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12
arch/arm/mach-keystone/init.c +36 -7
58 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3
PATCH 1/2 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
Quoted 8 lines · Nishanth Menon
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact.
Thanks and regards,
Lokesh
Quoted 139 lines
Signed-off-by Nishanth Menon <[email protected]>--- arch/arm/mach-keystone/include/mach/hardware-k2e.h | 3 -- arch/arm/mach-keystone/include/mach/hardware-k2l.h | 3 -- arch/arm/mach-keystone/include/mach/hardware.h | 27 +++++++++----- arch/arm/mach-keystone/init.c | 43 ++++++++++++++++++---- 4 files changed, 53 insertions(+), 23 deletions(-)arch/arm/mach-keystone/include/mach/hardware-k2e.h +0
-3@@ -34,9 +34,6 @@#define KS2_LPSC_PCIE_1 27#define KS2_LPSC_XGE 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 13 -/* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1/* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1/* not defined in K2E */ arch/arm/mach-keystone/include/mach/hardware-k2l.h +0
-3@@ -53,9 +53,6 @@#define KS2_LPSC_FFTC_B 49#define KS2_LPSC_IQN_AIL 50 -/* MSMC */ -#define KS2_MSMC_SEGMENT_PCIE1 14 -/* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01Darch/arm/mach-keystone/include/mach/hardware.h +17
-10@@ -215,16 +215,23 @@ typedef volatile unsigned int *dv_reg_p;/* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000#define KS2_MSMC_DATA_BASE 0x0c000000 -#ifndef CONFIG_SOC_K2G -#define KS2_MSMC_SEGMENT_TETRIS 8 -#define KS2_MSMC_SEGMENT_NETCP 9 -#define KS2_MSMC_SEGMENT_QM_PDSP 10 -#define KS2_MSMC_SEGMENT_PCIE0 11 -#else -#define KS2_MSMC_SEGMENT_TETRIS 1 -#define KS2_MSMC_SEGMENT_NETCP 4 -#define KS2_MSMC_SEGMENT_PCIE0 5 -#endif + +/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ +#define K2HKLE_MSMC_SEGMENT_ARM 8 +#define K2HKLE_MSMC_SEGMENT_NETCP 9 +#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10 +#define K2HKLE_MSMC_SEGMENT_PCIE0 11 + +/* K2L specific Privilege ID Settings */ +#define K2L_MSMC_SEGMENT_PCIE1 14 + +/* K2E specific Privilege ID Settings */ +#define K2E_MSMC_SEGMENT_PCIE1 13 + +/* K2G specific Privilege ID Settings */ +#define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_NSS 4 +#define K2G_MSMC_SEGMENT_PCIE 5/* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12arch/arm/mach-keystone/init.c +36
-7@@ -96,22 +96,51 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode)__raw_writel (val,KS2_DEVCFG ); } +static void msmc_k2hkle_common_setup (void ) +{ +msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_ARM ); +msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_NETCP ); +#ifdef KS2_MSMC_SEGMENT_QM_PDSP +msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_QM_PDSP ); +#endif +msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_PCIE0 ); +} + +static inline void msmc_k2l_setup (void ) +{ +msmc_share_all_segments (K2L_MSMC_SEGMENT_PCIE1 ); +} + +static inline void msmc_k2e_setup (void ) +{ +msmc_share_all_segments (K2E_MSMC_SEGMENT_PCIE1 ); +} + +static inline void msmc_k2g_setup (void ) +{ +msmc_share_all_segments (K2G_MSMC_SEGMENT_ARM ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_NSS ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_PCIE ); +} +int arch_cpu_init (void ) {chip_configuration_unlock ();icache_enable (); -msmc_share_all_segments (KS2_MSMC_SEGMENT_TETRIS ); -msmc_share_all_segments (KS2_MSMC_SEGMENT_NETCP ); -#ifdef KS2_MSMC_SEGMENT_QM_PDSP -msmc_share_all_segments (KS2_MSMC_SEGMENT_QM_PDSP ); -#endif -msmc_share_all_segments (KS2_MSMC_SEGMENT_PCIE0 ); +if (cpu_is_k2g ()) { +msmc_k2g_setup (); + }else { +msmc_k2hkle_common_setup (); +if (cpu_is_k2e ()) +msmc_k2e_setup (); +else if (cpu_is_k2l ()) +msmc_k2l_setup (); + }/* Initialize the PCIe-0 to work as Root Complex */ config_pcie_mode (0 ,ROOTCOMPLEX );#if defined(CONFIG_SOC_K2E ) || defined(CONFIG_SOC_K2L ) -msmc_share_all_segments (KS2_MSMC_SEGMENT_PCIE1 );/* Initialize the PCIe-1 to work as Root Complex */ config_pcie_mode (1 ,ROOTCOMPLEX );#endif
PATCH 1/2 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
In reply to Nishanth MenonQuoted 10 lines · Nishanth Menon
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact.
Signed-off-by Nishanth Menon <[email protected]>
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PATCH 1/2 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
In reply to Nishanth MenonQuoted 5 lines · Nishanth Menon
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC.
Quoted 7 lines
As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact.
Signed-off-by Nishanth Menon <[email protected]>Reviewed-by Lokesh Vutla <[email protected]>Reviewed-by Tom Rini <[email protected]>
Applied to u-boot/master, thanks!
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Nishanth Menon
maintainerPATCH 2/2 ARM: keystone2: Add missing privilege ID settings
In reply to Nishanth MenonAdd missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------
0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved
-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact).
By marking these segments as shared, we also ensure SoC wide coherency is enabled.
--- arch/arm/mach-keystone/include/mach/hardware.h | 23 ++++++++++++++++++ arch/arm/mach-keystone/init.c | 32 +++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-)
arch/arm/mach-keystone/include/mach/hardware.h +23 -0
@@ -216,22 +216,45 @@ typedef volatile unsigned int *dv_reg_p;#define KS2_MSMC_CTRL_BASE 0x0bc00000#define KS2_MSMC_DATA_BASE 0x0c000000 +/* KS2 Generic Privilege ID Settings for MSMC2 */ +#define KS2_MSMC_SEGMENT_C6X_0 0 +#define KS2_MSMC_SEGMENT_C6X_1 1 +#define KS2_MSMC_SEGMENT_C6X_2 2 +#define KS2_MSMC_SEGMENT_C6X_3 3 +#define KS2_MSMC_SEGMENT_C6X_4 4 +#define KS2_MSMC_SEGMENT_C6X_5 5 +#define KS2_MSMC_SEGMENT_C6X_6 6 +#define KS2_MSMC_SEGMENT_C6X_7 7 + +#define KS2_MSMC_SEGMENT_DEBUG 12 +/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ #define K2HKLE_MSMC_SEGMENT_ARM 8#define K2HKLE_MSMC_SEGMENT_NETCP 9#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10#define K2HKLE_MSMC_SEGMENT_PCIE0 11 +/* K2HK specific Privilege ID Settings */ +#define K2HKE_MSMC_SEGMENT_HYPERLINK 14 +/* K2L specific Privilege ID Settings */ #define K2L_MSMC_SEGMENT_PCIE1 14/* K2E specific Privilege ID Settings */ #define K2E_MSMC_SEGMENT_PCIE1 13 +#define K2E_MSMC_SEGMENT_TSIP 15/* K2G specific Privilege ID Settings */ #define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_ICSS0 2 +#define K2G_MSMC_SEGMENT_ICSS1 3#define K2G_MSMC_SEGMENT_NSS 4#define K2G_MSMC_SEGMENT_PCIE 5 +#define K2G_MSMC_SEGMENT_USB 6 +#define K2G_MSMC_SEGMENT_MLB 8 +#define K2G_MSMC_SEGMENT_PMMC 9 +#define K2G_MSMC_SEGMENT_DSS 10 +#define K2G_MSMC_SEGMENT_MMC 11/* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12
arch/arm/mach-keystone/init.c +31 -1
@@ -98,29 +98,57 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode)static void msmc_k2hkle_common_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_0 );msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_ARM );msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_NETCP );#ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_QM_PDSP );#endif msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_PCIE0 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_DEBUG ); +} + +static void msmc_k2hk_setup (void ) +{ +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_1 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_2 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_3 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_4 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_5 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_6 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_7 ); +msmc_share_all_segments (K2HKE_MSMC_SEGMENT_HYPERLINK ); }static inline void msmc_k2l_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_1 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_2 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_3 );msmc_share_all_segments (K2L_MSMC_SEGMENT_PCIE1 ); }static inline void msmc_k2e_setup (void ) {msmc_share_all_segments (K2E_MSMC_SEGMENT_PCIE1 ); +msmc_share_all_segments (K2HKE_MSMC_SEGMENT_HYPERLINK ); +msmc_share_all_segments (K2E_MSMC_SEGMENT_TSIP ); } -static inline void msmc_k2g_setup (void ) +static void msmc_k2g_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_0 );msmc_share_all_segments (K2G_MSMC_SEGMENT_ARM ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_ICSS0 ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_ICSS1 );msmc_share_all_segments (K2G_MSMC_SEGMENT_NSS );msmc_share_all_segments (K2G_MSMC_SEGMENT_PCIE ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_USB ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_MLB ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_PMMC ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_DSS ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_MMC ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_DEBUG ); }int arch_cpu_init (void )
@@ -136,6 +164,8 @@ int arch_cpu_init(void)msmc_k2e_setup (); else if (cpu_is_k2l()) msmc_k2l_setup(); + else +msmc_k2hk_setup (); }/* Initialize the PCIe-0 to work as Root Complex */
Signature · 1 line
2.8.0.rc3
PATCH 2/2 ARM: keystone2: Add missing privilege ID settings
Quoted 38 lines · Nishanth Menon
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state.
Quoted 8 lines
Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact).
By marking these segments as shared, we also ensure SoC wide coherency is enabled.
Thanks and regards,
Lokesh
Quoted 131 lines
Reported-by Bin Liu <[email protected]>Signed-off-by Nishanth Menon <[email protected]>--- arch/arm/mach-keystone/include/mach/hardware.h | 23 ++++++++++++++++++ arch/arm/mach-keystone/init.c | 32 +++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-)arch/arm/mach-keystone/include/mach/hardware.h +23
-0@@ -216,22 +216,45 @@ typedef volatile unsigned int *dv_reg_p;#define KS2_MSMC_CTRL_BASE 0x0bc00000#define KS2_MSMC_DATA_BASE 0x0c000000 +/* KS2 Generic Privilege ID Settings for MSMC2 */ +#define KS2_MSMC_SEGMENT_C6X_0 0 +#define KS2_MSMC_SEGMENT_C6X_1 1 +#define KS2_MSMC_SEGMENT_C6X_2 2 +#define KS2_MSMC_SEGMENT_C6X_3 3 +#define KS2_MSMC_SEGMENT_C6X_4 4 +#define KS2_MSMC_SEGMENT_C6X_5 5 +#define KS2_MSMC_SEGMENT_C6X_6 6 +#define KS2_MSMC_SEGMENT_C6X_7 7 + +#define KS2_MSMC_SEGMENT_DEBUG 12 +/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ #define K2HKLE_MSMC_SEGMENT_ARM 8#define K2HKLE_MSMC_SEGMENT_NETCP 9#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10#define K2HKLE_MSMC_SEGMENT_PCIE0 11 +/* K2HK specific Privilege ID Settings */ +#define K2HKE_MSMC_SEGMENT_HYPERLINK 14 +/* K2L specific Privilege ID Settings */ #define K2L_MSMC_SEGMENT_PCIE1 14/* K2E specific Privilege ID Settings */ #define K2E_MSMC_SEGMENT_PCIE1 13 +#define K2E_MSMC_SEGMENT_TSIP 15/* K2G specific Privilege ID Settings */ #define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_ICSS0 2 +#define K2G_MSMC_SEGMENT_ICSS1 3#define K2G_MSMC_SEGMENT_NSS 4#define K2G_MSMC_SEGMENT_PCIE 5 +#define K2G_MSMC_SEGMENT_USB 6 +#define K2G_MSMC_SEGMENT_MLB 8 +#define K2G_MSMC_SEGMENT_PMMC 9 +#define K2G_MSMC_SEGMENT_DSS 10 +#define K2G_MSMC_SEGMENT_MMC 11/* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12arch/arm/mach-keystone/init.c +31
-1@@ -98,29 +98,57 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode)static void msmc_k2hkle_common_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_0 );msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_ARM );msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_NETCP );#ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_QM_PDSP );#endif msmc_share_all_segments (K2HKLE_MSMC_SEGMENT_PCIE0 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_DEBUG ); +} + +static void msmc_k2hk_setup (void ) +{ +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_1 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_2 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_3 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_4 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_5 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_6 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_7 ); +msmc_share_all_segments (K2HKE_MSMC_SEGMENT_HYPERLINK ); }static inline void msmc_k2l_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_1 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_2 ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_3 );msmc_share_all_segments (K2L_MSMC_SEGMENT_PCIE1 ); }static inline void msmc_k2e_setup (void ) {msmc_share_all_segments (K2E_MSMC_SEGMENT_PCIE1 ); +msmc_share_all_segments (K2HKE_MSMC_SEGMENT_HYPERLINK ); +msmc_share_all_segments (K2E_MSMC_SEGMENT_TSIP ); } -static inline void msmc_k2g_setup (void ) +static void msmc_k2g_setup (void ) { +msmc_share_all_segments (KS2_MSMC_SEGMENT_C6X_0 );msmc_share_all_segments (K2G_MSMC_SEGMENT_ARM ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_ICSS0 ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_ICSS1 );msmc_share_all_segments (K2G_MSMC_SEGMENT_NSS );msmc_share_all_segments (K2G_MSMC_SEGMENT_PCIE ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_USB ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_MLB ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_PMMC ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_DSS ); +msmc_share_all_segments (K2G_MSMC_SEGMENT_MMC ); +msmc_share_all_segments (KS2_MSMC_SEGMENT_DEBUG ); }int arch_cpu_init (void )@@ -136,6 +164,8 @@ int arch_cpu_init(void)msmc_k2e_setup (); else if (cpu_is_k2l()) msmc_k2l_setup(); + else +msmc_k2hk_setup (); }/* Initialize the PCIe-0 to work as Root Complex */
PATCH 2/2 ARM: keystone2: Add missing privilege ID settings
In reply to Nishanth MenonQuoted 12 lines · Nishanth Menon
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Quoted 1 line
Overall mapping:
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PATCH 2/2 ARM: keystone2: Add missing privilege ID settings
In reply to Nishanth MenonQuoted 12 lines · Nishanth Menon
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Quoted 1 line
Overall mapping:
Applied to u-boot/master, thanks!
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