arm64: opcodes.h: Add arm big-endian config options before including arm header
PATCH 1/1 arm64: opcodes.h: Add arm big-endian config options before including arm header
arm and arm64 use different config options to specify big endian. This needs taking into account when including code/headers between the two architectures.
A case in point is PAN, which uses the __instr_arm() macro to output instructions. The macro comes from opcodes.h, which lives under arch/arm. On a big-endian build the mismatched config options mean the instruction isn't byte swapped correctly, resulting in undefined instruction exceptions during boot:
Quoted 19 lines
alternatives: patching kernel code kdevtmpfs[87]: undefined instruction: pc=ffffffc0004505b4 kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
Internal error: Oops - undefined instruction: 0 [#1] SMP Modules linked in: CPU: 0 PID: 87 Comm: kdevtmpfs Not tainted 4.1.16+ #5 Hardware name: Hisilicon PhosphorHi1382 EVB (DT) task: ffffffc336591700 ti: ffffffc3365a4000 task.ti: ffffffc3365a4000 PC is at dump_instr+0x68/0x100 LR is at do_undefinstr+0x1d4/0x2a4 pc : [<ffffffc00076231c>] lr : [<ffffffc0000811d4>] pstate: 604001c5
Quoted 1 line
sp :
ffffffc3365a6450
--- arch/arm64/include/asm/opcodes.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm64/include/asm/opcodes.h +4 -0
@@ -1 +1,5 @@ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define CONFIG_CPU_ENDIAN_BE8 CONFIG_CPU_BIG_ENDIAN +#endif +#include <../../arm/include/asm/opcodes.h>
Signature · 1 line
2.8.0.rc3
PATCH 1/1 arm64: opcodes.h: Add arm big-endian config options before including arm header
Quoted 29 lines · James Morse
arm and arm64 use different config options to specify big endian. This needs taking into account when including code/headers between the two architectures.
A case in point is PAN, which uses the
__instr_arm()macro to output instructions. The macro comes fromopcodes.h, which lives underarch/arm. On a big-endian build the mismatched config options mean the instruction isn't byte swapped correctly, resulting in undefined instruction exceptions during boot:Quoted 19 lines
alternatives: patching kernel code kdevtmpfs[87]: undefined instruction: pc=ffffffc0004505b4 kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
Internal error: Oops - undefined instruction: 0 [#1] SMP Modules linked in: CPU: 0 PID: 87 Comm: kdevtmpfs Not tainted 4.1.16+ #5 Hardware name: Hisilicon PhosphorHi1382 EVB (DT) task: ffffffc336591700 ti: ffffffc3365a4000 task.ti: ffffffc3365a4000 PC is at dump_instr+0x68/0x100 LR is at do_undefinstr+0x1d4/0x2a4 pc : [<ffffffc00076231c>] lr : [<ffffffc0000811d4>] pstate: 604001c5Quoted 1 line
sp :
ffffffc3365a6450
Quoted 1 line
Reported-by Hanjun Guo <[email protected]>
My colleague Xuefeng helped to test this patch, and the bug reported is gone,
Thanks
Hanjun