imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

PATCH New Peng Fan 2 participants 5 messages Mar 9, 2016 – Mar 25, 2016 Arm (32-bit)

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Peng Fan

author

2016-03-09 08:13 UTC #0 lore raw

PATCH 1/1 imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

From: Ye Li <[email protected]>

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by Ye Li <[email protected]>

Signed-off-by Peng Fan <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx6/soc.c +4 -1

index 91a3deb..bdd41b0 100644
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }

Signature · 1 line

2.6.2

Stefano Babic

2016-03-09 09:47 UTC #1 lore raw

PATCH 1/1 imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Hi Peng, Ye,

Quoted 19 lines · Peng Fan

From: Ye Li <[email protected]>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 91a3deb..bdd41b0 100644
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);

arch/arm/cpu/armv7/mx6/soc.c static void clear_mmdc_ch_mask(void) · line 287

Quoted 10 lines

arch/arm/cpu/armv7/mx6/soc.c +4 -1

 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }

Acked-by Stefano Babic <[email protected]>

This is a fix, and my question to you both: is it enough to merge it after 2016.03 ? I have not read about big issues due to periph_clk_sel, and maybe we can postponed it (or I merge directly into -next as several of you have already proposed).

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

author

2016-03-09 09:37 UTC #2 lore raw

PATCH 1/1 imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Hi Stefano,

Quoted 35 lines · Stefano Babic

Hi Peng, Ye,
Quoted 19 lines · Peng Fan
From: Ye Li <[email protected]>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 91a3deb..bdd41b0 100644
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
arch/arm/cpu/armv7/mx6/soc.c static void clear_mmdc_ch_mask(void) · line 287
Quoted 10 lines
arch/arm/cpu/armv7/mx6/soc.c +4 -1
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
Acked-by Stefano Babic <[email protected]>

Quoted 4 lines

This is a fix, and my question to you both: is it enough to merge it after 2016.03 ? I have not read about big issues due to periph_clk_sel, and maybe we can postponed it (or I merge directly into -next as several of you have already proposed).

Yeah. It's okay to merge after 2016.03.

Regards,
Peng.

Quoted 12 lines

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

author

2016-03-25 09:14 UTC #3 lore raw

PATCH 1/1 imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Hi Stefano,

Quoted 38 lines · Peng Fan

Hi Stefano,
Quoted 35 lines · Stefano Babic
Hi Peng, Ye,
Quoted 19 lines · Peng Fan
From: Ye Li <[email protected]>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 91a3deb..bdd41b0 100644
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
arch/arm/cpu/armv7/mx6/soc.c static void clear_mmdc_ch_mask(void) · line 287
Quoted 10 lines
arch/arm/cpu/armv7/mx6/soc.c +4 -1
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
Acked-by Stefano Babic <[email protected]>

Quoted 6 lines

Quoted 4 lines
This is a fix, and my question to you both: is it enough to merge it after 2016.03 ? I have not read about big issues due to periph_clk_sel, and maybe we can postponed it (or I merge directly into -next as several of you have already proposed).
Yeah. It's okay to merge after 2016.03.

Will you pick up this patch?

Regards,
Peng.

Quoted 16 lines

Regards,
Peng.

Quoted 12 lines

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2016-03-25 09:31 UTC #4 lore raw

PATCH 1/1 imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Quoted 47 lines · Peng Fan

Hi Stefano,
Quoted 44 lines · Peng Fan
Hi Stefano,
Quoted 35 lines · Stefano Babic
Hi Peng, Ye,
Quoted 19 lines · Peng Fan
From: Ye Li <[email protected]>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by Ye Li <[email protected]>
Signed-off-by Peng Fan <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index 91a3deb..bdd41b0 100644
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
arch/arm/cpu/armv7/mx6/soc.c static void clear_mmdc_ch_mask(void) · line 287
Quoted 10 lines
arch/arm/cpu/armv7/mx6/soc.c +4 -1
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
Acked-by Stefano Babic <[email protected]>
Quoted 4 lines
This is a fix, and my question to you both: is it enough to merge it after 2016.03 ? I have not read about big issues due to periph_clk_sel, and maybe we can postponed it (or I merge directly into -next as several of you have already proposed).
Yeah. It's okay to merge after 2016.03.

I do it

Stefano

Quoted 22 lines

Will you pick up this patch?

Regards,
Peng.

Quoted 16 lines

Regards,
Peng.

Quoted 12 lines

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================