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armv8: fsl-layerscape: change LS1043A SVR register

PATCH New Gong Qianyu 2 participants 4 messages Mar 23, 2016 – Mar 29, 2016 Arm (32-bit)

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Gong Qianyu

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PATCH 1/2 armv8: fsl-layerscape: change LS1043A SVR register

From: Mingkai Hu <[email protected]>

Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Gong Qianyu <[email protected]>
---
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -1
index ea78e15..512a8e0 100644
@@ -41,7 +41,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
-#define SVR_LS1043		0x879204
+#define SVR_LS1043		0x879200
 #define SVR_LS2045		0x870120
 #define SVR_LS2080		0x870110
 #define SVR_LS2085		0x870100
Signature · 1 line
2.1.0.27.g96db324
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#1 lore raw

PATCH 2/2 armv8: fsl-layerscape: add LS1023A SVR

From: Mingkai Hu <[email protected]>

Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Gong Qianyu <[email protected]>
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
 2 files changed, 2 insertions(+)
arch/arm/include/asm/arch-fsl-layerscape/cpu.h +1 -0
index 794b764..a9dadfa 100644
@@ -12,6 +12,7 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
 };
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 512a8e0..56989e1 100644
@@ -42,6 +42,7 @@ struct cpu_type {
 
 #define SVR_WO_E		0xFFFFFE
 #define SVR_LS1043		0x879200
+#define SVR_LS1023		0x879208
 #define SVR_LS2045		0x870120
 #define SVR_LS2080		0x870110
 #define SVR_LS2085		0x870100
Signature · 1 line
2.1.0.27.g96db324