mpc85xx: Enable pre-relocation malloc for MPC85xx

RFC PATCH Superseded Mario Six 2 participants 15 messages Mar 30, 2016 – Apr 8, 2016 PowerPC

lore

Share & tools

lore

York Sun

2016-03-30 15:44 UTC #1 lore raw

RFC PATCH 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoted 62 lines · Mario Six

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 8 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -8

index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,

arch/powerpc/cpu/mpc85xx/start.S +17 -0

index d867e2a..e6b5203 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1181

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/start.S +10 -0

+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+
+	/* Fix issue with exception handler alignment */
+	nop
+	nop
+	nop

Why do you need this? Does the code get too long and enters exception handler space?

arch/powerpc/cpu/mpc85xx/start.S _start_cont:

Quoted 5 lines

arch/powerpc/cpu/mpc85xx/start.S +1 -1

+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
--

This patch presumes stack is right under GD, which is OK. But CONFIG_SYS_MALLOC_F_LEN has not been used by powerpc. Presumption of (CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE) < CONFIG_SYS_INIT_RAM_SIZE may not be true. Would it be better to check@compiling time to make sure we have enough init ram for the malloc len?

York

Mario Six

author

2016-03-31 06:29 UTC #2 lore raw

RFC PATCH 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoting York Sun <[email protected]>:

Quoted 70 lines · Mario Six

Quoted 69 lines

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 8 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -8

index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,

arch/powerpc/cpu/mpc85xx/start.S +22 -0

index d867e2a..e6b5203 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16

Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1181
Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +5 -0
+
+	/* Fix issue with exception handler alignment */
+	nop
+	nop
+	nop
Why do you need this? Does the code get too long and enters exception handler space?

Those are the reason I sent the patch as RFC: There seems to be some kind of alignment issue with the exception vectors. If the nops are not there, the board crashes as soon as the timer_interrupt is raised for the first time. The
commit 96d2bb952bbf2e5a14f6ad668312cbce3cc4485a (powerpc/mpc85xx: Don't relocate exception vectors), among other things, removed the explicit alignment
of the vectors for E500. If you add those back in (and remove the nops), the code works too. So maybe some kind of alignment for the vectors is needed after
all?

Quoted 6 lines

arch/powerpc/cpu/mpc85xx/start.S _start_cont:
Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +1 -1
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
--

Quoted 8 lines

This patch presumes stack is right under GD, which is OK. But CONFIG_SYS_MALLOC_F_LEN has not been used by powerpc. Presumption of (CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE) < CONFIG_SYS_INIT_RAM_SIZE
may not be true. Would it be better to check at compiling time to make sure we
have enough init ram for the malloc len?

Yes, good idea; I'll add an appropriate check in v2 of the patch. Maybe something like

#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE + 0x80 > CONFIG_SYS_INIT_RAM_SIZE
#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif

to ensure we leave at least a minimum of ~128 byte stack space, too?

Quoted 1 line

York

Best regards,

Mario

York Sun

2016-03-31 16:23 UTC #3 lore raw

RFC PATCH 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoted 83 lines · Mario Six

Quoting York Sun <[email protected]>:

Quoted 70 lines · Mario Six

Quoted 69 lines

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 8 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -8

index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,

arch/powerpc/cpu/mpc85xx/start.S +22 -0

index d867e2a..e6b5203 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16

Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1181
Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +5 -0
+
+	/* Fix issue with exception handler alignment */
+	nop
+	nop
+	nop
Why do you need this? Does the code get too long and enters exception handler space?

Quoted 11 lines

Those are the reason I sent the patch as RFC: There seems to be some kind of alignment issue with the exception vectors. If the nops are not there, the board crashes as soon as the timer_interrupt is raised for the first time. The
commit 96d2bb952bbf2e5a14f6ad668312cbce3cc4485a (powerpc/mpc85xx: Don't relocate exception vectors), among other things, removed the explicit alignment
of the vectors for E500. If you add those back in (and remove the nops), the code works too. So maybe some kind of alignment for the vectors is needed after
all?

There is requirement for alignment. For e500 core, the interrupt vector offset registers (IVORs) have lowest 4 bit cleared. So the vectors must be aligned to 16 bytes. For legacy cores, the exception vectors are fixed. You have to make sure the vectors are exactly where they should be.

I think you can use .align 4. Try it.

Quoted 19 lines

Quoted 7 lines
arch/powerpc/cpu/mpc85xx/start.S _start_cont:
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/start.S +1 -1
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
--
Quoted 8 lines
This patch presumes stack is right under GD, which is OK. But CONFIG_SYS_MALLOC_F_LEN has not been used by powerpc. Presumption of (CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE) < CONFIG_SYS_INIT_RAM_SIZE
may not be true. Would it be better to check at compiling time to make sure we
have enough init ram for the malloc len?
Yes, good idea; I'll add an appropriate check in v2 of the patch. Maybe something like

Quoted 7 lines

#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE + 0x80 > CONFIG_SYS_INIT_RAM_SIZE
#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif
to ensure we leave at least a minimum of ~128 byte stack space, too?

I don't think so. We know the size of GD, and we know the size of MALLOC_LEN. But we don't know the depth of stack until we compile it. I would put GD on top, followed by MALLOC, and leave the rest to stack. I know the DDR driver we use needs way more than 128 bytes for stack.

York

Mario Six

author

2016-04-01 07:40 UTC #4 lore raw

RFC PATCH 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoting York Sun <[email protected]>:

Quoted 97 lines · Mario Six

Quoted 84 lines
Quoting York Sun <[email protected]>:
Quoted 71 lines · Mario Six
Quoted 70 lines
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28  
++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 8 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -8
index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
arch/powerpc/cpu/mpc85xx/start.S +22 -0
index d867e2a..e6b5203 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
Quoted 9 lines
arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1181
Quoted 5 lines
arch/powerpc/cpu/mpc85xx/start.S +5 -0
+
+	/* Fix issue with exception handler alignment */
+	nop
+	nop
+	nop
Why do you need this? Does the code get too long and enters exception handler space?
Quoted 11 lines
Those are the reason I sent the patch as RFC: There seems to be some kind of alignment issue with the exception vectors. If the nops are not there, the board crashes as soon as the timer_interrupt is raised for the first time. The
commit 96d2bb952bbf2e5a14f6ad668312cbce3cc4485a (powerpc/mpc85xx: Don't relocate exception vectors), among other things, removed the explicit alignment
of the vectors for E500. If you add those back in (and remove the nops), the code works too. So maybe some kind of alignment for the vectors is needed after
all?

Quoted 9 lines

There is requirement for alignment. For e500 core, the interrupt vector offset
registers (IVORs) have lowest 4 bit cleared. So the vectors must be aligned to
16 bytes. For legacy cores, the exception vectors are fixed. You have to make sure the vectors are exactly where they should be.
I think you can use .align 4. Try it.

Tried it and works perfectly, thanks. Will include this in v2, too.

Quoted 24 lines

Quoted 24 lines
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/start.S _start_cont:
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/start.S +1 -1
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
--
Quoted 8 lines
This patch presumes stack is right under GD, which is OK. But CONFIG_SYS_MALLOC_F_LEN has not been used by powerpc. Presumption of (CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE) < CONFIG_SYS_INIT_RAM_SIZE
may not be true. Would it be better to check at compiling time to make sure we
have enough init ram for the malloc len?
Yes, good idea; I'll add an appropriate check in v2 of the patch. Maybe something like
#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE + 0x80 > CONFIG_SYS_INIT_RAM_SIZE
#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif

Quoted 9 lines

Quoted 2 lines
to ensure we leave at least a minimum of ~128 byte stack space, too?
I don't think so. We know the size of GD, and we know the size of MALLOC_LEN. But we don't know the depth of stack until we compile it. I would put GD on top,
followed by MALLOC, and leave the rest to stack. I know the DDR driver we use needs way more than 128 bytes for stack.

OK, something like

#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif

then? The stack might end up awfully small, but if there are drivers that need a lot of stack, we can't do a much better test anyway.

Also, from what I see, the GD is on top for all MPC85xx boards (except for T4240QDS, apparently?), because they define either

#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -
GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -
GENERATED_GBL_DATA_SIZE)

and then

#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

So the memory layout is as you said: GD on top, followed by MALLOC, and the rest for the stack.

Best regards,

Mario

Mario Six

author

2016-04-01 08:12 UTC #5 lore raw

PATCH v2 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

In reply to York Sun

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---

v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area

 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 31 insertions(+), 8 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -8

index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,

arch/powerpc/cpu/mpc85xx/start.S +28 -0

index d867e2a..cc4cf5f 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */

include/ppc_asm.tmpl +3 -0

index ba166eb..379c493 100644
@@ -263,12 +263,14 @@
 	b	transfer_to_handler
 
 #define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(SRR0, SRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
 	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

@@ -276,6 +278,7 @@ label:								\
 	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
 
 #define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

--
2.7.0.GIT

York Sun

2016-04-01 17:10 UTC #6 lore raw

PATCH v2 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoted 34 lines · Mario Six

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 31 insertions(+), 8 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1
index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

arch/powerpc/cpu/mpc85xx/cpu_init_early.c void cpu_init_early_f(void *fdt) · line 104

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -7

@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-

I would appreciate a comment here to explain GD had been zeroed by ...

Quoted 8 lines

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
arch/powerpc/cpu/mpc85xx/start.S +0 -0
index d867e2a..cc4cf5f 100644

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1160

Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S +6 -0

@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif

I am not an expert on linking. I wonder if there can be a way to determine the max depth of stack. If we can, a check here would be great. If we can't, we have to live with it.

Quoted 15 lines

arch/powerpc/cpu/mpc85xx/start.S +15 -0

+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1185

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/start.S +7 -0

+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */

I was thinking to add .align 4 before the start of exception vectors.

York

Quoted 31 lines

include/ppc_asm.tmpl +3 -1

index ba166eb..379c493 100644
@@ -263,12 +263,14 @@
 	b	transfer_to_handler
 
 #define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(SRR0, SRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
 	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

@@ -276,6 +278,7 @@ label:								\
 	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
 
 #define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
--

2.7.0.GIT

Mario Six

author

2016-04-04 10:01 UTC #7 lore raw

PATCH v2 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoting York Sun <[email protected]>:

Quoted 39 lines · Mario Six

Quoted 38 lines
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 31 insertions(+), 8 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1
index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/cpu_init_early.c void cpu_init_early_f(void *fdt) · line 104
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -7
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
I would appreciate a comment here to explain GD had been zeroed by ...

Sure, will add in v3.

Quoted 45 lines

Quoted 17 lines

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0

 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,

arch/powerpc/cpu/mpc85xx/start.S +4 -0

index d867e2a..cc4cf5f 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE >

CONFIG_SYS_INIT_RAM_SIZE

arch/powerpc/cpu/mpc85xx/start.S

Quoted 2 lines

arch/powerpc/cpu/mpc85xx/start.S +2 -0
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif

I am not an expert on linking. I wonder if there can be a way to determine the
max depth of stack. If we can, a check here would be great. If we can't, we have
to live with it.

Quoted 19 lines

arch/powerpc/cpu/mpc85xx/start.S +19 -0

+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */

Quoted 9 lines

arch/powerpc/cpu/mpc85xx/start.S
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/start.S +3 -0
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
I was thinking to add .align 4 before the start of exception vectors.

I tried

(quoted diff) +0 -0

b/arch/powerpc/cpu/mpc85xx/start.S
index d867e2a..921c6f5 100644

arch/powerpc/cpu/mpc85xx/start.S +1 -0

@@ -1177,6 +1177,7 @@ _start_cont:
  	/* NOTREACHED - board_init_f() does not return */
 
  #ifndef MINIMAL_SPL
+	.align 4
  	.globl	_start_of_vectors
  _start_of_vectors:

without the aligns in ppc_asm.tmpl, and that crashes the board, I'm afraid.

Quoted 24 lines

include/ppc_asm.tmpl +2 -0

index ba166eb..379c493 100644
@@ -263,12 +263,14 @@
 	b	transfer_to_handler
 
 #define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(SRR0, SRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
 	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

@@ -276,6 +278,7 @@ label:								\
 	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\

Quoted 9 lines

include/ppc_asm.tmpl +1 -1

 #define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
--

2.7.0.GIT

Best regards,

Mario

York Sun

2016-04-04 16:04 UTC #8 lore raw

PATCH v2 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoted 125 lines · Mario Six

Quoting York Sun <[email protected]>:
Quoted 39 lines · Mario Six
Quoted 38 lines
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28 ++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 31 insertions(+), 8 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1
index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c void cpu_init_early_f(void *fdt) · line 104
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -7
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
I would appreciate a comment here to explain GD had been zeroed by ...
Sure, will add in v3.
Quoted 45 lines
Quoted 17 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
arch/powerpc/cpu/mpc85xx/start.S +4 -0
index d867e2a..cc4cf5f 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE >  
CONFIG_SYS_INIT_RAM_SIZE
arch/powerpc/cpu/mpc85xx/start.S
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/start.S +2 -0
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
I am not an expert on linking. I wonder if there can be a way to determine the
max depth of stack. If we can, a check here would be great. If we can't, we have
to live with it.
Quoted 19 lines
arch/powerpc/cpu/mpc85xx/start.S +19 -0
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
Quoted 9 lines
arch/powerpc/cpu/mpc85xx/start.S
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/start.S +3 -0
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
I was thinking to add .align 4 before the start of exception vectors.
I tried
arch/powerpc/cpu/mpc85xx/start.S +1 -0
index d867e2a..921c6f5 100644
@@ -1177,6 +1177,7 @@ _start_cont:
  	/* NOTREACHED - board_init_f() does not return */
 
  #ifndef MINIMAL_SPL
+	.align 4
  	.globl	_start_of_vectors
  _start_of_vectors:
 

Quoted 2 lines

without the aligns in ppc_asm.tmpl, and that crashes the board, I'm afraid.

Actually it is correct to add the alignment in ppc_asm.tmpl. It wasn't correct before but we were lucky to run this far.

York

Mario Six

author

2016-04-05 12:55 UTC #9 lore raw

PATCH v2 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoting York Sun <[email protected]>:

Quoted 127 lines · Mario Six

Quoted 126 lines
Quoting York Sun <[email protected]>:
Quoted 40 lines · Mario Six
Quoted 39 lines
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 --------
 arch/powerpc/cpu/mpc85xx/start.S          | 28  
++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 31 insertions(+), 8 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1
index 235a635..e6e1688 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c void cpu_init_early_f(void *fdt) · line 104
Quoted 7 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -7
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
-
I would appreciate a comment here to explain GD had been zeroed by ...
Sure, will add in v3.
Quoted 45 lines
Quoted 17 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0
 #ifdef CONFIG_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
arch/powerpc/cpu/mpc85xx/start.S +4 -0
index d867e2a..cc4cf5f 100644
@@ -1152,6 +1152,34 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE >
CONFIG_SYS_INIT_RAM_SIZE
arch/powerpc/cpu/mpc85xx/start.S
Quoted 2 lines
arch/powerpc/cpu/mpc85xx/start.S +2 -0
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
I am not an expert on linking. I wonder if there can be a way to determine the
max depth of stack. If we can, a check here would be great. If we can't, we have
to live with it.
Quoted 19 lines
arch/powerpc/cpu/mpc85xx/start.S +19 -0
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
Quoted 9 lines
arch/powerpc/cpu/mpc85xx/start.S
Quoted 6 lines
arch/powerpc/cpu/mpc85xx/start.S +3 -0
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
I was thinking to add .align 4 before the start of exception vectors.
I tried
arch/powerpc/cpu/mpc85xx/start.S +1 -0
index d867e2a..921c6f5 100644
@@ -1177,6 +1177,7 @@ _start_cont:
  	/* NOTREACHED - board_init_f() does not return */
 
  #ifndef MINIMAL_SPL
+	.align 4
  	.globl	_start_of_vectors
  _start_of_vectors:
 

Quoted 8 lines

Quoted 2 lines
without the aligns in ppc_asm.tmpl, and that crashes the board, I'm afraid.
Actually it is correct to add the alignment in ppc_asm.tmpl. It wasn't correct
before but we were lucky to run this far.
York

OK, I'll keep the aligns in ppc_asm.tmpl.

Also, I noticed a mistake on my part: The RAM has to be zeroed in start.S, regardless of whether CONFIG_SYS_MALLOC_F_LEN is defined or not, since I removed the zeroing from cpu_init_early.c. I'll fix that in v3, too.

Best regards,

Mario

Mario Six

author

2016-04-05 13:05 UTC #10 lore raw

PATCH v3 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

In reply to York Sun

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---

v3:
- Add comment regarding gd zeroing
- Unconditionally zero out initial RAM during startup

v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area

 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 +-------
 arch/powerpc/cpu/mpc85xx/start.S          | 30 ++++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 34 insertions(+), 7 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +1 -7

index 235a635..85b4112 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,12 +94,7 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
+	/* gd area was zeroed during startup */
 
 #ifdef CONFIG_QEMU_E500
 	/*

arch/powerpc/cpu/mpc85xx/start.S +30 -0

index d867e2a..82a151a 100644
@@ -1152,6 +1152,36 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+#endif
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */

include/ppc_asm.tmpl +3 -0

index ba166eb..379c493 100644
@@ -263,12 +263,14 @@
 	b	transfer_to_handler
 
 #define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(SRR0, SRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
 	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

@@ -276,6 +278,7 @@ label:								\
 	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
 
 #define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

--
2.7.0.GIT

York Sun

2016-04-06 20:37 UTC #11 lore raw

PATCH v3 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoted 64 lines · Mario Six

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.

Signed-off-by Mario Six <[email protected]>

Cc York Sun <[email protected]>

Cc Simon Glass <[email protected]>

---

v3:
- Add comment regarding gd zeroing
- Unconditionally zero out initial RAM during startup

v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area

 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 +-------
 arch/powerpc/cpu/mpc85xx/start.S          | 30 ++++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 34 insertions(+), 7 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +1 -7

index 235a635..85b4112 100644
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif

@@ -95,12 +94,7 @@ void cpu_init_early_f(void *fdt)
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
+	/* gd area was zeroed during startup */
 
 #ifdef CONFIG_QEMU_E500
 	/*

arch/powerpc/cpu/mpc85xx/start.S +5 -0

index d867e2a..82a151a 100644
@@ -1152,6 +1152,36 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."

arch/powerpc/cpu/mpc85xx/start.S _start_cont: · line 1169

Quoted 10 lines

arch/powerpc/cpu/mpc85xx/start.S +10 -0

+#endif
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+#endif
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+

CONFIG_SYS_INIT_RAM_SIZE is not defined for some platforms, for example P1010RDB, C29XPCIE, BSC9132QDS. I will send out a patch to fix.

York

York Sun

2016-04-06 20:59 UTC #12 lore raw

PATCH v3 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

In reply to Mario Six

Quoted 30 lines · Mario Six

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v3:
- Add comment regarding gd zeroing
- Unconditionally zero out initial RAM during startup
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 +-------
 arch/powerpc/cpu/mpc85xx/start.S          | 30 ++++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 34 insertions(+), 7 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0
index 235a635..85b4112 100644

arch/powerpc/cpu/mpc85xx/cpu_init_early.c void setup_ifc(void) · line 85

Quoted 4 lines

arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1

@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;

This causes a problem. Variable "i" is still used at line 158. I can fix it unless you want to respin the patch.

York

Mario Six

author

2016-04-07 06:06 UTC #13 lore raw

PATCH v3 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

Quoting York Sun <[email protected]>:

Quoted 41 lines · Mario Six

Quoted 32 lines
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v3:
- Add comment regarding gd zeroing
- Unconditionally zero out initial RAM during startup
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 +-------
 arch/powerpc/cpu/mpc85xx/start.S          | 30  
++++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 34 insertions(+), 7 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -0
index 235a635..85b4112 100644
arch/powerpc/cpu/mpc85xx/cpu_init_early.c void setup_ifc(void) · line 85
Quoted 4 lines
arch/powerpc/cpu/mpc85xx/cpu_init_early.c +0 -1
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
This causes a problem. Variable "i" is still used at line 158. I can fix it unless you want to respin the patch.

Quoted 1 line

York

Just fix it; no need to go through the whole procedure again for something like
that :-)

Thanks for all the help and best regards,

Mario

York Sun

2016-04-08 22:47 UTC #14 lore raw

PATCH v3 1/1 mpc85xx: Enable pre-relocation malloc for MPC85xx

In reply to Mario Six

Quoted 20 lines · Mario Six

To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch.
We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S.
Signed-off-by Mario Six <[email protected]>
Cc York Sun <[email protected]>
Cc Simon Glass <[email protected]>
---
v3:
- Add comment regarding gd zeroing
- Unconditionally zero out initial RAM during startup
v2:
- Correct IVOR alignment and remove nop hack
- Add sanity check for length of malloc area

Quoted 5 lines

 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |  8 +-------
 arch/powerpc/cpu/mpc85xx/start.S          | 30 ++++++++++++++++++++++++++++++
 include/ppc_asm.tmpl                      |  3 +++
 3 files changed, 34 insertions(+), 7 deletions(-)

Minor change in subject and minor fix in cpu_init_early.c. Applied to u-boot-mpc85xx master. Awaiting upstream.

Thanks.

York