sunxi: more AXP818 and A83T USB support
Subsystems (7)
cover sunxi: more AXP818 and A83T USB support
Hi everyone,
This series adds more support for axp818 regulators, and USB support for A83T. Normal EHCI/OHCI USB works, and so does OTG host mode. I couldn't get my Cubietruck Plus to work in gadget mode though. No USB device appears on the host end when it enters fastboot.
Patch 1 removes axp818_init() from the header file, as it is undefined and unused.
Patch 2 fixes axp818's DCDC5 default voltage. DCDC5 normally supplies DRAM. This changes the default to match DDR3 DRAM.
Patch 3 adds support for axp818's FLDOs, one of which powers the HSIC PHY.
Patch 4 raises the DCDC1 voltage on h8_homlet_v2 to 3.3V, the default value.
Patch 5 enables and sets DLDO4 to 3.3V on h8_homlet_v2. This powers the AC200 chip, which among other things, is the ethernet PHY.
Patch 6 adds support for the USB PHYs on A83T.
Patch 7 fixes some clock macros related to USB PHYs for A83T.
Patch 8 & 9 add A83T compatible strings to sunxi EHCI & OHCI.
Patch 10 adds support for A83T to musb sunxi glue.
Patch 11 generalizes the VBUS function related macros for AXP PMICs.
Patch 12 adds support for VBUS drive on AXP818.
Patch 13 enables USB Kconfig options in h8_homlet_v2_defconfig.
Patch 14 enables USB Kconfig options in Cubietruck_plus_defconfig.
Patch 15 ~ 17 is the minimal changes needed to enable USB on the A83T boards I have. They are not the same as the kernel changes I will submit, and should not be merged without discussion.
Regards
ChenYu
Chen-Yu Tsai (17):
power: axp818: Remove undefined axp818_init()
power: axp818: Fix DCDC5 default voltage
power: axp818: Add support for FLDOs
sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
sunxi: h8_homlet_v2: Set DLDO4 to 3.3V
sunxi: usb_phy: Add support for A83T USB PHYs
sunxi: clk: Fix USB PHY clock macros for A83T
sunxi: ehci: Add A83T compatible
sunxi: ohci: Add A83T compatible
musb: sunxi: Add support for A83T
sunxi: axp: Generalize register macros for VBUS drive GPIO
sunxi: axp: Support VBUS drive GPIO on AXP818
sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig
sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig [DO NOT MERGE] sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi [DO NOT MERGE] sunxi: Enable USB on Cubietruck Plus [DO NOT MERGE] sunxi: Enable USB nodes for H8Homlet v2
arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++++++++++++++++++++++ arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 ++++++ arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12 ++++++ arch/arm/dts/sun8i-a83t.dtsi | 34 +++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +-- board/sunxi/board.c | 6 +++ configs/Cubietruck_plus_defconfig | 10 ++++- configs/h8_homlet_v2_defconfig | 8 +++- drivers/gpio/axp_gpio.c | 25 ++++++----- drivers/power/Kconfig | 30 +++++++++++++- drivers/power/axp818.c | 34 +++++++++++++++ drivers/usb/host/ehci-sunxi.c | 1 + drivers/usb/host/ohci-sunxi.c | 1 + drivers/usb/musb-new/musb_regs.h | 2 +- include/axp221.h | 8 ++-- include/axp818.h | 9 ++-- include/axp_pmic.h | 1 + include/configs/sun8i.h | 2 + 18 files changed, 222 insertions(+), 27 deletions(-)
Signature · 1 line
2.7.0
RFC PATCH 1/17 power: axp818: Remove undefined axp818_init()
axp818_init() is declared, but never defined.
--- include/axp818.h | 2 -- 1 file changed, 2 deletions(-)
include/axp818.h +0 -2
@@ -53,8 +53,6 @@#define AXP818_ALDO2_CTRL 0x29#define AXP818_ALDO3_CTRL 0x2a -int axp818_init (void ); -/* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
Signature · 1 line
2.7.0
RFC PATCH 2/17 power: axp818: Fix DCDC5 default voltage
In reply to Chen-Yu TsaiDCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3, 1.35V for DDR3L, and 1.2V for LPDDR3.
Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig.
--- configs/h8_homlet_v2_defconfig | 1 - drivers/power/Kconfig | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-)
configs/h8_homlet_v2_defconfig +0 -1
@@ -12,4 +12,3 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_AXP_DCDC1_VOLT=3000 -CONFIG_AXP_DCDC5_VOLT=1500
drivers/power/Kconfig +1 -2
@@ -118,13 +118,12 @@ config AXP_DCDC4_VOLT config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" depends on AXP221_POWER || AXP818_POWER - default 1800 if AXP818_POWER default 1500 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to disable dcdc5. On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V, - 1.8V for A83T. + 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage"
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2.7.0
RFC PATCH 3/17 power: axp818: Add support for FLDOs
In reply to Chen-Yu TsaiThe FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8.
--- board/sunxi/board.c | 6 ++++++ drivers/power/Kconfig | 27 +++++++++++++++++++++++++++ drivers/power/axp818.c | 34 ++++++++++++++++++++++++++++++++++ include/axp818.h | 1 + include/axp_pmic.h | 1 + 5 files changed, 69 insertions(+)
board/sunxi/board.c +6 -0
@@ -486,6 +486,12 @@ void sunxi_board_init(void) power_failed |=axp_set_eldo (2 ,CONFIG_AXP_ELDO2_VOLT ); power_failed |=axp_set_eldo (3 ,CONFIG_AXP_ELDO3_VOLT );#endif + +#ifdef CONFIG_AXP818_POWER + power_failed |=axp_set_fldo (1 ,CONFIG_AXP_FLDO1_VOLT ); + power_failed |=axp_set_fldo (2 ,CONFIG_AXP_FLDO2_VOLT ); + power_failed |=axp_set_fldo (3 ,CONFIG_AXP_FLDO3_VOLT ); +#endif #endif printf ("DRAM:" ); ramsize =sunxi_dram_init ();
drivers/power/Kconfig +27 -0
@@ -238,6 +238,33 @@ config AXP_ELDO3_VOLT 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). +config AXP_FLDO1_VOLT + int "axp pmic fldo1 voltage" + depends on AXP818_POWER + default 0 if MACH_SUN8I_A83T + ---help--- + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. + On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is + used. + +config AXP_FLDO2_VOLT + int "axp pmic eldo2 voltage" + depends on AXP818_POWER + default 900 if MACH_SUN8I_A83T + ---help--- + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + +config AXP_FLDO3_VOLT + int "axp pmic fldo3 voltage" + depends on AXP818_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to + disable fldo3. + config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER
drivers/power/axp818.c +34 -0
@@ -191,6 +191,40 @@ int axp_set_eldo(int eldo_num, unsigned int mvolt) AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); } +int axp_set_fldo (int fldo_num,unsigned int mvolt) +{ +int ret; +u8 cfg; + +if (fldo_num <1 || fldo_num >3 ) +return -EINVAL ; + +if (mvolt ==0 ) +return pmic_bus_clrbits (AXP818_OUTPUT_CTRL3 , +AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num -1 )); + +if (fldo_num <3 ) { + cfg =axp818_mvolt_to_cfg (mvolt,700 ,1450 ,50 ); + ret =pmic_bus_write (AXP818_FLDO1_CTRL + (fldo_num -1 ), cfg); + }else { +/* +* Special case for FLDO3, which is DCDC5 / 2 or FLDOIN / 2 +* Since FLDOIN is unknown, test against DCDC5. +*/ +if (mvolt *2 ==CONFIG_AXP_DCDC5_VOLT ) + ret =pmic_bus_clrbits (AXP818_FLDO2_3_CTRL , +AXP818_FLDO2_3_CTRL_FLDO3_VOL ); +else + ret =pmic_bus_setbits (AXP818_FLDO2_3_CTRL , +AXP818_FLDO2_3_CTRL_FLDO3_VOL ); + } +if (ret) +return ret; + +return pmic_bus_setbits (AXP818_OUTPUT_CTRL3 , +AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num -1 )); +} +int axp_init (void ) {u8 axp_chip_id;
include/axp818.h +1 -0
@@ -41,6 +41,7 @@#define AXP818_ELDO3_CTRL 0x1b#define AXP818_FLDO1_CTRL 0x1c#define AXP818_FLDO2_3_CTRL 0x1d +#define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4)#define AXP818_DCDC1_CTRL 0x20#define AXP818_DCDC2_CTRL 0x21#define AXP818_DCDC3_CTRL 0x22
include/axp_pmic.h +1 -0
@@ -31,6 +31,7 @@ int axp_set_aldo3(unsigned int mvolt);int axp_set_aldo4 (unsigned int mvolt);int axp_set_dldo (int dldo_num,unsigned int mvolt);int axp_set_eldo (int eldo_num,unsigned int mvolt); +int axp_set_fldo (int fldo_num,unsigned int mvolt);int axp_init (void );int axp_get_sid (unsigned int *sid);
Signature · 1 line
2.7.0
RFC PATCH 4/17 sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
In reply to Chen-Yu TsaiThe schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some Allwinner-based boards set it to 3.0V to conserve power. Since the h8_homlet_v2 is a set-top box board with external power, there is no such requirement.
--- configs/h8_homlet_v2_defconfig | 1 - 1 file changed, 1 deletion(-)
configs/h8_homlet_v2_defconfig +0 -1
@@ -11,4 +11,3 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP_DCDC1_VOLT=3000
Signature · 1 line
2.7.0
RFC PATCH 5/17 sunxi: h8_homlet_v2: Set DLDO4 to 3.3V
In reply to Chen-Yu TsaiDLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY / composite video encoder.
--- configs/h8_homlet_v2_defconfig | 1 + 1 file changed, 1 insertion(+)
configs/h8_homlet_v2_defconfig +1 -0
@@ -11,3 +11,4 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_AXP_DLDO4_VOLT=3300
Signature · 1 line
2.7.0
RFC PATCH 6/17 sunxi: usb_phy: Add support for A83T USB PHYs
In reply to Chen-Yu TsaiThe A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC.
--- arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++++++++++++++++++++++++++++++++++++++ include/configs/sun8i.h | 2 ++ 2 files changed, 50 insertions(+)
arch/arm/cpu/armv7/sunxi/usb_phy.c +48 -0
@@ -34,6 +34,16 @@#define REG_PHY_UNK_H3 0x420#define REG_PMU_UNK_H3 0x810 +/* A83T specific control bits for PHY0 */ +#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) +#define SUNXI_PHY_CTL_SIDDQ BIT(3) + +/* A83T HSIC specific bits */ +#define SUNXI_EHCI_HS_FORCE BIT(20) +#define SUNXI_EHCI_CONNECT_DET BIT(17) +#define SUNXI_EHCI_CONNECT_INT BIT(16) +#define SUNXI_EHCI_HSIC BIT(1) + static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus;
@@ -55,6 +65,14 @@ static struct sunxi_usb_phy { .base = SUNXI_USB1_BASE, }, #if CONFIG_SUNXI_USB_PHYS >= 3 +#ifdef CONFIG_MACH_SUN8I_A83T + { + .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | + CCM_USB_CTRL_12M_CLK, + .id = 2, + .base = SUNXI_USB2_BASE, + } +#else { .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .id = 2,
@@ -68,6 +86,7 @@ static struct sunxi_usb_phy { .base = SUNXI_USB3_BASE, }#endif +#endif };static int get_vbus_gpio (int index)
@@ -97,6 +116,7 @@ static int get_id_detect_gpio(int index)return -EINVAL ; } +#ifndef CONFIG_MACH_SUN8I_A83T static void usb_phy_write (struct sunxi_usb_phy *phy,int addr,int data,int len) {
@@ -161,6 +181,7 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)return ; }#endif +#endif static void sunxi_usb_phy_passby (struct sunxi_usb_phy *phy,int enable) {
@@ -174,6 +195,13 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)SUNXI_EHCI_AHB_INCRX_ALIGN_EN |SUNXI_EHCI_ULPI_BYPASS_EN ; +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==2 ) + bits |=SUNXI_EHCI_HS_FORCE | +SUNXI_EHCI_CONNECT_INT | +SUNXI_EHCI_HSIC ; +#endif +if (enable)setbits_le32 (addr, bits);else
@@ -184,9 +212,11 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)void sunxi_usb_phy_enable_squelch_detect (int index,int enable) { +#ifndef CONFIG_MACH_SUN8I_A83T struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];usb_phy_write (phy,0x3c , enable ?0 :2 ,2 ); +#endif }void sunxi_usb_phy_init (int index)
@@ -200,10 +230,21 @@ void sunxi_usb_phy_init(int index)setbits_le32 (&ccm->usb_clk_cfg, phy->usb_rst_mask); +#ifndef CONFIG_MACH_SUN8I_A83T sunxi_usb_phy_config (phy); +#endif if (phy->id !=0 )sunxi_usb_phy_passby (phy,SUNXI_USB_PASSBY_EN ); + +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==0 ) { +setbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_VBUSVLDEXT ); +clrbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_SIDDQ ); + } +#endif }void sunxi_usb_phy_exit (int index)
@@ -218,6 +259,13 @@ void sunxi_usb_phy_exit(int index)if (phy->id !=0 )sunxi_usb_phy_passby (phy, !SUNXI_USB_PASSBY_EN ); +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==0 ) { +setbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_SIDDQ ); + } +#endif +clrbits_le32 (&ccm->usb_clk_cfg, phy->usb_rst_mask); }
include/configs/sun8i.h +2 -0
@@ -20,6 +20,8 @@#ifdef CONFIG_MACH_SUN8I_H3 #define CONFIG_SUNXI_USB_PHYS 4 +#elif definedCONFIG_MACH_SUN8I_A83T +#define CONFIG_SUNXI_USB_PHYS 3#else #define CONFIG_SUNXI_USB_PHYS 2#endif
Signature · 1 line
2.7.0
RFC PATCH 6/17 sunxi: usb_phy: Add support for A83T USB PHYs
Hi,
Quoted 4 lines · Chen-Yu Tsai
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC.
Signed-off-by Chen-Yu Tsai <[email protected]>
Note, I've made some minor changes to this one to reduce the amount of #ifdef-s it introduces.
Regards,
Hans
Quoted 141 lines
--- arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++++++++++++++++++++++++++++++++++++++ include/configs/sun8i.h | 2 ++ 2 files changed, 50 insertions(+)arch/arm/cpu/armv7/sunxi/usb_phy.c +48
-0@@ -34,6 +34,16 @@#define REG_PHY_UNK_H3 0x420#define REG_PMU_UNK_H3 0x810 +/* A83T specific control bits for PHY0 */ +#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) +#define SUNXI_PHY_CTL_SIDDQ BIT(3) + +/* A83T HSIC specific bits */ +#define SUNXI_EHCI_HS_FORCE BIT(20) +#define SUNXI_EHCI_CONNECT_DET BIT(17) +#define SUNXI_EHCI_CONNECT_INT BIT(16) +#define SUNXI_EHCI_HSIC BIT(1) + static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus;@@ -55,6 +65,14 @@ static struct sunxi_usb_phy { .base = SUNXI_USB1_BASE, }, #if CONFIG_SUNXI_USB_PHYS >= 3 +#ifdef CONFIG_MACH_SUN8I_A83T + { + .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | + CCM_USB_CTRL_12M_CLK, + .id = 2, + .base = SUNXI_USB2_BASE, + } +#else { .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .id = 2,@@ -68,6 +86,7 @@ static struct sunxi_usb_phy { .base = SUNXI_USB3_BASE, }#endif +#endif };static int get_vbus_gpio (int index)@@ -97,6 +116,7 @@ static int get_id_detect_gpio(int index)return -EINVAL ; } +#ifndef CONFIG_MACH_SUN8I_A83T static void usb_phy_write (struct sunxi_usb_phy *phy,int addr,int data,int len) {@@ -161,6 +181,7 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)return ; }#endif +#endif static void sunxi_usb_phy_passby (struct sunxi_usb_phy *phy,int enable) {@@ -174,6 +195,13 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)SUNXI_EHCI_AHB_INCRX_ALIGN_EN |SUNXI_EHCI_ULPI_BYPASS_EN ; +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==2 ) + bits |=SUNXI_EHCI_HS_FORCE | +SUNXI_EHCI_CONNECT_INT | +SUNXI_EHCI_HSIC ; +#endif +if (enable)setbits_le32 (addr, bits);else @@ -184,9 +212,11 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)void sunxi_usb_phy_enable_squelch_detect (int index,int enable) { +#ifndef CONFIG_MACH_SUN8I_A83T struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];usb_phy_write (phy,0x3c , enable ?0 :2 ,2 ); +#endif }void sunxi_usb_phy_init (int index)@@ -200,10 +230,21 @@ void sunxi_usb_phy_init(int index)setbits_le32 (&ccm->usb_clk_cfg, phy->usb_rst_mask); +#ifndef CONFIG_MACH_SUN8I_A83T sunxi_usb_phy_config (phy); +#endif if (phy->id !=0 )sunxi_usb_phy_passby (phy,SUNXI_USB_PASSBY_EN ); + +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==0 ) { +setbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_VBUSVLDEXT ); +clrbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_SIDDQ ); + } +#endif }void sunxi_usb_phy_exit (int index)@@ -218,6 +259,13 @@ void sunxi_usb_phy_exit(int index)if (phy->id !=0 )sunxi_usb_phy_passby (phy, !SUNXI_USB_PASSBY_EN ); +#ifdef CONFIG_MACH_SUN8I_A83T +if (phy->id ==0 ) { +setbits_le32 (SUNXI_USB0_BASE +SUNXI_USB_CSR , +SUNXI_PHY_CTL_SIDDQ ); + } +#endif +clrbits_le32 (&ccm->usb_clk_cfg, phy->usb_rst_mask); }include/configs/sun8i.h +2
-0@@ -20,6 +20,8 @@#ifdef CONFIG_MACH_SUN8I_H3 #define CONFIG_SUNXI_USB_PHYS 4 +#elif definedCONFIG_MACH_SUN8I_A83T +#define CONFIG_SUNXI_USB_PHYS 3#else #define CONFIG_SUNXI_USB_PHYS 2#endif
RFC PATCH 7/17 sunxi: clk: Fix USB PHY clock macros for A83T
In reply to Chen-Yu TsaiThe A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI.
--- arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +3 -3
@@ -224,14 +224,14 @@ struct sunxi_ccm_reg {#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_HSIC_RST (0x1 << 2)/* There is no global phy clk gate on sun6i, define as 0 */ #define CCM_USB_CTRL_PHYGATE 0#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10) +#define CCM_USB_CTRL_12M_CLK (0x1 << 11)#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
Signature · 1 line
2.7.0
RFC PATCH 8/17 sunxi: ehci: Add A83T compatible
In reply to Chen-Yu TsaiWe have a separate compatible for almost each SoC. Add one for the A83T.
--- drivers/usb/host/ehci-sunxi.c | 1 + 1 file changed, 1 insertion(+)
drivers/usb/host/ehci-sunxi.c +1 -0
@@ -91,6 +91,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ehci", }, { .compatible = "allwinner,sun7i-a20-ehci", }, { .compatible = "allwinner,sun8i-a23-ehci", }, + { .compatible = "allwinner,sun8i-a83t-ehci", }, { .compatible = "allwinner,sun8i-h3-ehci", }, { .compatible = "allwinner,sun9i-a80-ehci", }, { }
Signature · 1 line
2.7.0
RFC PATCH 9/17 sunxi: ohci: Add A83T compatible
In reply to Chen-Yu TsaiWe have a separate compatible for almost each SoC. Add one for the A83T.
--- drivers/usb/host/ohci-sunxi.c | 1 + 1 file changed, 1 insertion(+)
drivers/usb/host/ohci-sunxi.c +1 -0
@@ -94,6 +94,7 @@ static const struct udevice_id ohci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ohci", }, { .compatible = "allwinner,sun7i-a20-ohci", }, { .compatible = "allwinner,sun8i-a23-ohci", }, + { .compatible = "allwinner,sun8i-a83t-ohci", }, { .compatible = "allwinner,sun8i-h3-ohci", }, { .compatible = "allwinner,sun9i-a80-ohci", }, { }
Signature · 1 line
2.7.0
RFC PATCH 10/17 musb: sunxi: Add support for A83T
In reply to Chen-Yu TsaiLike the Allwinner A33 SoC, the A83T is missing the config register from the musb USB DRD hardware block. Use a known working value for it.
--- drivers/usb/musb-new/musb_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/usb/musb-new/musb_regs.h +1 -1
@@ -434,7 +434,7 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)static inline u8 musb_read_configdata (void __iomem *mbase) { -#ifdef CONFIG_MACH_SUN8I_A33 +#if definedCONFIG_MACH_SUN8I_A33 || definedCONFIG_MACH_SUN8I_A83T /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde ;#else
Signature · 1 line
2.7.0
RFC PATCH 11/17 sunxi: axp: Generalize register macros for VBUS drive GPIO
In reply to Chen-Yu TsaiVBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work.
--- drivers/gpio/axp_gpio.c | 25 ++++++++++++++----------- include/axp221.h | 8 ++++---- 2 files changed, 18 insertions(+), 15 deletions(-)
drivers/gpio/axp_gpio.c +14 -11
@@ -59,10 +59,11 @@ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,u8 reg;switch (pin) { -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +/* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE : - ret =pmic_bus_clrbits (AXP221_MISC_CTRL , -AXP221_MISC_CTRL_N_VBUSEN_FUNC ); + ret =pmic_bus_clrbits (AXP_MISC_CTRL , +AXP_MISC_CTRL_N_VBUSEN_FUNC );if (ret)return ret;
@@ -90,10 +91,11 @@ static int axp_gpio_get_value(struct udevice *dev, unsigned pin) mask =AXP_POWER_STATUS_VBUS_PRESENT ;break ;#endif -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +/* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE : - ret =pmic_bus_read (AXP221_VBUS_IPSOUT , &val); - mask =AXP221_VBUS_IPSOUT_DRIVEBUS ; + ret =pmic_bus_read (AXP_VBUS_IPSOUT , &val); + mask =AXP_VBUS_IPSOUT_DRIVEBUS ;break ;#endif default :
@@ -115,14 +117,15 @@ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)u8 reg;switch (pin) { -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC +/* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE :if (val) -return pmic_bus_setbits (AXP221_VBUS_IPSOUT , -AXP221_VBUS_IPSOUT_DRIVEBUS ); +return pmic_bus_setbits (AXP_VBUS_IPSOUT , +AXP_VBUS_IPSOUT_DRIVEBUS );else -return pmic_bus_clrbits (AXP221_VBUS_IPSOUT , -AXP221_VBUS_IPSOUT_DRIVEBUS ); +return pmic_bus_clrbits (AXP_VBUS_IPSOUT , +AXP_VBUS_IPSOUT_DRIVEBUS );#endif default : reg =axp_get_gpio_ctrl_reg (pin);
include/axp221.h +4 -4
@@ -43,12 +43,8 @@#define AXP221_ALDO1_CTRL 0x28#define AXP221_ALDO2_CTRL 0x29#define AXP221_ALDO3_CTRL 0x2a -#define AXP221_VBUS_IPSOUT 0x30 -#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2)#define AXP221_SHUTDOWN 0x32#define AXP221_SHUTDOWN_POWEROFF (1 << 7) -#define AXP221_MISC_CTRL 0x8f -#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)#define AXP221_PAGE 0xff/* Page 1 addresses */
@@ -57,6 +53,10 @@/* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)#define AXP_GPIO0_CTRL 0x90#define AXP_GPIO1_CTRL 0x92#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00/* Drive pin low */
Signature · 1 line
2.7.0
RFC PATCH 12/17 sunxi: axp: Support VBUS drive GPIO on AXP818
In reply to Chen-Yu TsaiAXP818 supports VBUS drive function, even though the manual does not mention it.
--- include/axp818.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
include/axp818.h +5 -1
@@ -56,7 +56,11 @@/* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)#define AXP_GPIO0_CTRL 0x90#define AXP_GPIO1_CTRL 0x92#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00/* Drive pin low */
Signature · 1 line
2.7.0
RFC PATCH 13/17 sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig
In reply to Chen-Yu TsaiThe h8_homlet_v2 has 2 USB host ports, one connected to the OTG controller, one connected to the EHCI/OHCI pair.
Also provide the card detect pin for MMC.
--- configs/h8_homlet_v2_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
configs/h8_homlet_v2_defconfig +5 -0
@@ -4,6 +4,9 @@ CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_USB0_VBUS_PIN="PL5" +CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -12,3 +15,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y
Signature · 1 line
2.7.0
RFC PATCH 14/17 sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig
In reply to Chen-Yu TsaiThe Cubietruck Plus uses all 3 USB controllers:
- USB OTG functions are provided by the musb USB OTG controller
- Onboard SATA is provied by a USB-SATA bridge connected to USB1
- The USB host ports on the board are provided by an HSIC USB hub
FLDO1 is set to 1.2V for HSIC.
--- configs/Cubietruck_plus_defconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
configs/Cubietruck_plus_defconfig +9 -1
@@ -6,13 +6,21 @@ CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_I2C0_ENABLE=y +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH11" +CONFIG_USB1_VBUS_PIN="PD29" +CONFIG_USB2_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RGMII,MACPWR=SUNXI_GPD(20)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_AXP_FLDO1_VOLT=1200 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y
Signature · 1 line
2.7.0
RFC PATCH 15/17 sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi
In reply to Chen-Yu TsaiThis provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel.
--- arch/arm/dts/sun8i-a83t.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
arch/arm/dts/sun8i-a83t.dtsi +34 -0
@@ -224,5 +224,39 @@ #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; + + usb_otg: usb at 01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + status = "disabled"; + }; + + ehci0: usb at 01c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ohci0: usb at 01c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ehci1: usb at 01c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + r_pio: pinctrl at 01f02c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + }; }; };
Signature · 1 line
2.7.0
RFC PATCH 16/17 sunxi: Enable USB on Cubietruck Plus
In reply to Chen-Yu TsaiThis provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel.
--- arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +12 -0
@@ -58,8 +58,20 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usb_otg { + status = "okay"; +};
Signature · 1 line
2.7.0
RFC PATCH 17/17 sunxi: Enable USB nodes for H8Homlet v2
In reply to Chen-Yu TsaiThis provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel.
--- arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +12 -0
@@ -57,8 +57,20 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usb_otg { + status = "okay"; +};
Signature · 1 line
2.7.0
cover sunxi: more AXP818 and A83T USB support
In reply to Chen-Yu TsaiHi,
Quoted 4 lines · Chen-Yu Tsai
Hi everyone,
This series adds more support for axp818 regulators, and USB support for A83T. Normal EHCI/OHCI USB works, and so does OTG host mode.
Cool, thanks for working on this!
Quoted 2 lines
I couldn't get my Cubietruck Plus to work in gadget mode though. No USB device appears on the host end when it enters fastboot.
Did you change CONFIG_USB_MUSB_HOST=y to CONFIG_USB_MUSB_GADGET=y ? currently we support building either one or the other.
I would certainly welcome patches to make things more dynamic, you could replace the
#ifdef CONFIG_USB_MUSB_HOST
#else
#endif
construct in drivers/usb/musb-new/sunxi.c: sunxi_musb_board_init() with an id=pin check (but only when both CONFIG_USB_MUSB_HOST and CONFIG_USB_MUSB_GADGET are defined, on some boards the port is hardwired for a certain use).
If you take a shot at this, do not forget to also update musb_plat dynamically, currently that is statically initialized depending on CONFIG_USB_MUSB_HOST being defined.
You probably also want to check other places for #ifdef CONFIG_USB_MUSB_HOST / #ifdef CONFIG_USB_MUSB_GADGET, but I'm reasonably sure that defining both at the same time should _mostly_ work, just as long as you only register either the host or gadget part from sunxi_musb_board_init() (which means that the right cable needs to be plugged in before u-boot starts).
###
I've applied patches 1-12 to my tree, and I plan to include these in my next pull-req I've not added 13-14 to give you some time to figure out what todo with the otg, I guess that on the h8_homlet_v2 you can just leave it as CONFIG_USB_MUSB_HOST=y since it is wired to an USB A female connector.
On the cubietruck you may want to make it CONFIG_USB_MUSB_GADGET=y since the most likely use there is using it in gadget mode (for host mode it has normal ports).
About patches 15-17 you've tagged these as "[DO NOT MERGE]" I understand that the devicetree bits which will eventually go upstream will look differently, but as long as the compatible and the base-address will not change, we can pretty merge them in u-boot already, u-boot's dts copy is only used internally and not passed to the kernel.
I will not merge them if you do not want me too, but we could have these minimal nodes for now to get things to work. These can then eventually be replaced with the real kernel dts when that is upstream.
Regards,
Hans
Quoted 78 lines
Patch 1 removes
axp818_init()from the header file, as it is undefined and unused.Patch 2 fixes axp818's DCDC5 default voltage. DCDC5 normally supplies DRAM. This changes the default to match DDR3 DRAM.
Patch 3 adds support for axp818's FLDOs, one of which powers the HSIC PHY.
Patch 4 raises the DCDC1 voltage on
h8_homlet_v2to 3.3V, the default value.Patch 5 enables and sets DLDO4 to 3.3V on
h8_homlet_v2. This powers the AC200 chip, which among other things, is the ethernet PHY.Patch 6 adds support for the USB PHYs on A83T.
Patch 7 fixes some clock macros related to USB PHYs for A83T.
Patch 8 & 9 add A83T compatible strings to sunxi EHCI & OHCI.
Patch 10 adds support for A83T to musb sunxi glue.
Patch 11 generalizes the VBUS function related macros for AXP PMICs.
Patch 12 adds support for VBUS drive on AXP818.
Patch 13 enables USB
Kconfigoptions inh8_homlet_v2_defconfig.Patch 14 enables USB
Kconfigoptions inCubietruck_plus_defconfig.Patch 15 ~ 17 is the minimal changes needed to enable USB on the A83T boards I have. They are not the same as the kernel changes I will submit, and should not be merged without discussion.
Regards
ChenYuChen-Yu Tsai (17):
power: axp818: Remove undefinedaxp818_init()
power: axp818: Fix DCDC5 default voltage
power: axp818: Add support for FLDOs
sunxi:h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
sunxi:h8_homlet_v2: Set DLDO4 to 3.3V
sunxi:usb_phy: Add support for A83T USB PHYs
sunxi: clk: Fix USB PHY clock macros for A83T
sunxi: ehci: Add A83T compatible
sunxi: ohci: Add A83T compatible
musb: sunxi: Add support for A83T
sunxi: axp: Generalize register macros for VBUS drive GPIO
sunxi: axp: Support VBUS drive GPIO on AXP818
sunxi:h8_homlet_v2: Enable USBKconfigoptions in defconfig
sunxi: Cubietruck Plus: Enable USBKconfigoptions in defconfig [DO NOT MERGE] sunxi: Add USB andR_PIOnodes tosun8i-a83t.dtsi[DO NOT MERGE] sunxi: Enable USB on Cubietruck Plus [DO NOT MERGE] sunxi: Enable USB nodes for H8Homlet v2arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++++++++++++++++++++++ arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 ++++++ arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12 ++++++ arch/arm/dts/sun8i-a83t.dtsi | 34 +++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +-- board/sunxi/board.c | 6 +++ configs/Cubietruck_plus_defconfig | 10 ++++- configs/h8_homlet_v2_defconfig | 8 +++- drivers/gpio/axp_gpio.c | 25 ++++++----- drivers/power/Kconfig | 30 +++++++++++++- drivers/power/axp818.c | 34 +++++++++++++++ drivers/usb/host/ehci-sunxi.c | 1 + drivers/usb/host/ohci-sunxi.c | 1 + drivers/usb/musb-new/musb_regs.h | 2 +- include/axp221.h | 8 ++-- include/axp818.h | 9 ++-- include/axp_pmic.h | 1 + include/configs/sun8i.h | 2 + 18 files changed, 222 insertions(+), 27 deletions(-)
cover sunxi: more AXP818 and A83T USB support
Quoted 10 lines · Hans de Goede
Hi,
Quoted 5 lines · Chen-Yu Tsai
Hi everyone,
This series adds more support for axp818 regulators, and USB support for A83T. Normal EHCI/OHCI USB works, and so does OTG host mode.
Quoted 8 lines
Cool, thanks for working on this!
Quoted 2 lines
I couldn't get my Cubietruck Plus to work in gadget mode though. No USB device appears on the host end when it enters fastboot.
Did you change
CONFIG_USB_MUSB_HOST=ytoCONFIG_USB_MUSB_GADGET=y? currently we support building either one or the other.
I did, but I didn't want to send a non-working defconfig. I'm certain musb was compiled in gadget mode, just that nothing was happening.
Quoted 16 lines
I would certainly welcome patches to make things more dynamic, you could replace the
#ifdef
CONFIG_USB_MUSB_HOST
#else
#endifconstruct in
drivers/usb/musb-new/sunxi.c:sunxi_musb_board_init()with an id=pin check (but only when bothCONFIG_USB_MUSB_HOSTandCONFIG_USB_MUSB_GADGETare defined, on some boards the port is hardwired for a certain use).If you take a shot at this, do not forget to also update
musb_platdynamically, currently that is statically initialized depending onCONFIG_USB_MUSB_HOSTbeing defined.
Quoted 7 lines
You probably also want to check other places for #ifdef
CONFIG_USB_MUSB_HOST/ #ifdefCONFIG_USB_MUSB_GADGET, but I'm reasonably sure that defining both at the same time should _mostly_ work, just as long as you only register either the host or gadget part fromsunxi_musb_board_init()(which means that the right cable needs to be plugged in before u-boot starts).
I'm probably not going to spend much more time on this, at least not soon. The host ports working should be enough for normal use.
Quoted 8 lines
###
I've applied patches 1-12 to my tree, and I plan to include these in my next pull-req I've not added 13-14 to give you some time to figure out what todo with the otg, I guess that on the
h8_homlet_v2you can just leave it asCONFIG_USB_MUSB_HOST=ysince it is wired to an USB A female connector.
That is what I intended.
Quoted 3 lines
On the cubietruck you may want to make it
CONFIG_USB_MUSB_GADGET=ysince the most likely use there is using it in gadget mode (for host mode it has normal ports).
Right. Except I couldn't get it to work.
Quoted 9 lines
About patches 15-17 you've tagged these as "[DO NOT MERGE]" I understand that the devicetree bits which will eventually go upstream will look differently, but as long as the compatible and the base-address will not change, we can pretty merge them in u-boot already, u-boot's dts copy is only used internally and not passed to the kernel.
I will not merge them if you do not want me too, but we could have these minimal nodes for now to get things to work. These can then eventually be replaced with the real kernel dts when that is upstream.
If you aren't concerned with them looking different than the kernel ones, I have no problem with merging them. Just wanted to be sure before you do so. :)
Regards
ChenYu
P.S. I'll be at ELC next week.
Quoted 80 lines
Quoted 79 lines
Patch 1 removes
axp818_init()from the header file, as it is undefined and unused.Patch 2 fixes axp818's DCDC5 default voltage. DCDC5 normally supplies DRAM. This changes the default to match DDR3 DRAM.
Patch 3 adds support for axp818's FLDOs, one of which powers the HSIC PHY.
Patch 4 raises the DCDC1 voltage on
h8_homlet_v2to 3.3V, the default value.Patch 5 enables and sets DLDO4 to 3.3V on
h8_homlet_v2. This powers the AC200 chip, which among other things, is the ethernet PHY.Patch 6 adds support for the USB PHYs on A83T.
Patch 7 fixes some clock macros related to USB PHYs for A83T.
Patch 8 & 9 add A83T compatible strings to sunxi EHCI & OHCI.
Patch 10 adds support for A83T to musb sunxi glue.
Patch 11 generalizes the VBUS function related macros for AXP PMICs.
Patch 12 adds support for VBUS drive on AXP818.
Patch 13 enables USB
Kconfigoptions inh8_homlet_v2_defconfig.Patch 14 enables USB
Kconfigoptions inCubietruck_plus_defconfig.Patch 15 ~ 17 is the minimal changes needed to enable USB on the A83T boards I have. They are not the same as the kernel changes I will submit, and should not be merged without discussion.
Regards
ChenYuChen-Yu Tsai (17):
power: axp818: Remove undefinedaxp818_init()
power: axp818: Fix DCDC5 default voltage
power: axp818: Add support for FLDOs
sunxi:h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
sunxi:h8_homlet_v2: Set DLDO4 to 3.3V
sunxi:usb_phy: Add support for A83T USB PHYs
sunxi: clk: Fix USB PHY clock macros for A83T
sunxi: ehci: Add A83T compatible
sunxi: ohci: Add A83T compatible
musb: sunxi: Add support for A83T
sunxi: axp: Generalize register macros for VBUS drive GPIO
sunxi: axp: Support VBUS drive GPIO on AXP818
sunxi:h8_homlet_v2: Enable USBKconfigoptions in defconfig
sunxi: Cubietruck Plus: Enable USBKconfigoptions in defconfig [DO NOT MERGE] sunxi: Add USB andR_PIOnodes tosun8i-a83t.dtsi[DO NOT MERGE] sunxi: Enable USB on Cubietruck Plus [DO NOT MERGE] sunxi: Enable USB nodes for H8Homlet v2arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++++++++++++++++++++++ arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 ++++++ arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12 ++++++ arch/arm/dts/sun8i-a83t.dtsi | 34 +++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +-- board/sunxi/board.c | 6 +++ configs/Cubietruck_plus_defconfig | 10 ++++- configs/h8_homlet_v2_defconfig | 8 +++- drivers/gpio/axp_gpio.c | 25 ++++++----- drivers/power/Kconfig | 30 +++++++++++++- drivers/power/axp818.c | 34 +++++++++++++++ drivers/usb/host/ehci-sunxi.c | 1 + drivers/usb/host/ohci-sunxi.c | 1 + drivers/usb/musb-new/musb_regs.h | 2 +- include/axp221.h | 8 ++-- include/axp818.h | 9 ++-- include/axp_pmic.h | 1 + include/configs/sun8i.h | 2 + 18 files changed, 222 insertions(+), 27 deletions(-)