MIPS: BMIPS: Fix up Kconfig settings

PATCH Applied Kevin Cernekee 3 participants 24 messages Nov 11, 2011 – Nov 12, 2011

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MIPS Broadcom bmips MIPS architecture

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Kevin Cernekee

author

2011-11-11 06:41 UTC #0 lore raw

PATCH v2 1/8 MIPS: BMIPS: Fix up Kconfig settings

Factor out common BMIPS options into "CPU_BMIPS". Add L2 cache for BMIPS5000. Add CPU_MIPS32 to satisfy checks in page.h, r4k_switch.S, tlb-r4k.c, etc.

Signed-off-by Kevin Cernekee <[email protected]>

---
 arch/mips/Kconfig |   34 ++++++++++++++--------------------
 1 files changed, 14 insertions(+), 20 deletions(-)

arch/mips/Kconfig +14 ~~-20~~

index d46f1da..e7587ac 100644
@@ -1413,51 +1413,36 @@ config CPU_CAVIUM_OCTEON
 config CPU_BMIPS3300
 	bool "BMIPS3300"
 	depends on SYS_HAS_CPU_BMIPS3300
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select WEAK_ORDERING
+	select CPU_BMIPS
 	help
 	  Broadcom BMIPS3300 processors.
 
 config CPU_BMIPS4350
 	bool "BMIPS4350"
 	depends on SYS_HAS_CPU_BMIPS4350
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select CPU_BMIPS
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS4350 ("VIPER") processors.
 
 config CPU_BMIPS4380
 	bool "BMIPS4380"
 	depends on SYS_HAS_CPU_BMIPS4380
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select CPU_BMIPS
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS4380 processors.
 
 config CPU_BMIPS5000
 	bool "BMIPS5000"
 	depends on SYS_HAS_CPU_BMIPS5000
-	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_BMIPS
 	select CPU_SUPPORTS_HIGHMEM
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select MIPS_CPU_SCACHE
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS5000 processors.

@@ -1518,6 +1503,15 @@ config CPU_LOONGSON2
 	select CPU_SUPPORTS_64BIT_KERNEL
 	select CPU_SUPPORTS_HIGHMEM
 
+config CPU_BMIPS
+	bool
+	select CPU_MIPS32
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select SWAP_IO_SPACE
+	select WEAK_ORDERING
+
 config SYS_HAS_CPU_LOONGSON2E
 	bool

Signature · 1 line

1.7.6.3

Kevin Cernekee

author

2011-11-11 06:41 UTC #1 lore raw

PATCH v2 2/8 MIPS: Clean up whitespace warning in hazards.h

Use a tab on second and subsequent lines of multiline #if's, for consistency with the next commit.

Signed-off-by Kevin Cernekee <[email protected]>

---
 arch/mips/include/asm/hazards.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

arch/mips/include/asm/hazards.h +2 -2

index 4e33216..8f630e4 100644
@@ -139,8 +139,8 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
-      defined(CONFIG_CPU_R5500)
+	defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
+	defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

Signature · 1 line

1.7.6.3

Ralf Baechle

Applied

2011-11-11 18:03 UTC #2 lore raw

Re: [PATCH V2 2/8] MIPS: Clean up whitespace warning in hazards.h

Queued for 3.3. Thanks,

Ralf

Kevin Cernekee

author

2011-11-11 06:42 UTC #3 lore raw

PATCH v2 3/8 MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

In reply to Kevin Cernekee

Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel images will compile and run.

Signed-off-by Kevin Cernekee <[email protected]>

---
 arch/mips/Makefile              |    1 +
 arch/mips/include/asm/hazards.h |    3 ++-
 arch/mips/include/asm/module.h  |    2 ++
 3 files changed, 5 insertions(+), 1 deletions(-)

arch/mips/Makefile +1 -0

index 9b4cb00..ae5cfa7 100644
@@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
+cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

arch/mips/include/asm/hazards.h +2 -1

index 8f630e4..b4c20e4 100644
@@ -87,7 +87,8 @@ do {									\
 	: "=r" (tmp));							\
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
+#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
+	defined(CONFIG_CPU_BMIPS)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to

arch/mips/include/asm/module.h +2 -0

index bc01a02..c392df2 100644
@@ -120,6 +120,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR
 #define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_BMIPS
+#define MODULE_PROC_FAMILY "BMIPS "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif

Signature · 1 line

1.7.6.3

Ralf Baechle

2011-11-11 12:58 UTC #4 lore raw

Re: [PATCH V2 3/8] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

arch/mips/Makefile ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))

Quoted 3 lines · Kevin Cernekee

arch/mips/Makefile +2 -0

+cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
 
+#define MODULE_PROC_FAMILY "BMIPS "

If BMIPS is just a MIPS32 with no relevant extensions to the instruction set, why don't you just call it a MIPS32 processor and use something like CPU_MIPS32_R2?

It's small things like that which can sometimes avoid many unnecessary recompilations which really saves times when rebuilding all defconfigs on a way to slow machine :)

Ralf

Kevin Cernekee

author

2011-11-11 16:57 UTC #5 lore raw

Re: [PATCH V2 3/8] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

Quoted 7 lines · Ralf Baechle

If BMIPS is just a MIPS32 with no relevant extensions to the instruction set, why don't you just call it a MIPS32 processor and use something like CPU_MIPS32_R2?
It's small things like that which can sometimes avoid many unnecessary recompilations which really saves times when rebuilding all defconfigs on a way to slow machine :)

At a high level, the CONFIG_CPU_BMIPS* settings are used to make compile-time decisions that differentiate BMIPS from standard MIPS32, and that differentiate the BMIPS CPUs from one another.

Present and future uses include:

Figuring out which set of proprietary BMIPS CP0 registers / core registers to use, where they are located, bit fields, etc.

Per-BMIPS SMP operations and capabilities

Per-BMIPS performance counter access

cpu-feature-overrides.h

HIGHMEM, SMP, and other basic features

eDSP instruction set (different on each BMIPS, and BMIPS-specific)

Cache architecture and BMIPS-specific cache optimizations

Some of these could potentially be replaced with a "switch (current_cpu_type())" but others are a little trickier (i.e. they show up in low-level PM resume code, exception vectors, or other sensitive places).

It is true that BMIPS uses -mips32 for compilation. If the criteria for adding a new CONFIG_CPU_* choice is whether it selects a new instruction set or compilation flags, do you think it makes sense to remove BMIPS* from the "CPU selection" menu, enable CONFIG_CPU_MIPS32_R1 for BMIPS platforms, and call our options something different? e.g.

CONFIG_BMIPS
CONFIG_BMIPS3300
CONFIG_BMIPS4350
CONFIG_BMIPS4380
CONFIG_BMIPS5000

Ralf Baechle

2011-11-11 17:20 UTC #6 lore raw

Re: [PATCH V2 3/8] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

Quoted 36 lines · Kevin Cernekee

At a high level, the CONFIG_CPU_BMIPS* settings are used to make compile-time decisions that differentiate BMIPS from standard MIPS32, and that differentiate the BMIPS CPUs from one another.
Present and future uses include:
Figuring out which set of proprietary BMIPS CP0 registers / core registers to use, where they are located, bit fields, etc.
Per-BMIPS SMP operations and capabilities
Per-BMIPS performance counter access
cpu-feature-overrides.h
HIGHMEM, SMP, and other basic features
eDSP instruction set (different on each BMIPS, and BMIPS-specific)
Cache architecture and BMIPS-specific cache optimizations
Some of these could potentially be replaced with a "switch (current_cpu_type())" but others are a little trickier (i.e. they show up in low-level PM resume code, exception vectors, or other sensitive places).
It is true that BMIPS uses -mips32 for compilation. If the criteria for adding a new CONFIG_CPU_* choice is whether it selects a new instruction set or compilation flags, do you think it makes sense to remove BMIPS* from the "CPU selection" menu, enable CONFIG_CPU_MIPS32_R1 for BMIPS platforms, and call our options something different? e.g.

Quoted 5 lines

CONFIG_BMIPS
CONFIG_BMIPS3300
CONFIG_BMIPS4350
CONFIG_BMIPS4380
CONFIG_BMIPS5000

Fair enough; sorting that kind of thing will need some effort across the tree at some point in the future.

I notice there seems to be only CPU core support; are you planning to submit board support code as well?

Ralf

Florian Fainelli

2011-11-12 14:11 UTC #7 lore raw

Re: [PATCH V2 3/8] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

Quoted 43 lines · Ralf Baechle

Quoted 36 lines · Kevin Cernekee
At a high level, the CONFIG_CPU_BMIPS* settings are used to make compile-time decisions that differentiate BMIPS from standard MIPS32, and that differentiate the BMIPS CPUs from one another.
Present and future uses include:
Figuring out which set of proprietary BMIPS CP0 registers / core registers to use, where they are located, bit fields, etc.
Per-BMIPS SMP operations and capabilities
Per-BMIPS performance counter access
cpu-feature-overrides.h
HIGHMEM, SMP, and other basic features
eDSP instruction set (different on each BMIPS, and BMIPS-specific)
Cache architecture and BMIPS-specific cache optimizations
Some of these could potentially be replaced with a "switch (current_cpu_type())" but others are a little trickier (i.e. they show up in low-level PM resume code, exception vectors, or other sensitive places).
It is true that BMIPS uses -mips32 for compilation. If the criteria for adding a new CONFIG_CPU_* choice is whether it selects a new instruction set or compilation flags, do you think it makes sense to remove BMIPS* from the "CPU selection" menu, enable CONFIG_CPU_MIPS32_R1 for BMIPS platforms, and call our options something different? e.g.
Quoted 5 lines
CONFIG_BMIPS
CONFIG_BMIPS3300
CONFIG_BMIPS4350
CONFIG_BMIPS4380
CONFIG_BMIPS5000

Quoted 5 lines

Fair enough; sorting that kind of thing will need some effort across the tree at some point in the future.
I notice there seems to be only CPU core support; are you planning to submit board support code as well?

BCM63xx and BCM47xx use BMIPS CPUs and can already take advantage of this core CPU support code.

Signature · 1 line

Florian

Ralf Baechle

Applied

2011-11-11 18:04 UTC #8 lore raw

Re: [PATCH V2 3/8] MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPS

In reply to Kevin Cernekee

Queued for 3.3. Thanks,

Ral

Kevin Cernekee

author

2011-11-11 06:42 UTC #9 lore raw

PATCH v2 4/8 MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operations

In reply to Kevin Cernekee

Several BMIPS-specific CP0 registers are used for SMP boot and other operations.

Signed-off-by Kevin Cernekee <[email protected]>

---
 arch/mips/include/asm/mipsregs.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

arch/mips/include/asm/mipsregs.h +8 -1

index 2ea7b81..7f87d82 100644
@@ -1106,7 +1106,7 @@ do {									\
 #define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
 
-/* BMIPS4380 */
+/* BMIPS43xx */
 #define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)

@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
 
 #endif /* !__ASSEMBLY__ */

Signature · 1 line

1.7.6.3

Ralf Baechle

Applied

2011-11-11 18:04 UTC #10 lore raw

Re: [PATCH V2 4/8] MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operations

Queued for 3.3. Thanks,

Ral

Kevin Cernekee

author

2011-11-11 06:42 UTC #11 lore raw

PATCH v2 5/8 MIPS: BMIPS: Introduce bmips.h

In reply to Kevin Cernekee

bmips.h contains BMIPS definitions that are useful for SMP, vector relocation, performance counters, etc.

Signed-off-by Kevin Cernekee <[email protected]>

---

V2:

Rewrite all of bmips_{read,write}_zscm_reg in assembly.

Add bmips_cpu_offset.

 arch/mips/include/asm/bmips.h |  109 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/bmips.h

arch/mips/include/asm/bmips.h new file +109 -0

new file mode 100644
index 0000000..1ec4a6e
@@ -0,0 +1,109 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee ([email protected])
+ *
+ * Definitions for BMIPS processors
+ */
+#ifndef _ASM_BMIPS_H
+#define _ASM_BMIPS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+
+/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
+#define BMIPS_GET_CBR()			((void __iomem *)(CKSEG1 | \
+					 (unsigned long) \
+					 ((read_c0_brcm_cbr() >> 18) << 18)))
+
+#define BMIPS_RAC_CONFIG		0x00000000
+#define BMIPS_RAC_ADDRESS_RANGE		0x00000004
+#define BMIPS_RAC_CONFIG_1		0x00000008
+#define BMIPS_L2_CONFIG			0x0000000c
+#define BMIPS_LMB_CONTROL		0x0000001c
+#define BMIPS_SYSTEM_BASE		0x00000020
+#define BMIPS_PERF_GLOBAL_CONTROL	0x00020000
+#define BMIPS_PERF_CONTROL_0		0x00020004
+#define BMIPS_PERF_CONTROL_1		0x00020008
+#define BMIPS_PERF_COUNTER_0		0x00020010
+#define BMIPS_PERF_COUNTER_1		0x00020014
+#define BMIPS_PERF_COUNTER_2		0x00020018
+#define BMIPS_PERF_COUNTER_3		0x0002001c
+#define BMIPS_RELO_VECTOR_CONTROL_0	0x00030000
+#define BMIPS_RELO_VECTOR_CONTROL_1	0x00038000
+
+#define BMIPS_NMI_RESET_VEC		0x80000000
+#define BMIPS_WARM_RESTART_VEC		0x80000380
+
+#define ZSCM_REG_BASE			0x97000000
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/cpumask.h>
+#include <asm/r4kcache.h>
+
+extern struct plat_smp_ops bmips_smp_ops;
+extern char bmips_reset_nmi_vec;
+extern char bmips_reset_nmi_vec_end;
+extern char bmips_smp_movevec;
+extern char bmips_smp_int_vec;
+extern char bmips_smp_int_vec_end;
+
+extern int bmips_smp_enabled;
+extern int bmips_cpu_offset;
+extern cpumask_t bmips_booted_mask;
+
+extern void bmips_ebase_setup(void);
+extern asmlinkage void plat_wired_tlb_setup(void);
+
+static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
+{
+	unsigned long ret;
+
+	__asm__ __volatile__(
+		".set push\n"
+		".set noreorder\n"
+		"cache %1, 0(%2)\n"
+		"sync\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"mfc0 %0, $28, 3\n"
+		"ssnop\n"
+		".set pop\n"
+		: "=&r" (ret)
+		: "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
+		: "memory");
+	return ret;
+}
+
+static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
+{
+	__asm__ __volatile__(
+		".set push\n"
+		".set noreorder\n"
+		"mtc0 %0, $28, 3\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		"cache %1, 0(%2)\n"
+		"ssnop\n"
+		"ssnop\n"
+		"ssnop\n"
+		: /* no outputs */
+		: "r" (data),
+		  "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
+		: "memory");
+}
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* _ASM_BMIPS_H */

Signature · 1 line

1.7.6.3

Ralf Baechle

2011-11-11 13:32 UTC #12 lore raw

Re: [PATCH V2 5/8] MIPS: BMIPS: Introduce bmips.h

arch/mips/include/asm/bmips.h line 72

Quoted 6 lines · Kevin Cernekee

arch/mips/include/asm/bmips.h new file +6 -0

+	__asm__ __volatile__(
+		".set push\n"
+		".set noreorder\n"
+		"cache %1, 0(%2)\n"
+		"sync\n"
+		"ssnop\n"

Ssnop was added relatively recently to gas and the kernel supports building with much older toolchains. To get around this <asm/hazard.h> defines a _ssnop macro.

Ralf

Ralf Baechle

2011-11-11 18:05 UTC #13 lore raw

Re: [PATCH V2 5/8] MIPS: BMIPS: Introduce bmips.h

In reply to Kevin Cernekee

Dropped; using the replacement you sent.

Thanks,

Ralf

Kevin Cernekee

author

2011-11-11 06:43 UTC #14 lore raw

PATCH v2 6/8 MIPS: Add NMI notifier

In reply to Kevin Cernekee

Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions.

Signed-off-by Kevin Cernekee <[email protected]>

---

V2:

Use a raw notifier instead of a function pointer for NMI events.

 arch/mips/include/asm/traps.h |   12 ++++++++++++
 arch/mips/kernel/traps.c      |    9 +++++++++
 2 files changed, 21 insertions(+), 0 deletions(-)

arch/mips/include/asm/traps.h +12 -0

index 90ff2f4..4edab87 100644
@@ -25,4 +25,16 @@ extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
 
+extern int register_nmi_notifier(struct notifier_block *nb);
+
+#define nmi_notifier(fn, pri)						\
+({									\
+	static struct notifier_block fn##_nb = {			\
+		.notifier_call = fn,					\
+		.priority = pri						\
+	};								\
+									\
+	register_nmi_notifier(&fn##_nb);				\
+})
+
 #endif /* _ASM_TRAPS_H */

arch/mips/kernel/traps.c +9 -0

index 5c8a49d..33945aa 100644
@@ -1339,9 +1339,18 @@ void ejtag_exception_handler(struct pt_regs *regs)
 
 /*
  * NMI exception handler.
+ * No lock; only written during early bootup by CPU 0.
  */
+static RAW_NOTIFIER_HEAD(nmi_chain);
+
+int register_nmi_notifier(struct notifier_block *nb)
+{
+	return raw_notifier_chain_register(&nmi_chain, nb);
+}
+
 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
 {
+	raw_notifier_call_chain(&nmi_chain, 0, regs);
 	bust_spinlocks(1);
 	printk("NMI taken!!!!\n");
 	die("NMI", regs);

Signature · 1 line

1.7.6.3

Ralf Baechle

2011-11-11 13:35 UTC #15 lore raw

Re: [PATCH V2 6/8] MIPS: Add NMI notifier

Quoted 1 line · Kevin Cernekee

+ * No lock; only written during early bootup by CPU 0.

And if that wasn't the case, an NMI might come at any time, even with the lock already being held which would result in a deadlock. NMIs are nasty stuff - and on MIPS they're just slightly more evil.

Ralf

Ralf Baechle

Applied

2011-11-11 18:05 UTC #16 lore raw

Re: [PATCH V2 6/8] MIPS: Add NMI notifier

In reply to Kevin Cernekee

Queued for 3.3. Thanks,

Ralf

Kevin Cernekee

author

2011-11-11 06:43 UTC #17 lore raw

PATCH v2 7/8 MIPS: Add board_ebase_setup()

In reply to Kevin Cernekee

Some systems need to relocate the MIPS exception vector base during trap initialization. Add a hook to make this possible.

Signed-off-by Kevin Cernekee <[email protected]>

---
 arch/mips/include/asm/traps.h |    1 +
 arch/mips/kernel/traps.c      |    3 +++
 2 files changed, 4 insertions(+), 0 deletions(-)

arch/mips/include/asm/traps.h +1 -0

index 4edab87..ff74aec 100644
@@ -24,6 +24,7 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
+extern void (*board_ebase_setup)(void);
 
 extern int register_nmi_notifier(struct notifier_block *nb);

arch/mips/kernel/traps.c +3 -0

index 33945aa..c18dfd4 100644
@@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 void (*board_nmi_handler_setup)(void);
 void (*board_ejtag_handler_setup)(void);
 void (*board_bind_eic_interrupt)(int irq, int regset);
+void (*board_ebase_setup)(void);
 
 
 static void show_raw_backtrace(unsigned long reg29)

@@ -1691,6 +1692,8 @@ void __init trap_init(void)
 			ebase += (read_c0_ebase() & 0x3ffff000);
 	}
 
+	if (board_ebase_setup)
+		board_ebase_setup();
 	per_cpu_trap_init();
 
 	/*

Signature · 1 line

1.7.6.3

Ralf Baechle

Applied

2011-11-11 18:05 UTC #18 lore raw

Re: [PATCH V2 7/8] MIPS: Add board_ebase_setup()

Queued for 3.3. Thanks,

Ralf

Kevin Cernekee

author

2011-11-11 06:44 UTC #19 lore raw

PATCH v2 8/8 MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000

In reply to Kevin Cernekee

Initial commit of BMIPS SMP support code. Smoke-tested on a variety of BMIPS4350, BMIPS4380, and BMIPS5000 platforms.

Signed-off-by Kevin Cernekee <[email protected]>

---

V2:

Move XKS01 option into this patch.

Remove dependency on local_flush_tlb_all_mm(), per the discussion earlier this week.

Allow platform-configurable variables to be accessed in !CONFIG_SMP mode, so the platform code does not need unnecessary #ifdefs.

Remove the code that clears the FPU registers.

Fix the jump to the NMI vector.

Add bmips_cpu_offset.

 arch/mips/Kconfig            |    3 +
 arch/mips/kernel/Makefile    |    1 +
 arch/mips/kernel/bmips_vec.S |  254 +++++++++++++++++++++++
 arch/mips/kernel/smp-bmips.c |  457 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 715 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/kernel/bmips_vec.S
 create mode 100644 arch/mips/kernel/smp-bmips.c

arch/mips/Kconfig +3 -0

index e7587ac..9c4a610 100644
@@ -1986,6 +1986,9 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
 	bool
 
+config XKS01
+	bool
+
 #
 # Vectored interrupt mode is an R2 feature
 #

arch/mips/kernel/Makefile +1 -0

index 1a96618..0198321 100644
@@ -58,6 +58,7 @@ obj-$(CONFIG_CPU_XLR)		+= r4k_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP_UP)		+= smp-up.o
+obj-$(CONFIG_CPU_BMIPS)		+= smp-bmips.o bmips_vec.o
 
 obj-$(CONFIG_MIPS_MT)		+= mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o

arch/mips/kernel/bmips_vec.S new file +254 -0

254 lines not on this page · raw message

arch/mips/kernel/smp-bmips.c new file +457 -0

457 lines not on this page · raw message

Signature · 1 line

1.7.6.3

Ralf Baechle

2011-11-11 18:06 UTC #20 lore raw

Re: [PATCH V2 8/8] MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000

Dropped; using the replacement you sent.

Ralf

Florian Fainelli

2011-11-12 14:31 UTC #21 lore raw

Re: [PATCH V2 8/8] MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000

In reply to Kevin Cernekee

Hello Kevin,

Quoted 13 lines · Kevin Cernekee

Initial commit of BMIPS SMP support code. Smoke-tested on a variety of BMIPS4350, BMIPS4380, and BMIPS5000 platforms.
Signed-off-by Kevin Cernekee <[email protected]>
---
V2:
Move XKS01 option into this patch.
Remove dependency on local_flush_tlb_all_mm(), per the discussion earlier this week.

Quoted 8 lines

Allow platform-configurable variables to be accessed in !CONFIG_SMP mode, so the platform code does not need unnecessary #ifdefs.
Remove the code that clears the FPU registers.
Fix the jump to the NMI vector.
Add bmips_cpu_offset.

I have two questions regarding this patchset:

- considering that BMIPS4350 has a shared TLB, is it still working fine? I must say that I have not yet tested on e.g: BCM6358

- there a couple of places in the code where we have:

#if defined (CONFIG_BMIPS_4350) || defined (CONFIG_BMIPS_4380)
... do something
#elif defined(CONFIG_BMIPS_4380)

can we turn this into a #if BMIPS43xx case .. #endif #if BMIPS5000 ... #endif to allow a single image supporting both BMIPS43xx and BMIPS5000?

By the time we are initializing the CPUs for SMP, we should be able to use runtime checks on the BMIPS CPU variant.

Thanks.

Signature · 1 line

Florian

Kevin Cernekee

author

2011-11-12 16:07 UTC #22 lore raw

Re: [PATCH V2 8/8] MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000

Quoted 2 lines · Florian Fainelli

- considering that BMIPS4350 has a shared TLB, is it still working fine? I must say that I have not yet tested on e.g: BCM6358

BCM6368 (which I did test) has a private TLB for each thread. I have not tested any of the shared TLB chips.

It is possible that more work will be required to cover the shared TLB case.

Quoted 8 lines

- there a couple of places in the code where we have:
#if defined (CONFIG_BMIPS_4350) || defined (CONFIG_BMIPS_4380) ... do something
#elif defined(CONFIG_BMIPS_4380)
can we turn this into a #if BMIPS43xx case .. #endif #if BMIPS5000 ... #endif to allow a single image supporting both BMIPS43xx and BMIPS5000?

Although it would be easy to check current_cpu_type() for the cases in smp-bmips.c, there are other decisions (not in this patchset) that are harder to make at runtime. One obvious case is cpu-feature-overrides.h; other cases include low-level code sequences in the exception vectors, power management standby/resume/reentry assembly code, HIGHMEM and cache configuration, memory map, etc.

Side note: one of Ralf's earlier comments on this patch was a request to use pr_info() instead of printk(). This somehow fell off my TODO list. I will fix it and submit V4 later today.

Ralf Baechle

Applied

2011-11-11 18:03 UTC #23 lore raw

In reply to Kevin Cernekee

Queued for 3.3. Thanks,

Ralf