spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

PATCH New Stefan Roese 3 participants 6 messages Feb 12, 2016 – Apr 6, 2016

Subsystems (2)

Arm (32-bit) SPI

lore

Share & tools

lore

Stefan Roese

author

2016-02-12 12:45 UTC #0 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
 drivers/spi/kirkwood_spi.c            |  6 ++++++
 2 files changed, 18 insertions(+), 5 deletions(-)

arch/arm/include/asm/arch-mvebu/spi.h +12 -5

index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
 #define SCK_MPP10	(1 << 1)
 #define MISO_MPP11	(1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT		(1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT		2	/* chip select shift */
+#define KWSPI_CS_MASK		0x7	/* chip select mask */
+
+/* Configuration Register */
 #define KWSPI_CLKPRESCL_MASK	0x1f
 #define KWSPI_CLKPRESCL_MIN	0x12
-#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
 #define KWSPI_XFERLEN_1BYTE	0
 #define KWSPI_XFERLEN_2BYTE	(1 << 5)
 #define KWSPI_XFERLEN_MASK	(1 << 5)

@@ -47,6 +49,11 @@ struct kwspi_registers {
 #define KWSPI_ADRLEN_3BYTE	(2 << 8)
 #define KWSPI_ADRLEN_4BYTE	(3 << 8)
 #define KWSPI_ADRLEN_MASK	(3 << 8)
+
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+
 #define KWSPI_TIMEOUT		10000
 
 #endif /* __KW_SPI_H__ */

drivers/spi/kirkwood_spi.c +6 -0

index 7890796..fa30be4 100644
@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct udevice *bus = dev->parent;
 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
 
+#ifdef CONFIG_ARCH_MVEBU
+	clrsetbits_le32(&plat->spireg->ctrl,
+			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+			spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif
+
 	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
 }

Signature · 1 line

2.7.1

Jagan Teki

2016-02-12 20:27 UTC #1 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Hi Stefan,

Quoted 57 lines · Stefan Roese

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
 drivers/spi/kirkwood_spi.c            |  6 ++++++
 2 files changed, 18 insertions(+), 5 deletions(-)

arch/arm/include/asm/arch-mvebu/spi.h +12 -5

index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
 #define SCK_MPP10      (1 << 1)
 #define MISO_MPP11     (1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT          (1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT         2       /* chip select shift */
+#define KWSPI_CS_MASK          0x7     /* chip select mask */
+
+/* Configuration Register */
 #define KWSPI_CLKPRESCL_MASK   0x1f
 #define KWSPI_CLKPRESCL_MIN    0x12
-#define KWSPI_CSN_ACT          1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready irq */
 #define KWSPI_XFERLEN_1BYTE    0
 #define KWSPI_XFERLEN_2BYTE    (1 << 5)
 #define KWSPI_XFERLEN_MASK     (1 << 5)

@@ -47,6 +49,11 @@ struct kwspi_registers {
 #define KWSPI_ADRLEN_3BYTE     (2 << 8)
 #define KWSPI_ADRLEN_4BYTE     (3 << 8)
 #define KWSPI_ADRLEN_MASK      (3 << 8)
+
+#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready irq */
+
 #define KWSPI_TIMEOUT          10000
 
 #endif /* __KW_SPI_H__ */

drivers/spi/kirkwood_spi.c +0 -0

index 7890796..fa30be4 100644

drivers/spi/kirkwood_spi.c static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, · line 287

Quoted 8 lines

drivers/spi/kirkwood_spi.c +5 -0

@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
        struct udevice *bus = dev->parent;
        struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
 
+#ifdef CONFIG_ARCH_MVEBU
+       clrsetbits_le32(&plat->spireg->ctrl,
+                       KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+                       spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif

This looks clearing a desired cs from 'sf probe' why is this need here? I think we can do the desired cs activate or deactivate through existing spi_cs_activate/deactivate functions itself.

thanks!

Signature · 1 line

Jagan.

Stefan Roese

author

2016-03-23 14:36 UTC #2 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Hi Jagan,

please excuse the long delay here. Some comments below.

Quoted 61 lines · Jagan Teki

Quoted 60 lines · Stefan Roese

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Jagan Teki <[email protected]>

---
  arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
  drivers/spi/kirkwood_spi.c            |  6 ++++++
  2 files changed, 18 insertions(+), 5 deletions(-)

arch/arm/include/asm/arch-mvebu/spi.h +12 -5

index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
  #define SCK_MPP10      (1 << 1)
  #define MISO_MPP11     (1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT          (1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT         2       /* chip select shift */
+#define KWSPI_CS_MASK          0x7     /* chip select mask */
+
+/* Configuration Register */
  #define KWSPI_CLKPRESCL_MASK   0x1f
  #define KWSPI_CLKPRESCL_MIN    0x12
-#define KWSPI_CSN_ACT          1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready irq */
  #define KWSPI_XFERLEN_1BYTE    0
  #define KWSPI_XFERLEN_2BYTE    (1 << 5)
  #define KWSPI_XFERLEN_MASK     (1 << 5)

@@ -47,6 +49,11 @@ struct kwspi_registers {
  #define KWSPI_ADRLEN_3BYTE     (2 << 8)
  #define KWSPI_ADRLEN_4BYTE     (3 << 8)
  #define KWSPI_ADRLEN_MASK      (3 << 8)
+
+#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready irq */
+
  #define KWSPI_TIMEOUT          10000
 
  #endif /* __KW_SPI_H__ */

drivers/spi/kirkwood_spi.c +0 -0

index 7890796..fa30be4 100644
@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
         struct udevice *bus = dev->parent;
         struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

Quoted 8 lines

drivers/spi/kirkwood_spi.c static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, · line 287
Quoted 5 lines
drivers/spi/kirkwood_spi.c +5 -0
+#ifdef CONFIG_ARCH_MVEBU
+       clrsetbits_le32(&plat->spireg->ctrl,
+                       KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+                       spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif
This looks clearing a desired cs from 'sf probe' why is this need here?

Its not clearing a CS but configuring the CS number in the CTRL register. This configured CS number will get enabled or disabled exactly the same way as when its zero (without this patch) in the existing spi_cs_activate/deactivate functions

Quoted 2 lines

I think we can do the desired cs activate or deactivate through existing spi_cs_activate/deactivate functions itself.

This is exactly what this patch does. The CS number is configured with the clrsetbits_le32() call above. And activated / deactivated in the existing functions.

Or do you mean something else?

Thanks,
Stefan

Stefan Roese

author

2016-04-05 06:02 UTC #3 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Hi Jagan,

Quoted 87 lines · Stefan Roese

Hi Jagan,
please excuse the long delay here. Some comments below.
Quoted 68 lines · Jagan Teki
Quoted 67 lines · Stefan Roese
Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.
The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.
Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>
---
  arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
  drivers/spi/kirkwood_spi.c            |  6 ++++++
  2 files changed, 18 insertions(+), 5 deletions(-)
arch/arm/include/asm/arch-mvebu/spi.h +2 -0
index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
  #define SCK_MPP10      (1 << 1)
  #define MISO_MPP11     (1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT          (1 << 0) /* Activates serial memory
interface */
arch/arm/include/asm/arch-mvebu/spi.h +5 -1
+#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT         2       /* chip select shift */
+#define KWSPI_CS_MASK          0x7     /* chip select mask */
+
+/* Configuration Register */
  #define KWSPI_CLKPRESCL_MASK   0x1f
  #define KWSPI_CLKPRESCL_MIN    0x12
-#define KWSPI_CSN_ACT          1 /* Activates serial memory
interface */
arch/arm/include/asm/arch-mvebu/spi.h +0 -4
-#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready
irq */
  #define KWSPI_XFERLEN_1BYTE    0
  #define KWSPI_XFERLEN_2BYTE    (1 << 5)
  #define KWSPI_XFERLEN_MASK     (1 << 5)
arch/arm/include/asm/arch-mvebu/spi.h +4 -0
@@ -47,6 +49,11 @@ struct kwspi_registers {
  #define KWSPI_ADRLEN_3BYTE     (2 << 8)
  #define KWSPI_ADRLEN_4BYTE     (3 << 8)
  #define KWSPI_ADRLEN_MASK      (3 << 8)
+
+#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready
irq */
arch/arm/include/asm/arch-mvebu/spi.h +1 -0
+
  #define KWSPI_TIMEOUT          10000
 
  #endif /* __KW_SPI_H__ */
drivers/spi/kirkwood_spi.c +0 -0
index 7890796..fa30be4 100644
@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev,
 unsigned int bitlen,
         struct udevice *bus = dev->parent;
         struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
 
Quoted 8 lines
drivers/spi/kirkwood_spi.c static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, · line 287
Quoted 5 lines
drivers/spi/kirkwood_spi.c +5 -0
+#ifdef CONFIG_ARCH_MVEBU
+       clrsetbits_le32(&plat->spireg->ctrl,
+                       KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+                       spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif
This looks clearing a desired cs from 'sf probe' why is this need here?
Its not clearing a CS but configuring the CS number in the CTRL register. This configured CS number will get enabled or disabled exactly the same way as when its zero (without this patch) in the existing spi_cs_activate/deactivate functions

Quoted 8 lines

Quoted 2 lines
I think we can do the desired cs activate or deactivate through existing spi_cs_activate/deactivate functions itself.
This is exactly what this patch does. The CS number is configured with the clrsetbits_le32() call above. And activated / deactivated in the existing functions.
Or do you mean something else?

Any updates on this? I would like to have this multiple CS support added in this release. I can push it via the marvell git repository if you have no objections.

Thanks,
Stefan

Jagan Teki

2016-04-06 11:21 UTC #4 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Hi Stefan,

Quoted 95 lines · Stefan Roese

Hi Jagan,
Quoted 91 lines · Stefan Roese
Hi Jagan,
please excuse the long delay here. Some comments below.
Quoted 70 lines · Jagan Teki
Quoted 68 lines · Stefan Roese
Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.
The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.
Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>
---
  arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
  drivers/spi/kirkwood_spi.c            |  6 ++++++
  2 files changed, 18 insertions(+), 5 deletions(-)
arch/arm/include/asm/arch-mvebu/spi.h +2 -0
index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
  #define SCK_MPP10      (1 << 1)
  #define MISO_MPP11     (1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT          (1 << 0) /* Activates serial memory
interface */
arch/arm/include/asm/arch-mvebu/spi.h +5 -1
+#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT         2       /* chip select shift */
+#define KWSPI_CS_MASK          0x7     /* chip select mask */
+
+/* Configuration Register */
  #define KWSPI_CLKPRESCL_MASK   0x1f
  #define KWSPI_CLKPRESCL_MIN    0x12
-#define KWSPI_CSN_ACT          1 /* Activates serial memory
interface */
arch/arm/include/asm/arch-mvebu/spi.h +0 -4
-#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready
irq */
  #define KWSPI_XFERLEN_1BYTE    0
  #define KWSPI_XFERLEN_2BYTE    (1 << 5)
  #define KWSPI_XFERLEN_MASK     (1 << 5)
arch/arm/include/asm/arch-mvebu/spi.h +4 -0
@@ -47,6 +49,11 @@ struct kwspi_registers {
  #define KWSPI_ADRLEN_3BYTE     (2 << 8)
  #define KWSPI_ADRLEN_4BYTE     (3 << 8)
  #define KWSPI_ADRLEN_MASK      (3 << 8)
+
+#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready
irq */
arch/arm/include/asm/arch-mvebu/spi.h +1 -0
+
  #define KWSPI_TIMEOUT          10000
 
  #endif /* __KW_SPI_H__ */
drivers/spi/kirkwood_spi.c +0 -0
index 7890796..fa30be4 100644
@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev,
 unsigned int bitlen,
         struct udevice *bus = dev->parent;
         struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
 
Quoted 9 lines
drivers/spi/kirkwood_spi.c static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, · line 287
Quoted 5 lines
drivers/spi/kirkwood_spi.c +5 -0
+#ifdef CONFIG_ARCH_MVEBU
+       clrsetbits_le32(&plat->spireg->ctrl,
+                       KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+                       spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif
This looks clearing a desired cs from 'sf probe' why is this need here?
Its not clearing a CS but configuring the CS number in the CTRL register. This configured CS number will get enabled or disabled exactly the same way as when its zero (without this patch) in the existing spi_cs_activate/deactivate functions

OK, if ie the case configure doesn't require for each spi_xfer, isn't it? may be we can put this on to probe or setup_slave area?

Quoted 9 lines

Quoted 9 lines
Quoted 3 lines
I think we can do the desired cs activate or deactivate through existing spi_cs_activate/deactivate functions itself.
This is exactly what this patch does. The CS number is configured with the clrsetbits_le32() call above. And activated / deactivated in the existing functions.

Quoted 6 lines

Quoted 1 line
Or do you mean something else?
Any updates on this? I would like to have this multiple CS support added in this release. I can push it via the marvell git repository if you have no objections.

thanks!

Signature · 1 line

Jagan.

Stefan Roese

author

2016-04-06 11:32 UTC #5 lore raw

PATCH 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Hi Jagan,

Quoted 92 lines · Jagan Teki

Quoted 91 lines · Stefan Roese

Hi Jagan,

Quoted 87 lines · Stefan Roese

Hi Jagan,

please excuse the long delay here. Some comments below.

Quoted 79 lines · Jagan Teki

Quoted 64 lines · Stefan Roese

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Jagan Teki <[email protected]>

---
   arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
   drivers/spi/kirkwood_spi.c            |  6 ++++++
   2 files changed, 18 insertions(+), 5 deletions(-)

arch/arm/include/asm/arch-mvebu/spi.h +2 -0

index e512dce..4b66499 100644
@@ -32,13 +32,15 @@ struct kwspi_registers {
   #define SCK_MPP10      (1 << 1)
   #define MISO_MPP11     (1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT          (1 << 0) /* Activates serial memory

interface */

arch/arm/include/asm/arch-mvebu/spi.h +5 -1

+#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT         2       /* chip select shift */
+#define KWSPI_CS_MASK          0x7     /* chip select mask */
+
+/* Configuration Register */
   #define KWSPI_CLKPRESCL_MASK   0x1f
   #define KWSPI_CLKPRESCL_MIN    0x12
-#define KWSPI_CSN_ACT          1 /* Activates serial memory

interface */

arch/arm/include/asm/arch-mvebu/spi.h +0 -4

-#define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready

irq */

   #define KWSPI_XFERLEN_1BYTE    0
   #define KWSPI_XFERLEN_2BYTE    (1 << 5)
   #define KWSPI_XFERLEN_MASK     (1 << 5)

arch/arm/include/asm/arch-mvebu/spi.h +4 -0

@@ -47,6 +49,11 @@ struct kwspi_registers {
   #define KWSPI_ADRLEN_3BYTE     (2 << 8)
   #define KWSPI_ADRLEN_4BYTE     (3 << 8)
   #define KWSPI_ADRLEN_MASK      (3 << 8)
+
+#define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK          0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ                1 /* SerMem data xfer ready

irq */

arch/arm/include/asm/arch-mvebu/spi.h +1 -0

+
   #define KWSPI_TIMEOUT          10000
 
   #endif /* __KW_SPI_H__ */

drivers/spi/kirkwood_spi.c +0 -0

index 7890796..fa30be4 100644

drivers/spi/kirkwood_spi.c static int mvebu_spi_xfer(struct udevice *dev, · line 288

Quoted 9 lines

drivers/spi/kirkwood_spi.c +5 -0

@@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev,
 unsigned int bitlen,
          struct udevice *bus = dev->parent;
          struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
 
+#ifdef CONFIG_ARCH_MVEBU
+       clrsetbits_le32(&plat->spireg->ctrl,
+                       KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+                       spi_chip_select(dev) << KWSPI_CS_SHIFT);
+#endif

This looks clearing a desired cs from 'sf probe' why is this need here?

Quoted 7 lines

Quoted 4 lines
Quoted 4 lines
Its not clearing a CS but configuring the CS number in the CTRL register. This configured CS number will get enabled or disabled exactly the same way as when its zero (without this patch) in the existing spi_cs_activate/deactivate functions
OK, if ie the case configure doesn't require for each spi_xfer, isn't it?

Correct.

Quoted 1 line

may be we can put this on to probe or setup_slave area?

AFAIK, probe() is only called once per SPI controller. Without any device (chip-select) to use. We need a function that's called per SPI device for this specific chip-select configuration. Checking a bit further, I could use claim_bus() for this. If you are okay, I'll send a v2, using clain_bus() for this CS configuration.

Okay?

Thanks,
Stefan