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spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

PATCH Superseded Stefan Roese 2 participants 5 messages Apr 6, 2016

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Arm (32-bit) SPI
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Stefan Roese

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#0 lore raw

PATCH v3 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>

---
v3:
- Remove unnecessary #ifdef

v2:
- Introduce clain_bus() function and move the CS configuration into it. As it only needs to be done once for the active bus.

  arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++-----
 drivers/spi/kirkwood_spi.c            | 14 ++++++++++++++
 2 files changed, 26 insertions(+), 5 deletions(-)
arch/arm/include/asm/arch-mvebu/spi.h +12 -5
index 526fea6..78869a2 100644
@@ -35,13 +35,15 @@ struct kwspi_registers {
 #define SCK_MPP10	(1 << 1)
 #define MISO_MPP11	(1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT		(1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT		2	/* chip select shift */
+#define KWSPI_CS_MASK		0x7	/* chip select mask */
+
+/* Configuration Register */
 #define KWSPI_CLKPRESCL_MASK	0x1f
 #define KWSPI_CLKPRESCL_MIN	0x12
-#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
 #define KWSPI_XFERLEN_1BYTE	0
 #define KWSPI_XFERLEN_2BYTE	(1 << 5)
 #define KWSPI_XFERLEN_MASK	(1 << 5)

@@ -50,6 +52,11 @@ struct kwspi_registers {
 #define KWSPI_ADRLEN_3BYTE	(2 << 8)
 #define KWSPI_ADRLEN_4BYTE	(3 << 8)
 #define KWSPI_ADRLEN_MASK	(3 << 8)
+
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+
 #define KWSPI_TIMEOUT		10000
 
 #endif /* __KW_SPI_H__ */
drivers/spi/kirkwood_spi.c +14 -0
index 80cdbd0..6851ba9 100644
@@ -283,6 +283,19 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
 }
 
+static int mvebu_spi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+	/* Configure the chip-select in the CTRL register */
+	clrsetbits_le32(&plat->spireg->ctrl,
+			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+			spi_chip_select(dev) << KWSPI_CS_SHIFT);
+
+	return 0;
+}
+
 static int mvebu_spi_probe(struct udevice *bus)
 {
 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

@@ -305,6 +318,7 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
 }
 
 static const struct dm_spi_ops mvebu_spi_ops = {
+	.claim_bus	= mvebu_spi_claim_bus,
 	.xfer		= mvebu_spi_xfer,
 	.set_speed	= mvebu_spi_set_speed,
 	.set_mode	= mvebu_spi_set_mode,
Signature · 1 line
2.8.1
#1 lore raw

PATCH v3 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Quoted 7 lines · Stefan Roese

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Quoted 6 lines
Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>

---
v3:
- Remove unnecessary #ifdef

Does this mean dm for this driver will operate only for MVEBU now?

Signature · 1 line
Jagan.
author
#2 lore raw

PATCH v3 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Quoted 8 lines · Jagan Teki
Quoted 7 lines · Stefan Roese

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers.

Quoted 8 lines
Quoted 6 lines
Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>

---
v3:
- Remove unnecessary #ifdef

Does this mean dm for this driver will operate only for MVEBU now?

Not sure. The Kirkwood platform has not been ported to DM yet. But I can't see anything right now that should prevent Kirkwood to using this driver also once its ported to DM. Not sure why I had this #ifdef in this patch - its been a while since I first started this patch.

Are you okay with this patch now? If yes, should I push it via the Marvell repository?

Thanks,
Stefan

#3 lore raw

PATCH v3 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Quoted 10 lines · Stefan Roese
Quoted 8 lines · Jagan Teki
Quoted 6 lines · Stefan Roese

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch.

Grouping

Quoted 10 lines
Quoted 10 lines
Quoted 8 lines

them to the corresponding registers.

Signed-off-by Stefan Roese <[email protected]>
Cc Luka Perkov <[email protected]>
Cc Jagan Teki <[email protected]>

---
v3:
- Remove unnecessary #ifdef

Quoted 9 lines
Quoted 1 line

Does this mean dm for this driver will operate only for MVEBU now?

Not sure. The Kirkwood platform has not been ported to DM yet. But I can't see anything right now that should prevent Kirkwood to using this driver also once its ported to DM. Not sure why I had this #ifdef in this patch - its been a while since I first started this patch.

Reviewed-by Jagan Teki <[email protected]>
Quoted 2 lines

Are you okay with this patch now? If yes, should I push it via the Marvell repository?

Ok.

author
#4 lore raw

PATCH v3 1/1 spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Quoted 36 lines · Jagan Teki
Quoted 4 lines · On Apr 6, 2016 6:01 PM, "Stefan Roese" <sr at denx.de <mailto:[email protected]>>…
Quoted 2 lines · Jagan Teki

On 6 April 2016 at 17:24, Stefan Roese <[email protected]

Quoted 6 lines · <mailto:[email protected]>> wrote:
Quoted 6 lines
Quoted 6 lines

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch.

Grouping

Quoted 4 lines
Quoted 4 lines
Quoted 4 lines

them to the corresponding registers.

Signed-off-by Stefan Roese <sr at denx.de <mailto:[email protected]>>
Cc Luka Perkov <[email protected]

<mailto:[email protected]>>

Quoted 6 lines
Quoted 6 lines
Quoted 4 lines
Cc Jagan Teki <jteki at openedev.com <mailto:[email protected]>>

---
v3:
- Remove unnecessary #ifdef

Quoted 9 lines
Quoted 1 line

Does this mean dm for this driver will operate only for MVEBU now?

Not sure. The Kirkwood platform has not been ported to DM yet. But I can't see anything right now that should prevent Kirkwood to using this driver also once its ported to DM. Not sure why I had this #ifdef in this patch - its been a while since I first started this patch.

Quoted 6 lines
Reviewed-by Jagan Teki <jteki at openedev.com <mailto:[email protected]>>
Quoted 2 lines

Are you okay with this patch now? If yes, should I push it via the Marvell repository?

Ok.

Applied to u-boot-marvell/master.

Thanks,
Stefan