board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
PATCH 1/1 board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
From: Schuyler Patton <[email protected]>
Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet
Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different bank, minus 1.
Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1.
---
X15 BOM:
https://github.com/beagleboard/beagleboard-x15/blob/master/BeagleBoard-X15_RevA2B_BOM.xlsx
AM5728 Data sheet: http://www.ti.com/product/AM5728/datasheet
board/ti/am57xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
board/ti/am57xx/board.c +2 -2
@@ -131,9 +131,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config2 = 0x08000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36ab, + .sdram_tim1 = 0xcccf36b3, .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x409f88a8, + .sdram_tim3 = 0x407f88a8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
Signature · 1 line
2.8.0
PATCH 1/1 board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
Quoted 6 lines · Nishanth Menon
From: Schuyler Patton <[email protected]>
Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet
Quoted 6 lines
Update
T_RRDfrom 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different bank, minus 1.Update
T_CKESRfrom 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1.
Thanks and regards,
Lokesh
PATCH 1/1 board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
In reply to Nishanth MenonQuoted 10 lines · Nishanth Menon
From: Schuyler Patton <[email protected]>
Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet
Update
T_RRDfrom 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different bank, minus 1.
Quoted 5 lines
Update
T_CKESRfrom 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1.Signed-off-by Schuyler Patton <[email protected]>Signed-off-by Nishanth Menon <[email protected]>
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160411/94907101/attachment.sig>
Quoted 10 lines · Nishanth Menon
From: Schuyler Patton <[email protected]>
Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet
Update
T_RRDfrom 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different bank, minus 1.
Quoted 7 lines
Update
T_CKESRfrom 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1.Signed-off-by Schuyler Patton <[email protected]>Signed-off-by Nishanth Menon <[email protected]>Reviewed-by Lokesh Vutla <[email protected]>Reviewed-by Tom Rini <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160421/7bf7b3b8/attachment.sig>