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board: ge: bx50v3: Disable unused pins

PATCH New Akshay Bhat 2 participants 2 messages Apr 13, 2016 – Apr 19, 2016

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PATCH 1/1 board: ge: bx50v3: Disable unused pins

From: Justin Waters <[email protected]>

Certain pins are not used on the i.MX6, and should have a neutral pad configuration in order to reduce electrical interference on the board. This commit defines these pins with a default value rather than relying on the system defaults.

---
 board/ge/bx50v3/bx50v3.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
board/ge/bx50v3/bx50v3.c +10 -0
index 822fc35..ff8f4d7 100644
@@ -28,6 +28,10 @@
 #include <pwm.h>
 DECLARE_GLOBAL_DATA_PTR;
 
+#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS)
+
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
@@ -532,6 +536,12 @@ int board_eth_init(bd_t *bis)
 
 static iomux_v3_cfg_t const misc_pads[] = {
 	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
 };
 #define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
 #define WIFI_EN	IMX_GPIO_NR(6, 14)
Signature · 1 line
2.8.1
#1 lore raw

PATCH 1/1 board: ge: bx50v3: Disable unused pins

Quoted 33 lines · Akshay Bhat

From: Justin Waters <[email protected]>

Certain pins are not used on the i.MX6, and should have a neutral pad configuration in order to reduce electrical interference on the board. This commit defines these pins with a default value rather than relying on the system defaults.

---
 board/ge/bx50v3/bx50v3.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
board/ge/bx50v3/bx50v3.c +4 -0
index 822fc35..ff8f4d7 100644
@@ -28,6 +28,10 @@
 #include <pwm.h>
 DECLARE_GLOBAL_DATA_PTR;
 
+#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS)
+
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
@@ -532,6 +536,12 @@ int board_eth_init(bd_t *bis)
 
 static iomux_v3_cfg_t const misc_pads[] = {

board/ge/bx50v3/bx50v3.c int board_eth_init(bd_t *bis) · line 547

Quoted 10 lines
board/ge/bx50v3/bx50v3.c +6 -0
 	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
 };
 #define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
 #define WIFI_EN	IMX_GPIO_NR(6, 14)

Applied to master, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
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