ARM: tegra: cleanup part 1

deleted file mode 100644
index 8c2586c6f548..000000000000
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY	(300)
-#define IO_STABILIZATION_DELAY	(1000)
-
-#define PLLX_ENABLED		(1 << 30)
-#define CCLK_BURST_POLICY	0x20008888
-#define SUPER_CCLK_DIVIDER	0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ)	((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)	(((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0		0x0
-
-/* AP base physical address of internal SRAM */
-#define NV_PA_BASE_SRAM		0x40000000
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP			2
-#define HALT_COP_EVENT_JTAG		(1 << 28)
-#define HALT_COP_EVENT_IRQ_1		(1 << 11)
-#define HALT_COP_EVENT_FIQ_1		(1 << 9)
-
-/* This is the main entry into U-Boot, used by the Cortex-A9 */
-extern void _start(void);
-
-/**
- * Works out the SOC/SKU type used for clocks settings
- *
- * @return	SOC type - see TEGRA_SOC...
- */
-int tegra_get_chip_sku(void);
-
-/**
- * Returns the pure SOC (chip ID) from the HIDREV register
- *
- * @return	SOC ID - see CHIPID_TEGRAxx...
- */
-int tegra_get_chip(void);
-
-/**
- * Returns the SKU ID from the sku_info register
- *
- * @return	SKU ID - see SKU_ID_Txx...
- */
-int tegra_get_sku_info(void);
-
-/* Do any chip-specific cache config */
-void config_cache(void);
-
-#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
-bool tegra_cpu_is_non_secure(void);
-#endif

135 lines not on this page · raw message

index e56031d1afa7..a20832b7f35f 100644
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -134,7 +135,6 @@ enum crc_reset_id {
 	/* Things we can hold in reset for each CPU */
 	crc_rst_cpu = 1,
 	crc_rst_de = 1 << 4,	/* What is de? */
-	crc_rst_watchdog = 1 << 8,
 	crc_rst_debug = 1 << 12,
 };
 

index 695f3e6fba82..854966a30f9e 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010-2015
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -8,8 +8,6 @@
 #ifndef _TEGRA_GP_PADCTRL_H_
 #define _TEGRA_GP_PADCTRL_H_
 
-#define GP_HIDREV			0x804
-
 /* bit fields definitions for APB_MISC_GP_HIDREV register */
 #define HIDREV_CHIPID_SHIFT		8
 #define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)

index daf5698e6625..363d16c486d1 100644
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2011, Google Inc. All rights reserved.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -8,8 +10,6 @@
 
 #define TEGRA_GPIOS_PER_PORT	8
 #define TEGRA_PORTS_PER_BANK	4
-#define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
-#define GPIO_NAME_SIZE		20	/* gpio_request max label len */
 
 #define GPIO_BANK(x)		((x) >> 5)
 #define GPIO_PORT(x)		(((x) >> 3) & 0x3)

index 66c08797656c..9c9b67448985 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010-2015
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -294,7 +294,6 @@ struct pmc_ctlr {
 #define CRAIL		0
 #define CE0		14
 #define C0NC		15
-#define SOR		17
 
 #define PMC_XOFS_SHIFT	1
 #define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)

@@ -319,20 +318,6 @@ struct pmc_ctlr {
 #define MULT_16			4
 #endif
 
-#define AMAP_WRITE_SHIFT	20
-#define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
-
-/* SEC_DISABLE_0, 0x04 */
-#define SEC_DISABLE_WRITE0_ON			(1 << 4)
-#define SEC_DISABLE_READ0_ON			(1 << 5)
-#define SEC_DISABLE_WRITE1_ON			(1 << 6)
-#define SEC_DISABLE_READ1_ON			(1 << 7)
-#define SEC_DISABLE_WRITE2_ON			(1 << 8)
-#define SEC_DISABLE_READ2_ON			(1 << 9)
-#define SEC_DISABLE_WRITE3_ON			(1 << 10)
-#define SEC_DISABLE_READ3_ON			(1 << 11)
-#define SEC_DISABLE_AMAP_WRITE_ON		(1 << 20)
-
 /* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
 #define PWRGATE_TOGGLE_PARTID_CRAIL		0
 #define PWRGATE_TOGGLE_PARTID_TD		1

index 5a2d9f3a9c1e..b69c0b041f40 100644
@@ -2,6 +2,7 @@
  * Tegra pulse width frequency modulator definitions
  *
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -15,8 +16,6 @@ struct pwm_ctlr {
 	uint reserved[3];	/* Space space */
 };
 
-#define PWM_NUM_CHANNELS	4
-
 /* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
 #define PWM_ENABLE_SHIFT	31
 #define PWM_ENABLE_MASK	(0x1 << PWM_ENABLE_SHIFT)

index b64f9d813b0e..8c2f94b578fe 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -8,8 +8,6 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-void invalidate_dcache(void);
-
 /**
  * tegra_board_id() - Get the board iD
  *

index 3add1b3c09bb..4051a7d26630 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -8,6 +8,8 @@
 #ifndef _TEGRA_H_
 #define _TEGRA_H_
 
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM		0x40000000
 #define NV_PA_ARM_PERIPHBASE	0x50040000
 #define NV_PA_PG_UP_BASE	0x60000000
 #define NV_PA_TMRUS_BASE	0x60005010

@@ -22,17 +24,8 @@
 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
-#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
-#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
-#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
-#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
-#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
-#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
-#define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
 	defined(CONFIG_TEGRA114)

@@ -40,19 +33,11 @@
 #else
 #define NV_PA_CSITE_BASE	0x70800000
 #endif
-#define TEGRA_USB_ADDR_MASK	0xFFFFC000
 
-#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
-#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
-#define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
-#define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
+#define PG_UP_TAG_0		0x0
 #define PG_UP_TAG_AVP		0xAAAAAAAA
 
 #ifndef __ASSEMBLY__
-struct timerus {
-	unsigned int cntr_1us;
-};
-
 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
 #define NV_WB_RUN_ADDRESS	0x40020000
 

@@ -96,9 +81,8 @@ enum {
 	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,
 };
+#endif
 
-#else  /* __ASSEMBLY__ */
 #define PRM_RSTCTRL		NV_PA_PMC_BASE
-#endif
 
 #endif	/* TEGRA_H */

index 341df74d777d..eb83af89f7f5 100644
@@ -1,7 +1,7 @@
 /*
  * NVIDIA Tegra I2C controller
  *
- * Copyright 2010-2011 NVIDIA Corporation
+ * Copyright 2010-2016 NVIDIA Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -18,11 +18,7 @@ enum {
 
 enum i2c_transaction_flags {
 	I2C_IS_WRITE = 0x1,		/* for I2C write operation */
-	I2C_IS_10_BIT_ADDRESS = 0x2,	/* for 10-bit I2C slave address */
-	I2C_USE_REPEATED_START = 0x4,	/* for repeat start */
-	I2C_NO_ACK = 0x8,		/* for slave that won't generate ACK */
-	I2C_SOFTWARE_CONTROLLER	= 0x10,	/* for I2C transfer using GPIO */
-	I2C_NO_STOP = 0x20,
+	I2C_USE_REPEATED_START = 0x2,	/* for repeat start */
 };
 
 /* Contians the I2C transaction details */

@@ -38,7 +34,6 @@ struct i2c_trans_info {
 	 * the slave device.
 	 */
 	u8 *buf;
-	int is_10bit_address;
 };
 
 struct i2c_control {

@@ -142,8 +137,6 @@ struct i2c_ctlr {
 #define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 
 /* I2C_CLK_DIVISOR_REGISTER */
-#define CLK_DIV_STD_FAST_MODE		0x19
-#define CLK_DIV_HS_MODE			1
 #define CLK_MULT_STD_FAST_MODE		8
 
 /**

index a20bdaa61872..9b371add1de4 100644
@@ -1,7 +1,7 @@
 /*
+ * Copyright (C) 2011-2016 NVIDIA Corporation
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <[email protected]>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -15,7 +15,6 @@
 /* for mmc_config definition */
 #include <mmc.h>
 
-#ifndef __ASSEMBLY__
 struct tegra_mmc {
 	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
 	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */

@@ -145,5 +144,4 @@ struct mmc_host {
 
 void pad_init_mmc(struct mmc_host *host);
 
-#endif	/* __ASSEMBLY__ */
 #endif	/* __TEGRA_MMC_H_ */

deleted file mode 100644
index 5d5664115f41..000000000000
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* Tegra20 timer functions */
-
-#ifndef _TEGRA_TIMER_H
-#define _TEGRA_TIMER_H
-
-/* returns the current monotonic timer value in microseconds */
-unsigned long timer_get_us(void);
-
-#endif

deleted file mode 100644
index fef7f8db3f98..000000000000
@@ -1,31 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _UART_H_
-#define _UART_H_
-
-/* UART registers */
-struct uart_ctlr {
-	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
-	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
-	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
-	uint uart_lcr;			/* UART_LCR_0, offset 0C */
-	uint uart_mcr;			/* UART_MCR_0, offset 10 */
-	uint uart_lsr;			/* UART_LSR_0, offset 14 */
-	uint uart_msr;			/* UART_MSR_0, offset 18 */
-	uint uart_spr;			/* UART_SPR_0, offset 1C */
-	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
-	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
-	uint uart_asr;			/* UART_ASR_0, offset 3C */
-};
-
-#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
-#define NV_DEFAULT_DEBUG_BAUD		115200
-
-#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
-
-#endif	/* UART_H */

index f400c01a3954..24198e4a33d0 100644
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
+ * Copyright (c) 2013-2016 NVIDIA Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -355,7 +355,4 @@ struct usb_ctlr {
 #define VBUS_B_SESS_VLD_SW_VALUE	(1 << 12)
 #define VBUS_B_SESS_VLD_SW_EN		(1 << 11)
 
-/* Setup USB on the board */
-int usb_process_devicetree(const void *blob);
-
 #endif	/* _TEGRA_USB_H_ */

index 2e66e0f23b9b..b6326c8f7b11 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010, 2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -127,7 +127,6 @@ union scratch3_reg {
 int warmboot_save_sdram_params(void);
 
 int warmboot_prepare_code(u32 seg_address, u32 seg_length);
-int sign_data_block(u8 *source, u32 length, u8 *signature);
 void wb_start(void);	/* Start of WB assembly code */
 void wb_end(void);	/* End of WB assembly code */
 

91 lines not on this page · raw message

58 lines not on this page · raw message

index 7818b1bd3455..3f70fb190527 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2013
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -35,14 +35,8 @@ struct flow_ctlr {
 };
 
 /* HALT_COP_EVENTS_0, 0x04 */
-#define EVENT_MSEC		(1 << 24)
-#define EVENT_USEC		(1 << 25)
-#define EVENT_JTAG		(1 << 28)
 #define EVENT_MODE_STOP		(2 << 29)
 
-/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
-#define ACTIVE_LP		(1 << 0)
-
 /* CPUn_CSR_0 */
 #define CSR_ENABLE		(1 << 0)
 #define CSR_IMMEDIATE_WAKE	(1 << 3)

index d97b2c87c631..190dd9754ef1 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -66,7 +66,6 @@ struct mc_ctlr {
 
 #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
 
-#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
 
 #endif	/* _TEGRA124_MC_H_ */

index db3d8379203b..f009925611c6 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -23,8 +23,5 @@
 #define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
 
 #define MAX_NUM_CPU		4
-#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
-
-#define TEGRA_USB1_BASE		0x7D000000
 
 #endif /* _TEGRA124_H_ */

index 22774abb936d..1cea245e4171 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -13,8 +13,6 @@
 
 #include <asm/arch-tegra/tegra.h>
 
-#define TEGRA_USB1_BASE		0xC5000000
-
 #define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
 
 #define MAX_NUM_CPU		2

index 3a37af417748..2e676a436e3d 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -77,15 +77,4 @@ struct ahb_ctlr {
 	u32 axicif_fastsync2_mcclk_to_cpuclk;
 };
 
-#define PPSB_STOPCLK_ENABLE	(1 << 2)
-
-#define GIZ_ENABLE_SPLIT	(1 << 0)
-#define GIZ_ENB_FAST_REARB	(1 << 2)
-#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
-
-#define GIZ_USB_IMMEDIATE	(1 << 18)
-
-/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
-#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
-
 #endif	/* _TEGRA210_AHB_H_ */

index 3501be2abbb4..54e70439952d 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -20,7 +20,6 @@
 #define PLLC_RESET		30
 #define PLLC_IDDQ		27
 #define PLLD_ENABLE_CLK		21
-#define PLLD_EN_LCKDET		28
 
 int tegra_plle_enable(void);
 

index e2301aee548f..e4ede6a81500 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -28,18 +28,4 @@ struct flow_ctlr {
 	u32 ram_repair;		/* offset 0x40 */
 };
 
-/* HALT_COP_EVENTS_0, 0x04 */
-#define EVENT_MSEC		(1 << 24)
-#define EVENT_USEC		(1 << 25)
-#define EVENT_JTAG		(1 << 28)
-#define EVENT_MODE_STOP		(2 << 29)
-
-/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
-#define ACTIVE_LP		(1 << 0)
-
-/* CPUn_CSR_0 */
-#define CSR_ENABLE		(1 << 0)
-#define CSR_IMMEDIATE_WAKE	(1 << 3)
-#define CSR_WAIT_WFI_SHIFT	8
-
 #endif /*  _TEGRA210_FLOW_H_ */

index 77e9aa51f60f..dc910b9c7a0f 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2016 NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: GPL-2.0+
  */

@@ -64,9 +64,6 @@ struct mc_ctlr {
 	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
 };
 
-#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
-
-#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
 
 #endif	/* _TEGRA210_MC_H_ */

index 95c67fbb8e9f..17b9f6af3679 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -25,8 +25,5 @@
 #define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
 
 #define MAX_NUM_CPU		4
-#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
-
-#define TEGRA_USB1_BASE		0x7D000000
 
 #endif /* _TEGRA210_TEGRA_H_ */

index 280245e98e87..28f9741a1d76 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -12,8 +12,6 @@
 
 #include <asm/arch-tegra/tegra.h>
 
-#define TEGRA_USB1_BASE		0x7D000000
-
 #define BCT_ODMDATA_OFFSET	6116	/* 12 bytes from end of BCT */
 
 #define MAX_NUM_CPU		4

index a4fa00c9adae..336a7e08196d 100644
@@ -1,9 +1,9 @@
 /*
-* (C) Copyright 2010-2015
-* NVIDIA Corporation <www.nvidia.com>
-*
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
-*/
+ */
 
 /* Tegra AP (Application Processor) code */
 

@@ -12,13 +12,13 @@
 #include <asm/io.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/mc.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clock.h>
 #include <asm/arch-tegra/fuse.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/scu.h>
 #include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
+#include "cpu.h"
 
 int tegra_get_chip(void)
 {

index 3d1d26d13d13..098547ab1e88 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010-2015
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -14,7 +14,6 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>

@@ -77,7 +76,7 @@ static phys_size_t query_sdram_size(void)
 	emem_cfg = readl(&mc->mc_emem_cfg);
 #if defined(CONFIG_TEGRA20)
 	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
-	size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
+	size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE, emem_cfg * 1024);
 #else
 	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
 #ifndef CONFIG_PHYS_64BIT

@@ -101,8 +100,8 @@ static phys_size_t query_sdram_size(void)
 		 * avoid using it. There's no reason we should need this
 		 * validation step anyway.
 		 */
-		if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
-			size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
+		if (emem_cfg <= (0 - NV_PA_SDRAM_BASE) / (1024 * 1024))
+			size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE,
 						  size_bytes);
 #endif
 	}

index 141d6e1cb555..33e346017a8b 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -17,12 +17,10 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
-#include <asm/arch-tegra/uart.h>
 #include <asm/arch-tegra/warmboot.h>
 #include <asm/arch-tegra/gpu.h>
 #ifdef CONFIG_TEGRA_CLOCK_SCALING

index 6dad40325d2f..b93814fcb96b 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -8,8 +8,8 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch/gp_padctrl.h>
+#include "cpu.h"
 
 #ifndef CONFIG_ARM64
 void config_cache(void)

index c50d56dc888b..80d6fccf2551 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -11,10 +11,8 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 3f38969a44f1..c0284ce03787 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -21,20 +21,12 @@
 #error "Unknown Tegra chip!"
 #endif
 
-#define PLLX_ENABLED		(1 << 30)
 #define CCLK_BURST_POLICY	0x20008888
 #define SUPER_CCLK_DIVIDER	0x80000000
 
 /* Calculate clock fractional divider value from ref and target frequencies */
 #define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
 
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0             0x0
-
 #define CORESIGHT_UNLOCK	0xC5ACCE55
 
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)

@@ -53,10 +45,6 @@
 
 #define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
 
-/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
-#define SB_AA64_RESET_LOW	0x6000C230
-#define SB_AA64_RESET_HIGH	0x6000C234
-
 struct clk_pll_table {
 	u16	n;
 	u16	m;

@@ -71,8 +59,28 @@ void init_pllx(void);
 void powerup_cpu(void);
 void reset_A9_cpu(int reset);
 void start_cpu(u32 reset_vector);
+/**
+ * Returns the pure SOC (chip ID) from the HIDREV register
+ *
+ * @return	SOC ID - see CHIPID_TEGRAxx...
+ */
 int tegra_get_chip(void);
+/**
+ * Returns the SKU ID from the sku_info register
+ *
+ * @return	SKU ID - see SKU_ID_Txx...
+ */
 int tegra_get_sku_info(void);
+/**
+ * Works out the SOC/SKU type used for clocks settings
+ *
+ * @return	SOC type - see TEGRA_SOC...
+ */
 int tegra_get_chip_sku(void);
 void adjust_pllp_out_freqs(void);
 void pmic_enable_cpu_vdd(void);
+/* Do any chip-specific cache config */
+void config_cache(void);
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+bool tegra_cpu_is_non_secure(void);
+#endif

index 8c62f36a7b04..70aec7fc1b3d 100644
@@ -1,19 +1,20 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include "emc.h"
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/pmu.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/sys_proto.h>
+#include "emc.h"
+#include "cpu.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

index e6ef873c8dc4..7a73e159a7cd 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -13,7 +13,6 @@
 #include <asm/arch/sysctr.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 1e71146236e9..1219b6413844 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -13,7 +13,6 @@
 #include <asm/arch/sysctr.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 0aca6583bacd..be31cb4ac881 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -7,14 +7,12 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/ahb.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/flow.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/ap.h>
 #include "../cpu.h"
 
 /* Tegra124-specific CPU init code */

index 16d196508c6e..08225e32dbd4 100644
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2015, Siemens AG
  * Author: Jan Kiszka <[email protected]>
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -10,8 +11,8 @@
 #include <asm/psci.h>
 #include <asm/arch/flow.h>
 #include <asm/arch/powergate.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/pmc.h>
+#include "../cpu.h"
 
 static void park_cpu(void)
 {

index cd9fb9a55340..0ff538830abd 100644
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -14,7 +14,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 73be9a9cbd1f..52a476eb7d8a 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -12,5 +12,4 @@
 #include <asm/arch/display.h>
 #include <asm/arch-tegra/dc.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 

index ed2462ab0fa6..eab61b7cd2ab 100644
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -7,7 +8,6 @@
 #include <common.h>
 #include <fdtdec.h>
 #include <asm/io.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/emc.h>

index a774246a2779..0da704cd4f3c 100644
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -10,9 +10,9 @@
 #include <tps6586x.h>
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/tegra_i2c.h>
 #include <asm/arch-tegra/sys_proto.h>
+#include "../cpu.h"
 
 #define VDD_CORE_NOMINAL_T25	0x17	/* 1.3v */
 #define VDD_CPU_NOMINAL_T25	0x10	/* 1.125v */

index 5fdc4bbb5007..1013441d4265 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010 - 2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -14,12 +14,12 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sdram_param.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/fuse.h>
 #include <asm/arch-tegra/warmboot.h>
+#include "crypto.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

index 27ce5f480f54..616358b657be 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010 - 2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -11,11 +11,11 @@
 #include <asm/arch/flow.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/warmboot.h>
+#include "../cpu.h"
 #include "warmboot_avp.h"
 
 #define DEBUG_RESET_CORESIGHT

@@ -204,7 +204,7 @@ void wb_start(void)
 
 	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
 	      SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
-	      SCLK_SYS_STATE_IDLE;
+	      (SCLK_SYS_STATE_IDLE << SCLK_SYS_STATE_SHIFT);
 	writel(reg, &clkrst->crc_sclk_brst_pol);
 
 	/* avp_resume: no return after the write */

index 7b86acb15632..85892b023fad 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010, 2011
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -12,9 +12,6 @@
 #define TEGRA_DEV_H			1
 #define TEGRA_DEV_U			2
 
-#define SIMPLE_PLLX			(CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-#define SIMPLE_PLLE			(CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
-
 #define TIMER_USEC_CNTR			(NV_PA_TMRUS_BASE + 0)
 #define TIMER_USEC_CFG			(NV_PA_TMRUS_BASE + 4)
 

@@ -49,7 +46,6 @@
 #define PLLM_OUT1_CLKEN_ENABLE		(1 << 1)
 #define PLLM_OUT1_RATIO_VAL_8		(8 << 8)
 
-#define SCLK_SYS_STATE_IDLE		(1 << 28)
 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1	(7 << 12)
 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1	(7 << 8)
 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1	(7 << 4)

index f0052e7934a1..b025711acf09 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -14,7 +14,6 @@
 #include <asm/arch/sysctr.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 1f104f288e57..98289b8ac7a7 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -13,7 +13,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
 

index 9c8677943ad3..981862ce1aff 100644
@@ -1,8 +1,8 @@
 /*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *  (C) Copyright 2011-2012
- *  Avionic Design GmbH <www.avionic-design.de>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2011-2012
+ * Avionic Design GmbH <www.avionic-design.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -18,7 +18,6 @@
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/sys_proto.h>
-#include <asm/arch-tegra/uart.h>
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)

index 3f56971a13b1..8fdee023ee8a 100644
@@ -1,6 +1,7 @@
 /*
- *  (C) Copyright 2014
- *  Marcel Ziswiler <[email protected]>
+ * (C) Copyright 2014
+ * Marcel Ziswiler <[email protected]>
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -8,7 +9,6 @@
 #include <common.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
 #include <asm/io.h>

index 879f25a5384b..b9f845a09b6a 100644
@@ -1,5 +1,6 @@
 /*
- *  Copyright (C) 2012 Lucas Stach
+ * Copyright (C) 2012 Lucas Stach
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -8,7 +9,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>

index 44b5beb92832..3902bff203d5 100644
@@ -1,6 +1,7 @@
 /*
- *  (C) Copyright 2014
- *  Stefan Agner <[email protected]>
+ * (C) Copyright 2014
+ * Stefan Agner <[email protected]>
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -8,7 +9,6 @@
 #include <common.h>
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/tegra.h>
 #include <asm/gpio.h>
 #include <asm/io.h>

index 2fa07f9c57c4..0735ea0b2b12 100644
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
- * Copyright (c) 2010-2011 NVIDIA Corporation
- *  NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2010-2016 NVIDIA Corporation
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -292,7 +292,6 @@ static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
 	if (end_with_repeated_start)
 		trans_info.flags |= I2C_USE_REPEATED_START;
 	trans_info.num_bytes = len;
-	trans_info.is_10bit_address = 0;
 
 	error = send_recv_packets(i2c_bus, &trans_info);
 	if (error)

@@ -311,7 +310,6 @@ static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
 	trans_info.buf = data;
 	trans_info.flags = 0;
 	trans_info.num_bytes = len;
-	trans_info.is_10bit_address = 0;
 
 	error = send_recv_packets(i2c_bus, &trans_info);
 	if (error)

index c77f61076962..349d95804201 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2011
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -16,7 +16,6 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
-#include <asm/arch-tegra/timer.h>
 #include <linux/input.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index 7fd10e6af35e..13b10645478e 100644
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 

@@ -17,7 +19,6 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/display.h>
-#include <asm/arch-tegra/timer.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

index b07ee5645bb8..776394151661 100644
@@ -1,6 +1,6 @@
 /*
- *  (C) Copyright 2010-2012
- *  NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -84,7 +84,7 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRAM_BASE + 0x600000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 
 #ifndef CONFIG_ARM64

@@ -97,11 +97,9 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	2
-#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
 #define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE	NV_PA_SDRAM_BASE
 
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
 

index 9b371add1de4..adc9772a3c18 100644
@@ -142,6 +142,4 @@ struct mmc_host {
 	struct mmc_config cfg;	/* mmc configuration */
 };
 
-void pad_init_mmc(struct mmc_host *host);
-
 #endif	/* __TEGRA_MMC_H_ */

index 33e346017a8b..98fd94646909 100644
@@ -31,7 +31,6 @@
 #include <usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
-#include <asm/arch-tegra/tegra_mmc.h>
 #include <asm/arch-tegra/mmc.h>
 #endif
 #include <asm/arch-tegra/xusb-padctl.h>

@@ -246,34 +245,6 @@ int board_mmc_init(bd_t *bd)
 
 	return 0;
 }
-
-void pad_init_mmc(struct mmc_host *host)
-{
-#if defined(CONFIG_TEGRA30)
-	enum periph_id id = host->mmc_id;
-	u32 val;
-
-	debug("%s: sdmmc address = %08x, id = %d\n", __func__,
-		(unsigned int)host->reg, id);
-
-	/* Set the pad drive strength for SDMMC1 or 3 only */
-	if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
-		debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
-			__func__);
-		return;
-	}
-
-	val = readl(&host->reg->sdmemcmppadctl);
-	val &= 0xFFFFFFF0;
-	val |= MEMCOMP_PADCTRL_VREF;
-	writel(val, &host->reg->sdmemcmppadctl);
-
-	val = readl(&host->reg->autocalcfg);
-	val &= 0xFFFF0000;
-	val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
-	writel(val, &host->reg->autocalcfg);
-#endif	/* T30 */
-}
 #endif	/* MMC */
 
 /*

index 573819a01e21..23c6c2cf4583 100644
@@ -1,8 +1,8 @@
 /*
+ * Copyright 2011-2016 NVIDIA Corporation
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <[email protected]>
  * Jaehoon Chung <[email protected]>
- * Portions Copyright 2011-2015 NVIDIA Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -428,6 +428,34 @@ static void tegra_mmc_set_ios(struct mmc *mmc)
 	debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 }
 
+static void tegra_mmc_pad_init(struct mmc_host *host)
+{
+#if defined(CONFIG_TEGRA30)
+	enum periph_id id = host->mmc_id;
+	u32 val;
+
+	debug("%s: sdmmc address = %08x, id = %d\n", __func__,
+	      (unsigned int)host->reg, id);
+
+	/* Set the pad drive strength for SDMMC1 or 3 only */
+	if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+		debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+		      __func__);
+		return;
+	}
+
+	val = readl(&host->reg->sdmemcmppadctl);
+	val &= 0xFFFFFFF0;
+	val |= MEMCOMP_PADCTRL_VREF;
+	writel(val, &host->reg->sdmemcmppadctl);
+
+	val = readl(&host->reg->autocalcfg);
+	val &= 0xFFFF0000;
+	val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+	writel(val, &host->reg->autocalcfg);
+#endif	/* T30 */
+}
+
 static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 {
 	unsigned int timeout;

@@ -461,7 +489,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 		readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
 
 	/* Make sure SDIO pads are set up */
-	pad_init_mmc(host);
+	tegra_mmc_pad_init(host);
 }
 
 static int tegra_mmc_core_init(struct mmc *mmc)

index 23c6c2cf4583..12b14fc35d08 100644
@@ -9,13 +9,14 @@
 
 #include <bouncebuf.h>
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/mmc.h>
-#include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
+#include "tegra_mmc_priv.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

similarity index 98%
rename from arch/arm/include/asm/arch-tegra/tegra_mmc.h
rename to drivers/mmc/tegra_mmc_priv.h
index adc9772a3c18..3d9bcb78187c 100644
@@ -6,10 +6,9 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __TEGRA_MMC_H_
-#define __TEGRA_MMC_H_
+#ifndef __TEGRA_MMC_PRIV_H_
+#define __TEGRA_MMC_PRIV_H_
 
-#include <fdtdec.h>
 #include <asm/gpio.h>
 
 /* for mmc_config definition */

@@ -142,4 +141,4 @@ struct mmc_host {
 	struct mmc_config cfg;	/* mmc configuration */
 };
 
-#endif	/* __TEGRA_MMC_H_ */
+#endif

index 98fd94646909..05e83268cd40 100644
@@ -31,7 +31,7 @@
 #include <usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
-#include <asm/arch-tegra/mmc.h>
+#include <mach/tegra_mmc.h>
 #endif
 #include <asm/arch-tegra/xusb-padctl.h>
 #include <power/as3722.h>

similarity index 50%
rename from arch/arm/include/asm/arch-tegra/mmc.h
rename to arch/arm/mach-tegra/include/mach/tegra_mmc.h
index c2d52b297743..23f90e300b2a 100644
@@ -1,11 +1,12 @@
 /*
  * Copyright (c) 2011, Google Inc. All rights reserved.
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _TEGRA_MMC_H_
-#define _TEGRA_MMC_H_
+#ifndef _MACH_TEGRA_MMC_H_
+#define _MACH_TEGRA_MMC_H_
 
 void tegra_mmc_init(void);
 
-#endif /* _TEGRA_MMC_H_ */
+#endif

index 12b14fc35d08..6e1667b3bce7 100644
@@ -10,12 +10,12 @@
 #include <bouncebuf.h>
 #include <common.h>
 #include <fdtdec.h>
+#include <mmc.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/mmc.h>
-#include <mmc.h>
+#include <mach/tegra_mmc.h>
 #include "tegra_mmc_priv.h"
 
 DECLARE_GLOBAL_DATA_PTR;

deleted file mode 100644
index 3d2c4324dc1d..000000000000
@@ -1,14 +0,0 @@
-/*
- * Tegra pulse width frequency modulator definitions
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_TEGRA124_PWM_H
-#define __ASM_ARCH_TEGRA124_PWM_H
-
-#include <asm/arch-tegra/pwm.h>
-
-#endif	/* __ASM_ARCH_TEGRA124_PWM_H */

deleted file mode 100644
index 2207d9cd4d74..000000000000
@@ -1,14 +0,0 @@
-/*
- * Tegra pulse width frequency modulator definitions
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_TEGRA20_PWM_H
-#define __ASM_ARCH_TEGRA20_PWM_H
-
-#include <asm/arch-tegra/pwm.h>
-
-#endif	/* __ASM_ARCH_TEGRA20_PWM_H */

index 10e1fdc9b562..a0f204a216de 100644
@@ -1,5 +1,6 @@
 /*
  * Copyright 2016 Google Inc.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */

@@ -9,7 +10,7 @@
 #include <pwm.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/pwm.h>
+#include "tegra_pwm_priv.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

similarity index 86%
rename from arch/arm/include/asm/arch-tegra/pwm.h
rename to drivers/pwm/tegra_pwm_priv.h
index b69c0b041f40..25943494fb5c 100644
@@ -7,8 +7,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __ASM_ARCH_TEGRA_PWM_H
-#define __ASM_ARCH_TEGRA_PWM_H
+#ifndef _TEGRA_PWM_PRIV_H
+#define _TEGRA_PWM_PRIV_H
 
 /* This is a single PWM channel */
 struct pwm_ctlr {

@@ -26,4 +26,4 @@ struct pwm_ctlr {
 #define PWM_DIVIDER_SHIFT	0
 #define PWM_DIVIDER_MASK	(0x1FFF << PWM_DIVIDER_SHIFT)
 
-#endif	/* __ASM_ARCH_TEGRA_PWM_H */
+#endif

index 13b10645478e..b4c83b674147 100644
@@ -17,7 +17,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch/pwm.h>
 #include <asm/arch/display.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index 2f1f0df20eb1..d627285b8081 100644
@@ -1,5 +1,6 @@
 /*
  * Copyright 2014 Google Inc.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier:     GPL-2.0+
  *

@@ -18,7 +19,6 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/pwm.h>
 #include <asm/arch-tegra/dc.h>
 #include <dm/uclass-internal.h>
 #include "displayport.h"

new file mode 100644
index 000000000000..dcdd86cef71e
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (c) 2010-2016 NVIDIA Corporation
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/tegra_i2c.h>
+#include "../../../drivers/i2c/tegra_i2c_priv.h"
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}

new file mode 100644
index 000000000000..57837885176a
@@ -0,0 +1,25 @@
+/*
+ * NVIDIA Tegra I2C controller custom API
+ *
+ * Copyright 2010-2016 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _MACH_TEGRA_I2C_H_
+#define _MACH_TEGRA_I2C_H_
+
+struct udevice;
+
+/* Custom APIs for very early I2C access */
+void tegra_i2c_ll_write_addr(uint addr, uint config);
+void tegra_i2c_ll_write_data(uint data, uint config);
+
+/**
+ * Returns the bus number of the DVC controller
+ *
+ * @return number of bus, or -1 if there is no DVC active
+ */
+int tegra_i2c_get_dvc_bus(struct udevice **busp);
+
+#endif

index 0da704cd4f3c..8488d97d5cde 100644
@@ -10,8 +10,8 @@
 #include <tps6586x.h>
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/tegra_i2c.h>
 #include <asm/arch-tegra/sys_proto.h>
+#include <mach/tegra_i2c.h>
 #include "../cpu.h"
 
 #define VDD_CORE_NOMINAL_T25	0x17	/* 1.3v */

index 66b021b82459..774207354064 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -11,25 +11,10 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/tegra_i2c.h>
+#include <mach/tegra_i2c.h>
 #include "../cpu.h"
 
 /* Tegra30-specific CPU init code */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(addr, &reg->cmd_addr0);
-	writel(config, &reg->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(data, &reg->cmd_data1);
-	writel(config, &reg->cnfg);
-}
 
 #define TPS62366A_I2C_ADDR		0xC0
 #define TPS62366A_SET1_REG		0x01

index 960fea7ee7e3..86b164db3be1 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2013
+ * (C) Copyright 2013-2016
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+

@@ -7,27 +7,11 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch-tegra/tegra_i2c.h>
+#include <mach/tegra_i2c.h>
 #include "as3722_init.h"
 
 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
 
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(addr, &reg->cmd_addr0);
-	writel(config, &reg->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
-	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
-	writel(data, &reg->cmd_data1);
-	writel(config, &reg->cnfg);
-}
-
 void pmic_enable_cpu_vdd(void)
 {
 	debug("%s entry\n", __func__);

index 0735ea0b2b12..2a8ab2d5e0b9 100644
@@ -17,7 +17,8 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/tegra_i2c.h>
+#include <mach/tegra_i2c.h>
+#include "tegra_i2c_priv.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

similarity index 95%
rename from arch/arm/include/asm/arch-tegra/tegra_i2c.h
rename to drivers/i2c/tegra_i2c_priv.h
index eb83af89f7f5..95c73293d341 100644
@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0
  */
 
-#ifndef _TEGRA_I2C_H_
-#define _TEGRA_I2C_H_
+#ifndef _TEGRA_I2C_PRIV_H
+#define _TEGRA_I2C_PRIV_H
 
 #include <asm/types.h>
 

@@ -139,11 +139,4 @@ struct i2c_ctlr {
 /* I2C_CLK_DIVISOR_REGISTER */
 #define CLK_MULT_STD_FAST_MODE		8
 
-/**
- * Returns the bus number of the DVC controller
- *
- * @return number of bus, or -1 if there is no DVC active
- */
-int tegra_i2c_get_dvc_bus(struct udevice **busp);
-
-#endif	/* _TEGRA_I2C_H_ */
+#endif

index 05e83268cd40..3ee65ee3f921 100644
@@ -26,7 +26,7 @@
 #ifdef CONFIG_TEGRA_CLOCK_SCALING
 #include <asm/arch/emc.h>
 #endif
-#include <asm/arch-tegra/usb.h>
+#include "../../../drivers/usb/host/ehci-tegra-priv.h"
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <usb.h>
 #endif

similarity index 99%
rename from arch/arm/include/asm/arch-tegra/usb.h
rename to drivers/usb/host/ehci-tegra-priv.h
index 24198e4a33d0..72d8a1a7eb9c 100644
@@ -5,8 +5,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _TEGRA_USB_H_
-#define _TEGRA_USB_H_
+#ifndef _EHCI_TEGRA_PRIV_H
+#define _EHCI_TEGRA_PRIV_H
 
 /* USB Controller (USBx_CONTROLLER_) regs */
 struct usb_ctlr {

@@ -355,4 +355,4 @@ struct usb_ctlr {
 #define VBUS_B_SESS_VLD_SW_VALUE	(1 << 12)
 #define VBUS_B_SESS_VLD_SW_EN		(1 << 11)
 
-#endif	/* _TEGRA_USB_H_ */
+#endif

index 31d54ab285bf..9bf069382605 100644
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2009-2015 NVIDIA Corporation
+ * Copyright (c) 2009-2016 NVIDIA Corporation
  * Copyright (c) 2013 Lucas Stach
  *
  * SPDX-License-Identifier:	GPL-2.0+

@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm-generic/gpio.h>
 #include <asm/arch/clock.h>
-#include <asm/arch-tegra/usb.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <usb.h>
 #include <usb/ulpi.h>

@@ -20,6 +19,7 @@
 #include <fdtdec.h>
 
 #include "ehci.h"
+#include "ehci-tegra-priv.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

deleted file mode 100644
index ee5a3f6c91c0..000000000000
@@ -1,29 +0,0 @@
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include <asm/arch-tegra/dc.h>
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
-	enum win_color_depth_id fmt;	/* Color depth/format */
-	unsigned	bpp;		/* Bits per pixel */
-	phys_addr_t	phys_addr;	/* Physical address in memory */
-	unsigned	x;		/* Horizontal address offset (bytes) */
-	unsigned	y;		/* Veritical address offset (bytes) */
-	unsigned	w;		/* Width of source window */
-	unsigned	h;		/* Height of source window */
-	unsigned	stride;		/* Number of bytes per line */
-	unsigned	out_x;		/* Left edge of output window (col) */
-	unsigned	out_y;		/* Top edge of output window (row) */
-	unsigned	out_w;		/* Width of output window in pixels */
-	unsigned	out_h;		/* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/

deleted file mode 100644
index 52a476eb7d8a..000000000000
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2010-2016
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/display.h>
-#include <asm/arch-tegra/dc.h>
-#include <asm/arch-tegra/clk_rst.h>
-

index b4c83b674147..45a2876d4030 100644
@@ -13,11 +13,10 @@
 #include <asm/system.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch/display.h>
+#include "tegra_dc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

index d627285b8081..bc31103e8b92 100644
@@ -19,8 +19,8 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch-tegra/dc.h>
 #include <dm/uclass-internal.h>
+#include "../tegra_dc.h"
 #include "displayport.h"
 
 DECLARE_GLOBAL_DATA_PTR;

index 5bf8524a5e8a..4e97b6de276a 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013, NVIDIA Corporation.
+ * Copyright (c) 2011-2016, NVIDIA Corporation.
  * Copyright 2014 Google Inc.
  *
  * SPDX-License-Identifier:     GPL-2.0

@@ -13,7 +13,7 @@
 #include <fdtdec.h>
 #include <video_bridge.h>
 #include <asm/io.h>
-#include <asm/arch-tegra/dc.h>
+#include "../tegra_dc.h"
 #include "display.h"
 #include "edid.h"
 #include "sor.h"

index e5cea51d48c8..40d9dd22a2c4 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013, NVIDIA Corporation.
+ * Copyright (c) 2011-2016, NVIDIA Corporation.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -13,7 +13,7 @@
 #include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch-tegra/dc.h>
+#include "../tegra_dc.h"
 #include "displayport.h"
 #include "sor.h"
 

similarity index 94%
rename from arch/arm/include/asm/arch-tegra/dc.h
rename to drivers/video/tegra_dc.h
index 3a7ee5e77baf..77ff2122de3c 100644
@@ -1,12 +1,12 @@
 /*
- *  (C) Copyright 2010
+ *  (C) Copyright 2010-2016
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __ASM_ARCH_TEGRA_DC_H
-#define __ASM_ARCH_TEGRA_DC_H
+#ifndef _VIDEO_TEGRA_DC_H
+#define _VIDEO_TEGRA_DC_H
 
 /* Register definitions for the Tegra display controller */
 

@@ -566,4 +566,26 @@ enum {
 #define DC_N_WINDOWS			5
 #define DC_REG_SAVE_SPACE		(DC_N_WINDOWS + 5)
 
-#endif /* __ASM_ARCH_TEGRA_DC_H */
+#ifdef CONFIG_TEGRA20
+/*
+ * I am not sure if this structure actually only applies to Tegra20, or simply
+ * was only in <arch-tegra20/display.h> and nowhere else for no good reason.
+ */
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+	enum win_color_depth_id fmt;	/* Color depth/format */
+	unsigned	bpp;		/* Bits per pixel */
+	phys_addr_t	phys_addr;	/* Physical address in memory */
+	unsigned	x;		/* Horizontal address offset (bytes) */
+	unsigned	y;		/* Veritical address offset (bytes) */
+	unsigned	w;		/* Width of source window */
+	unsigned	h;		/* Height of source window */
+	unsigned	stride;		/* Number of bytes per line */
+	unsigned	out_x;		/* Left edge of output window (col) */
+	unsigned	out_y;		/* Top edge of output window (row) */
+	unsigned	out_w;		/* Width of output window in pixels */
+	unsigned	out_h;		/* Height of output window in pixels */
+};
+#endif
+
+#endif