Add support for Espresso7420 board

From: Thomas Abraham <[email protected]>

The fixed rate clock driver could be used to represent oscillator clocks. Platforms that need to determine the rate of the oscillator clock frequency would require that the fixed rate clock driver be available for use prior to relocation. So add the DM_FLAG_PRE_RELOC property to the driver flags.

Cc Masahiro Yamada <[email protected]>

Cc Simon Glass <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/clk_fixed_rate.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

drivers/clk/clk_fixed_rate.c +1 -1

index 8beda9c..070e568 100644
@@ -54,4 +54,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
        .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
        .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
        .ops = &clk_fixed_rate_ops,
+       .flags = DM_FLAG_PRE_RELOC,
 };
--

1.6.6.rc2

From: Thomas Abraham <[email protected]>

Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver.

Cc Minkyu Kang <[email protected]>

Cc Simon Glass <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/Kconfig                        |    1 +
 drivers/clk/Makefile                       |    1 +
 drivers/clk/exynos/Kconfig                 |   18 +++
 drivers/clk/exynos/Makefile                |    9 +
 drivers/clk/exynos/clk-exynos7420.c        |  227 ++++++++++++++++++++++++++++
 drivers/clk/exynos/clk-pll.c               |   35 +++++
 drivers/clk/exynos/clk-pll.h               |    9 +
 include/dt-bindings/clock/exynos7420-clk.h |  207 +++++++++++++++++++++++++
 8 files changed, 507 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/exynos/Kconfig
 create mode 100644 drivers/clk/exynos/Makefile
 create mode 100644 drivers/clk/exynos/clk-exynos7420.c
 create mode 100644 drivers/clk/exynos/clk-pll.c
 create mode 100644 drivers/clk/exynos/clk-pll.h
 create mode 100644 include/dt-bindings/clock/exynos7420-clk.h

drivers/clk/Kconfig +1 -0

index a98b74b..6eee8eb 100644
@@ -21,5 +21,6 @@ config SPL_CLK
          used as U-Boot proper.
 
 source "drivers/clk/uniphier/Kconfig"
+source "drivers/clk/exynos/Kconfig"
 
 endmenu

drivers/clk/Makefile +1 -0

index c51db15..81fe600 100644
@@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_EXYNOS) += exynos/

drivers/clk/exynos/Kconfig new file +18 -0

new file mode 100644
index 0000000..eb0efa9
@@ -0,0 +1,18 @@
+config CLK_EXYNOS
+       bool
+       select CLK
+       help
+         This enables support for common clock driver API on Samsung
+         Exynos SoCs.
+
+menu "Clock drivers for Exynos SoCs"
+       depends on CLK_EXYNOS
+
+config CLK_EXYNOS7420
+       bool "Clock driver for Samsung's Exynos7420 SoC"
+       default y
+       help
+         This enables common clock driver support for platforms based
+         on Samsung Exynos7420 SoC.
+
+endmenu

drivers/clk/exynos/Makefile new file +9 -0

new file mode 100644
index 0000000..1df10fe
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <[email protected]>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y                          += clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420)   += clk-exynos7420.o

drivers/clk/exynos/clk-exynos7420.c new file +5 -0

new file mode 100644
index 0000000..1feaea4
@@ -0,0 +1,226 @@
+/*
+ * Samsung Exynos7420 clock driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *

drivers/clk/exynos/clk-exynos7420.c new file +12 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIVIDER(reg, shift, mask)      \
+       (((readl(reg) >> shift) & mask) + 1)
+
+struct exynos7420_clk_cmu_topc {
+       unsigned int    rsvd1[68];
+       unsigned int    bus0_pll_con[2];
+       unsigned int    rsvd2[2];
+       unsigned int    bus1_pll_con[2];
+       unsigned int    rsvd3[54];

drivers/clk/exynos/clk-exynos7420.c new file +25 -0

+};
+
+static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+{
+       struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+
+       switch (periph) {
+       case DOUT_SCLK_BUS0_PLL:
+       case SCLK_BUS0_PLL_A:
+       case SCLK_BUS0_PLL_B:
+               return priv->sclk_bus0_pll_a;
+       case DOUT_SCLK_BUS1_PLL:
+       case SCLK_BUS1_PLL_A:
+       case SCLK_BUS1_PLL_B:
+               return priv->sclk_bus1_pll_a;
+       default:
+               return 0;
+       }
+}
+
+static struct clk_ops exynos7420_clk_topc_ops = {
+       .get_periph_rate        = exynos7420_topc_get_periph_rate,
+};
+
+static int exynos7420_clk_topc_probe(struct udevice *dev)

drivers/clk/exynos/clk-exynos7420.c new file +98 -0

+               return -EINVAL;
 
+
+       base = dev_get_addr(dev);
+       if (base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       topc = (struct exynos7420_clk_cmu_topc *)base;
+       priv->topc = topc;
+
+       ret = clk_get_by_index(dev, 0, &clk_dev);
+       if (ret >= 0)
+               priv->fin_freq = clk_get_rate(clk_dev);
+
+       rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
+       if (readl(&topc->mux_sel[1]) & (1 << 16))
+               rate >>= 1;
+       rate /= DIVIDER(&topc->div[3], 0, 0xf);
+       priv->sclk_bus0_pll_a = rate;
+
+       rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
+                       DIVIDER(&topc->div[3], 8, 0xf);
+       priv->sclk_bus1_pll_a = rate;
+
+       return 0;
+}
+
+static const struct udevice_id exynos7420_clk_topc_compat[] = {
+       { .compatible = "samsung,exynos7-clock-topc" },
+       { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_topc) = {
+       .name = "exynos7420-clock-topc",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_topc_compat,
+       .probe = exynos7420_clk_topc_probe,
+       .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+       .ops = &exynos7420_clk_topc_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+};
+
+struct exynos7420_clk_cmu_top0 {
+       unsigned int    rsvd0[128];
+       unsigned int    mux_sel[7];
+       unsigned int    rsvd1[261];
+       unsigned int    div_peric[5];
+};
+
+struct exynos7420_clk_top0_priv {
+       struct exynos7420_clk_cmu_top0 *top0;
+       unsigned long mout_top0_bus0_pll_half;
+       unsigned long sclk_uart2;
+};
+
+static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+{
+       struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+       struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
+
+       switch (periph) {
+       case CLK_SCLK_UART2:
+               return priv->mout_top0_bus0_pll_half /
+                       DIVIDER(&top0->div_peric[3], 8, 0xf);
+       default:
+               return 0;
+       }
+}
+
+static struct clk_ops exynos7420_clk_top0_ops = {
+       .get_periph_rate        = exynos7420_top0_get_periph_rate,
+};
+
+static int exynos7420_clk_top0_probe(struct udevice *dev)
+{
+       struct exynos7420_clk_top0_priv *priv;
+       struct exynos7420_clk_cmu_top0 *top0;
+       struct udevice *clk_dev;
+       fdt_addr_t base;
+       int ret;
+
+       priv = dev_get_priv(dev);
+       if (!priv)
+               return -EINVAL;
+
+       base = dev_get_addr(dev);
+       if (base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       top0 = (struct exynos7420_clk_cmu_top0 *)base;
+       priv->top0 = top0;
+
+       ret = clk_get_by_index(dev, 1, &clk_dev);
+       if (ret >= 0) {
+               priv->mout_top0_bus0_pll_half =
+                       clk_get_periph_rate(clk_dev, ret);
+               if (readl(&top0->mux_sel[1]) & (1 << 16))
+                       priv->mout_top0_bus0_pll_half >>= 1;
+       }

drivers/clk/exynos/clk-exynos7420.c new file +7 -0

+       .name = "exynos7420-clock-top0",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_top0_compat,
+       .probe = exynos7420_clk_top0_probe,
+       .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+       .ops = &exynos7420_clk_top0_ops,
+       .flags = DM_FLAG_PRE_RELOC,

drivers/clk/exynos/clk-exynos7420.c new file +4 -0

+               if (ret >= 0)
+                       return clk_get_periph_rate(clk_dev, ret);
+       default:
+               return 0;

drivers/clk/exynos/clk-exynos7420.c new file +15 -0

+}
+
+static const struct udevice_id exynos7420_clk_peric1_compat[] = {
+       { .compatible = "samsung,exynos7-clock-peric1" },
+       { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_peric1) = {
+       .name = "exynos7420-clock-peric1",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_peric1_compat,
+       .probe = exynos7420_clk_peric1_probe,
+       .ops = &exynos7420_clk_peric1_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+};

drivers/clk/exynos/clk-pll.c new file +33 -0

new file mode 100644
index 0000000..dd11268
@@ -0,0 +1,33 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define PLL145X_MDIV_SHIFT     16
+#define PLL145X_MDIV_MASK      0x3ff
+#define PLL145X_PDIV_SHIFT     8
+#define PLL145X_PDIV_MASK      0x3f
+#define PLL145X_SDIV_SHIFT     0
+#define PLL145X_SDIV_MASK      0x7
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+{
+       unsigned long pll_con1 = readl(con1);
+       unsigned long mdiv, sdiv, pdiv;
+       uint64_t fvco = fin_freq;
+
+       mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+       pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+       sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+       fvco *= mdiv;
+       do_div(fvco, (pdiv << sdiv));
+       return (unsigned long)fvco;
+}

drivers/clk/exynos/clk-pll.h new file +9 -0

new file mode 100644
index 0000000..631d035
@@ -0,0 +1,9 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);

include/dt-bindings/clock/exynos7420-clk.h new file +207 -1

new file mode 100644
index 0000000..10c5586
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS                        1
+#define DOUT_SCLK_BUS0_PLL             2
+#define DOUT_SCLK_BUS1_PLL             3
+#define DOUT_SCLK_CC_PLL               4
+#define DOUT_SCLK_MFC_PLL              5
+#define DOUT_ACLK_CCORE_133            6
+#define DOUT_ACLK_MSCL_532             7
+#define ACLK_MSCL_532                  8
+#define DOUT_SCLK_AUD_PLL              9
+#define FOUT_AUD_PLL                   10
+#define SCLK_AUD_PLL                   11
+#define SCLK_MFC_PLL_B                 12
+#define SCLK_MFC_PLL_A                 13
+#define SCLK_BUS1_PLL_B                        14
+#define SCLK_BUS1_PLL_A                        15
+#define SCLK_BUS0_PLL_B                        16
+#define SCLK_BUS0_PLL_A                        17
+#define SCLK_CC_PLL_B                  18
+#define SCLK_CC_PLL_A                  19
+#define ACLK_CCORE_133                 20
+#define ACLK_PERIS_66                  21
+#define TOPC_NR_CLK                    22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1               1
+#define DOUT_ACLK_PERIC0               2
+#define CLK_SCLK_UART0                 3
+#define CLK_SCLK_UART1                 4
+#define CLK_SCLK_UART2                 5
+#define CLK_SCLK_UART3                 6
+#define CLK_SCLK_SPI0                  7
+#define CLK_SCLK_SPI1                  8
+#define CLK_SCLK_SPI2                  9
+#define CLK_SCLK_SPI3                  10
+#define CLK_SCLK_SPI4                  11
+#define CLK_SCLK_SPDIF                 12
+#define CLK_SCLK_PCM1                  13
+#define CLK_SCLK_I2S1                  14
+#define CLK_ACLK_PERIC0_66             15
+#define CLK_ACLK_PERIC1_66             16
+#define TOP0_NR_CLK                    17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200            1
+#define DOUT_ACLK_FSYS0_200            2
+#define DOUT_SCLK_MMC2                 3
+#define DOUT_SCLK_MMC1                 4
+#define DOUT_SCLK_MMC0                 5
+#define CLK_SCLK_MMC2                  6
+#define CLK_SCLK_MMC1                  7
+#define CLK_SCLK_MMC0                  8
+#define CLK_ACLK_FSYS0_200             9
+#define CLK_ACLK_FSYS1_200             10
+#define CLK_SCLK_PHY_FSYS1             11
+#define CLK_SCLK_PHY_FSYS1_26M         12
+#define MOUT_SCLK_UFSUNIPRO20          13
+#define DOUT_SCLK_UFSUNIPRO20          14
+#define CLK_SCLK_UFSUNIPRO20           15
+#define DOUT_SCLK_PHY_FSYS1            16
+#define DOUT_SCLK_PHY_FSYS1_26M                17
+#define TOP1_NR_CLK                    18
+
+/* CCORE */
+#define PCLK_RTC                       1
+#define CCORE_NR_CLK                   2
+
+/* PERIC0 */
+#define PCLK_UART0                     1
+#define SCLK_UART0                     2
+#define PCLK_HSI2C0                    3
+#define PCLK_HSI2C1                    4
+#define PCLK_HSI2C4                    5
+#define PCLK_HSI2C5                    6
+#define PCLK_HSI2C9                    7
+#define PCLK_HSI2C10                   8
+#define PCLK_HSI2C11                   9
+#define PCLK_PWM                       10
+#define SCLK_PWM                       11
+#define PCLK_ADCIF                     12
+#define PERIC0_NR_CLK                  13
+
+/* PERIC1 */
+#define PCLK_UART1                     1
+#define PCLK_UART2                     2
+#define PCLK_UART3                     3
+#define SCLK_UART1                     4
+#define SCLK_UART2                     5
+#define SCLK_UART3                     6
+#define PCLK_HSI2C2                    7
+#define PCLK_HSI2C3                    8
+#define PCLK_HSI2C6                    9
+#define PCLK_HSI2C7                    10
+#define PCLK_HSI2C8                    11
+#define PCLK_SPI0                      12
+#define PCLK_SPI1                      13
+#define PCLK_SPI2                      14
+#define PCLK_SPI3                      15
+#define PCLK_SPI4                      16
+#define SCLK_SPI0                      17
+#define SCLK_SPI1                      18
+#define SCLK_SPI2                      19
+#define SCLK_SPI3                      20
+#define SCLK_SPI4                      21
+#define PCLK_I2S1                      22
+#define PCLK_PCM1                      23
+#define PCLK_SPDIF                     24
+#define SCLK_I2S1                      25
+#define SCLK_PCM1                      26
+#define SCLK_SPDIF                     27
+#define PERIC1_NR_CLK                  28
+
+/* PERIS */
+#define PCLK_CHIPID                    1
+#define SCLK_CHIPID                    2
+#define PCLK_WDT                       3
+#define PCLK_TMU                       4
+#define SCLK_TMU                       5
+#define PERIS_NR_CLK                   6
+
+/* FSYS0 */
+#define ACLK_MMC2                      1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X    2
+#define ACLK_USBDRD300                 3
+#define SCLK_USBDRD300_SUSPENDCLK      4
+#define SCLK_USBDRD300_REFCLK          5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER         6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER            7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY            8
+#define ACLK_PDMA0                     9
+#define ACLK_PDMA1                     10
+#define FSYS0_NR_CLK                   11
+
+/* FSYS1 */
+#define ACLK_MMC1                      1
+#define ACLK_MMC0                      2
+#define PHYCLK_UFS20_TX0_SYMBOL                3
+#define PHYCLK_UFS20_RX0_SYMBOL                4
+#define PHYCLK_UFS20_RX1_SYMBOL                5
+#define ACLK_UFS20_LINK                        6
+#define SCLK_UFSUNIPRO20_USER          7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER   8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER   9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER   10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY   11
+#define SCLK_COMBO_PHY_EMBEDDED_26M    12
+#define DOUT_PCLK_FSYS1                        13
+#define PCLK_GPIO_FSYS1                        14
+#define MOUT_FSYS1_PHYCLK_SEL1         15
+#define FSYS1_NR_CLK                   16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532          1
+#define DOUT_PCLK_MSCL                 2
+#define ACLK_MSCL_0                    3
+#define ACLK_MSCL_1                    4
+#define ACLK_JPEG                      5
+#define ACLK_G2D                       6
+#define ACLK_LH_ASYNC_SI_MSCL_0                7
+#define ACLK_LH_ASYNC_SI_MSCL_1                8
+#define ACLK_AXI2ACEL_BRIDGE           9
+#define ACLK_XIU_MSCLX_0               10
+#define ACLK_XIU_MSCLX_1               11
+#define ACLK_QE_MSCL_0                 12
+#define ACLK_QE_MSCL_1                 13
+#define ACLK_QE_JPEG                   14
+#define ACLK_QE_G2D                    15
+#define ACLK_PPMU_MSCL_0               16
+#define ACLK_PPMU_MSCL_1               17
+#define ACLK_MSCLNP_133                        18
+#define ACLK_AHB2APB_MSCL0P            19
+#define ACLK_AHB2APB_MSCL1P            20
+
+#define PCLK_MSCL_0                    21
+#define PCLK_MSCL_1                    22
+#define PCLK_JPEG                      23
+#define PCLK_G2D                       24
+#define PCLK_QE_MSCL_0                 25
+#define PCLK_QE_MSCL_1                 26
+#define PCLK_QE_JPEG                   27
+#define PCLK_QE_G2D                    28
+#define PCLK_PPMU_MSCL_0               29
+#define PCLK_PPMU_MSCL_1               30
+#define PCLK_AXI2ACEL_BRIDGE           31
+#define PCLK_PMU_MSCL                  32
+#define MSCL_NR_CLK                    33
+
+/* AUD */
+#define SCLK_I2S                       1
+#define SCLK_PCM                       2
+#define PCLK_I2S                       3
+#define PCLK_PCM                       4
+#define ACLK_ADMA                      5
+#define AUD_NR_CLK                     6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
--

1.6.6.rc2

Hi Thomas,

Quoted 96 lines · Thomas Abraham

From: Thomas Abraham <[email protected]>

Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver.

Cc Minkyu Kang <[email protected]>

Cc Simon Glass <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/Kconfig                        |    1 +
 drivers/clk/Makefile                       |    1 +
 drivers/clk/exynos/Kconfig                 |   18 +++
 drivers/clk/exynos/Makefile                |    9 +
 drivers/clk/exynos/clk-exynos7420.c        |  227 ++++++++++++++++++++++++++++
 drivers/clk/exynos/clk-pll.c               |   35 +++++
 drivers/clk/exynos/clk-pll.h               |    9 +
 include/dt-bindings/clock/exynos7420-clk.h |  207 +++++++++++++++++++++++++
 8 files changed, 507 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/exynos/Kconfig
 create mode 100644 drivers/clk/exynos/Makefile
 create mode 100644 drivers/clk/exynos/clk-exynos7420.c
 create mode 100644 drivers/clk/exynos/clk-pll.c
 create mode 100644 drivers/clk/exynos/clk-pll.h
 create mode 100644 include/dt-bindings/clock/exynos7420-clk.h

drivers/clk/Kconfig +1 -0

index a98b74b..6eee8eb 100644
@@ -21,5 +21,6 @@ config SPL_CLK
          used as U-Boot proper.
 
 source "drivers/clk/uniphier/Kconfig"
+source "drivers/clk/exynos/Kconfig"
 
 endmenu

drivers/clk/Makefile +1 -0

index c51db15..81fe600 100644
@@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_EXYNOS) += exynos/

drivers/clk/exynos/Kconfig new file +18 -0

new file mode 100644
index 0000000..eb0efa9
@@ -0,0 +1,18 @@
+config CLK_EXYNOS
+       bool
+       select CLK
+       help
+         This enables support for common clock driver API on Samsung
+         Exynos SoCs.
+
+menu "Clock drivers for Exynos SoCs"
+       depends on CLK_EXYNOS
+
+config CLK_EXYNOS7420
+       bool "Clock driver for Samsung's Exynos7420 SoC"
+       default y
+       help
+         This enables common clock driver support for platforms based
+         on Samsung Exynos7420 SoC.
+
+endmenu

drivers/clk/exynos/Makefile new file +9 -0

new file mode 100644
index 0000000..1df10fe
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <[email protected]>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y                          += clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420)   += clk-exynos7420.o

drivers/clk/exynos/clk-exynos7420.c new file +5 -0

new file mode 100644
index 0000000..1feaea4
@@ -0,0 +1,226 @@
+/*
+ * Samsung Exynos7420 clock driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *

drivers/clk/exynos/clk-exynos7420.c line 15

Quoted 10 lines

drivers/clk/exynos/clk-exynos7420.c new file +10 -0

+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <clk.h>
+#include "clk-pll.h"
+#include <dt-bindings/clock/exynos7420-clk.h>

Please see include order.

http://www.denx.de/wiki/U-Boot/CodingStyle

Quoted 12 lines

drivers/clk/exynos/clk-exynos7420.c new file +12 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIVIDER(reg, shift, mask)      \
+       (((readl(reg) >> shift) & mask) + 1)
+
+struct exynos7420_clk_cmu_topc {
+       unsigned int    rsvd1[68];
+       unsigned int    bus0_pll_con[2];
+       unsigned int    rsvd2[2];
+       unsigned int    bus1_pll_con[2];
+       unsigned int    rsvd3[54];

drivers/clk/exynos/clk-exynos7420.c line 37

Quoted 10 lines

drivers/clk/exynos/clk-exynos7420.c new file +10 -0

+       unsigned int    mux_sel[6];
+       unsigned int    rsvd4[250];
+       unsigned int    div[4];
+};
+
+struct exynos7420_clk_topc_priv {
+       struct exynos7420_clk_cmu_topc *topc;
+       unsigned long fin_freq;
+       unsigned long sclk_bus0_pll_a;
+       unsigned long sclk_bus1_pll_a;

Comments on these members please.

Quoted 29 lines

drivers/clk/exynos/clk-exynos7420.c new file +29 -0

+};
+
+static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+{
+       struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+
+       switch (periph) {
+       case DOUT_SCLK_BUS0_PLL:
+       case SCLK_BUS0_PLL_A:
+       case SCLK_BUS0_PLL_B:
+               return priv->sclk_bus0_pll_a;
+       case DOUT_SCLK_BUS1_PLL:
+       case SCLK_BUS1_PLL_A:
+       case SCLK_BUS1_PLL_B:
+               return priv->sclk_bus1_pll_a;
+       default:
+               return 0;
+       }
+}
+
+static struct clk_ops exynos7420_clk_topc_ops = {
+       .get_periph_rate        = exynos7420_topc_get_periph_rate,
+};
+
+static int exynos7420_clk_topc_probe(struct udevice *dev)
+{
+       struct exynos7420_clk_topc_priv *priv;
+       struct exynos7420_clk_cmu_topc *topc;
+       struct udevice *clk_dev;

drivers/clk/exynos/clk-exynos7420.c line 72

Quoted 6 lines

drivers/clk/exynos/clk-exynos7420.c new file +6 -0

+       unsigned long rate;
+       fdt_addr_t base;
+       int ret;
+
+       priv = dev_get_priv(dev);
+       if (!priv)

This cannot happen as it is auto-allocated.

Quoted 105 lines

drivers/clk/exynos/clk-exynos7420.c new file +103 -0

+               return -EINVAL;
 
+
+       base = dev_get_addr(dev);
+       if (base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       topc = (struct exynos7420_clk_cmu_topc *)base;
+       priv->topc = topc;
+
+       ret = clk_get_by_index(dev, 0, &clk_dev);
+       if (ret >= 0)
+               priv->fin_freq = clk_get_rate(clk_dev);
+
+       rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
+       if (readl(&topc->mux_sel[1]) & (1 << 16))
+               rate >>= 1;
+       rate /= DIVIDER(&topc->div[3], 0, 0xf);
+       priv->sclk_bus0_pll_a = rate;
+
+       rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
+                       DIVIDER(&topc->div[3], 8, 0xf);
+       priv->sclk_bus1_pll_a = rate;
+
+       return 0;
+}
+
+static const struct udevice_id exynos7420_clk_topc_compat[] = {
+       { .compatible = "samsung,exynos7-clock-topc" },
+       { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_topc) = {
+       .name = "exynos7420-clock-topc",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_topc_compat,
+       .probe = exynos7420_clk_topc_probe,
+       .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+       .ops = &exynos7420_clk_topc_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+};
+
+struct exynos7420_clk_cmu_top0 {
+       unsigned int    rsvd0[128];
+       unsigned int    mux_sel[7];
+       unsigned int    rsvd1[261];
+       unsigned int    div_peric[5];
+};
+
+struct exynos7420_clk_top0_priv {
+       struct exynos7420_clk_cmu_top0 *top0;
+       unsigned long mout_top0_bus0_pll_half;
+       unsigned long sclk_uart2;
+};
+
+static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+{
+       struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+       struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
+
+       switch (periph) {
+       case CLK_SCLK_UART2:
+               return priv->mout_top0_bus0_pll_half /
+                       DIVIDER(&top0->div_peric[3], 8, 0xf);
+       default:
+               return 0;
+       }
+}
+
+static struct clk_ops exynos7420_clk_top0_ops = {
+       .get_periph_rate        = exynos7420_top0_get_periph_rate,
+};
+
+static int exynos7420_clk_top0_probe(struct udevice *dev)
+{
+       struct exynos7420_clk_top0_priv *priv;
+       struct exynos7420_clk_cmu_top0 *top0;
+       struct udevice *clk_dev;
+       fdt_addr_t base;
+       int ret;
+
+       priv = dev_get_priv(dev);
+       if (!priv)
+               return -EINVAL;
+
+       base = dev_get_addr(dev);
+       if (base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       top0 = (struct exynos7420_clk_cmu_top0 *)base;
+       priv->top0 = top0;
+
+       ret = clk_get_by_index(dev, 1, &clk_dev);
+       if (ret >= 0) {
+               priv->mout_top0_bus0_pll_half =
+                       clk_get_periph_rate(clk_dev, ret);
+               if (readl(&top0->mux_sel[1]) & (1 << 16))
+                       priv->mout_top0_bus0_pll_half >>= 1;
+       }
+
+       return 0;
+}
+
+static const struct udevice_id exynos7420_clk_top0_compat[] = {

drivers/clk/exynos/clk-exynos7420.c line 180

Quoted 5 lines

drivers/clk/exynos/clk-exynos7420.c new file +5 -0

+       { .compatible = "samsung,exynos7-clock-top0" },
+       { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_top0) = {

It might be better to put all the U_BOOT_DRIVER() and compatible stuff at the end of the file?

Quoted 8 lines

drivers/clk/exynos/clk-exynos7420.c new file +7 -0

+       .name = "exynos7420-clock-top0",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_top0_compat,
+       .probe = exynos7420_clk_top0_probe,
+       .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+       .ops = &exynos7420_clk_top0_ops,
+       .flags = DM_FLAG_PRE_RELOC,

drivers/clk/exynos/clk-exynos7420.c line 197

Quoted 10 lines

drivers/clk/exynos/clk-exynos7420.c new file +10 -0

+};
+
+static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+{
+       struct udevice *clk_dev;
+       unsigned int ret;
+
+       switch (periph) {
+       case SCLK_UART2:
+               ret = clk_get_by_index(dev, 3, &clk_dev);

Shouldn't this be:

if (ret < 0)
return ret;

Quoted 5 lines

drivers/clk/exynos/clk-exynos7420.c new file +4 -0

+               if (ret >= 0)
+                       return clk_get_periph_rate(clk_dev, ret);
+       default:
+               return 0;

drivers/clk/exynos/clk-exynos7420.c line 211

Quoted 10 lines

drivers/clk/exynos/clk-exynos7420.c new file +10 -0

+       }
+}
+
+static struct clk_ops exynos7420_clk_peric1_ops = {
+       .get_periph_rate        = exynos7420_peric1_get_periph_rate,
+};
+
+static int exynos7420_clk_peric1_probe(struct udevice *dev)
+{
+       return 0;

Then you can omit this function.

Quoted 283 lines

drivers/clk/exynos/clk-exynos7420.c new file +15 -0

+}
+
+static const struct udevice_id exynos7420_clk_peric1_compat[] = {
+       { .compatible = "samsung,exynos7-clock-peric1" },
+       { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_peric1) = {
+       .name = "exynos7420-clock-peric1",
+       .id = UCLASS_CLK,
+       .of_match = exynos7420_clk_peric1_compat,
+       .probe = exynos7420_clk_peric1_probe,
+       .ops = &exynos7420_clk_peric1_ops,
+       .flags = DM_FLAG_PRE_RELOC,
+};

drivers/clk/exynos/clk-pll.c new file +33 -0

new file mode 100644
index 0000000..dd11268
@@ -0,0 +1,33 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define PLL145X_MDIV_SHIFT     16
+#define PLL145X_MDIV_MASK      0x3ff
+#define PLL145X_PDIV_SHIFT     8
+#define PLL145X_PDIV_MASK      0x3f
+#define PLL145X_SDIV_SHIFT     0
+#define PLL145X_SDIV_MASK      0x7
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+{
+       unsigned long pll_con1 = readl(con1);
+       unsigned long mdiv, sdiv, pdiv;
+       uint64_t fvco = fin_freq;
+
+       mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+       pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+       sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+       fvco *= mdiv;
+       do_div(fvco, (pdiv << sdiv));
+       return (unsigned long)fvco;
+}

drivers/clk/exynos/clk-pll.h new file +9 -0

new file mode 100644
index 0000000..631d035
@@ -0,0 +1,9 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+u-boot,dm-pre-reloc
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);

include/dt-bindings/clock/exynos7420-clk.h new file +207 -1

new file mode 100644
index 0000000..10c5586
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS                        1
+#define DOUT_SCLK_BUS0_PLL             2
+#define DOUT_SCLK_BUS1_PLL             3
+#define DOUT_SCLK_CC_PLL               4
+#define DOUT_SCLK_MFC_PLL              5
+#define DOUT_ACLK_CCORE_133            6
+#define DOUT_ACLK_MSCL_532             7
+#define ACLK_MSCL_532                  8
+#define DOUT_SCLK_AUD_PLL              9
+#define FOUT_AUD_PLL                   10
+#define SCLK_AUD_PLL                   11
+#define SCLK_MFC_PLL_B                 12
+#define SCLK_MFC_PLL_A                 13
+#define SCLK_BUS1_PLL_B                        14
+#define SCLK_BUS1_PLL_A                        15
+#define SCLK_BUS0_PLL_B                        16
+#define SCLK_BUS0_PLL_A                        17
+#define SCLK_CC_PLL_B                  18
+#define SCLK_CC_PLL_A                  19
+#define ACLK_CCORE_133                 20
+#define ACLK_PERIS_66                  21
+#define TOPC_NR_CLK                    22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1               1
+#define DOUT_ACLK_PERIC0               2
+#define CLK_SCLK_UART0                 3
+#define CLK_SCLK_UART1                 4
+#define CLK_SCLK_UART2                 5
+#define CLK_SCLK_UART3                 6
+#define CLK_SCLK_SPI0                  7
+#define CLK_SCLK_SPI1                  8
+#define CLK_SCLK_SPI2                  9
+#define CLK_SCLK_SPI3                  10
+#define CLK_SCLK_SPI4                  11
+#define CLK_SCLK_SPDIF                 12
+#define CLK_SCLK_PCM1                  13
+#define CLK_SCLK_I2S1                  14
+#define CLK_ACLK_PERIC0_66             15
+#define CLK_ACLK_PERIC1_66             16
+#define TOP0_NR_CLK                    17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200            1
+#define DOUT_ACLK_FSYS0_200            2
+#define DOUT_SCLK_MMC2                 3
+#define DOUT_SCLK_MMC1                 4
+#define DOUT_SCLK_MMC0                 5
+#define CLK_SCLK_MMC2                  6
+#define CLK_SCLK_MMC1                  7
+#define CLK_SCLK_MMC0                  8
+#define CLK_ACLK_FSYS0_200             9
+#define CLK_ACLK_FSYS1_200             10
+#define CLK_SCLK_PHY_FSYS1             11
+#define CLK_SCLK_PHY_FSYS1_26M         12
+#define MOUT_SCLK_UFSUNIPRO20          13
+#define DOUT_SCLK_UFSUNIPRO20          14
+#define CLK_SCLK_UFSUNIPRO20           15
+#define DOUT_SCLK_PHY_FSYS1            16
+#define DOUT_SCLK_PHY_FSYS1_26M                17
+#define TOP1_NR_CLK                    18
+
+/* CCORE */
+#define PCLK_RTC                       1
+#define CCORE_NR_CLK                   2
+
+/* PERIC0 */
+#define PCLK_UART0                     1
+#define SCLK_UART0                     2
+#define PCLK_HSI2C0                    3
+#define PCLK_HSI2C1                    4
+#define PCLK_HSI2C4                    5
+#define PCLK_HSI2C5                    6
+#define PCLK_HSI2C9                    7
+#define PCLK_HSI2C10                   8
+#define PCLK_HSI2C11                   9
+#define PCLK_PWM                       10
+#define SCLK_PWM                       11
+#define PCLK_ADCIF                     12
+#define PERIC0_NR_CLK                  13
+
+/* PERIC1 */
+#define PCLK_UART1                     1
+#define PCLK_UART2                     2
+#define PCLK_UART3                     3
+#define SCLK_UART1                     4
+#define SCLK_UART2                     5
+#define SCLK_UART3                     6
+#define PCLK_HSI2C2                    7
+#define PCLK_HSI2C3                    8
+#define PCLK_HSI2C6                    9
+#define PCLK_HSI2C7                    10
+#define PCLK_HSI2C8                    11
+#define PCLK_SPI0                      12
+#define PCLK_SPI1                      13
+#define PCLK_SPI2                      14
+#define PCLK_SPI3                      15
+#define PCLK_SPI4                      16
+#define SCLK_SPI0                      17
+#define SCLK_SPI1                      18
+#define SCLK_SPI2                      19
+#define SCLK_SPI3                      20
+#define SCLK_SPI4                      21
+#define PCLK_I2S1                      22
+#define PCLK_PCM1                      23
+#define PCLK_SPDIF                     24
+#define SCLK_I2S1                      25
+#define SCLK_PCM1                      26
+#define SCLK_SPDIF                     27
+#define PERIC1_NR_CLK                  28
+
+/* PERIS */
+#define PCLK_CHIPID                    1
+#define SCLK_CHIPID                    2
+#define PCLK_WDT                       3
+#define PCLK_TMU                       4
+#define SCLK_TMU                       5
+#define PERIS_NR_CLK                   6
+
+/* FSYS0 */
+#define ACLK_MMC2                      1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X    2
+#define ACLK_USBDRD300                 3
+#define SCLK_USBDRD300_SUSPENDCLK      4
+#define SCLK_USBDRD300_REFCLK          5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER         6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER            7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY            8
+#define ACLK_PDMA0                     9
+#define ACLK_PDMA1                     10
+#define FSYS0_NR_CLK                   11
+
+/* FSYS1 */
+#define ACLK_MMC1                      1
+#define ACLK_MMC0                      2
+#define PHYCLK_UFS20_TX0_SYMBOL                3
+#define PHYCLK_UFS20_RX0_SYMBOL                4
+#define PHYCLK_UFS20_RX1_SYMBOL                5
+#define ACLK_UFS20_LINK                        6
+#define SCLK_UFSUNIPRO20_USER          7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER   8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER   9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER   10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY   11
+#define SCLK_COMBO_PHY_EMBEDDED_26M    12
+#define DOUT_PCLK_FSYS1                        13
+#define PCLK_GPIO_FSYS1                        14
+#define MOUT_FSYS1_PHYCLK_SEL1         15
+#define FSYS1_NR_CLK                   16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532          1
+#define DOUT_PCLK_MSCL                 2
+#define ACLK_MSCL_0                    3
+#define ACLK_MSCL_1                    4
+#define ACLK_JPEG                      5
+#define ACLK_G2D                       6
+#define ACLK_LH_ASYNC_SI_MSCL_0                7
+#define ACLK_LH_ASYNC_SI_MSCL_1                8
+#define ACLK_AXI2ACEL_BRIDGE           9
+#define ACLK_XIU_MSCLX_0               10
+#define ACLK_XIU_MSCLX_1               11
+#define ACLK_QE_MSCL_0                 12
+#define ACLK_QE_MSCL_1                 13
+#define ACLK_QE_JPEG                   14
+#define ACLK_QE_G2D                    15
+#define ACLK_PPMU_MSCL_0               16
+#define ACLK_PPMU_MSCL_1               17
+#define ACLK_MSCLNP_133                        18
+#define ACLK_AHB2APB_MSCL0P            19
+#define ACLK_AHB2APB_MSCL1P            20
+
+#define PCLK_MSCL_0                    21
+#define PCLK_MSCL_1                    22
+#define PCLK_JPEG                      23
+#define PCLK_G2D                       24
+#define PCLK_QE_MSCL_0                 25
+#define PCLK_QE_MSCL_1                 26
+#define PCLK_QE_JPEG                   27
+#define PCLK_QE_G2D                    28
+#define PCLK_PPMU_MSCL_0               29
+#define PCLK_PPMU_MSCL_1               30
+#define PCLK_AXI2ACEL_BRIDGE           31
+#define PCLK_PMU_MSCL                  32
+#define MSCL_NR_CLK                    33
+
+/* AUD */
+#define SCLK_I2S                       1
+#define SCLK_PCM                       2
+#define PCLK_I2S                       3
+#define PCLK_PCM                       4
+#define ACLK_ADMA                      5
+#define AUD_NR_CLK                     6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
--

Quoted 2 lines

1.6.6.rc2

Regards,
Simon

From: Thomas Abraham <[email protected]>

The port id, if not specified in the device node, can be obtained from the alias of the device node listed in the aliases node.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/serial/serial_s5p.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

drivers/serial/serial_s5p.c +0 -0

index feba467..038d9b6 100644

drivers/serial/serial_s5p.c +0 -1

        return 0;
 }
--

1.6.6.rc2

From: Thomas Abraham <[email protected]>

On Exynos platforms that support clock driver API, allow the driver to use clock api get the SCLK clock rate.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/serial/serial_s5p.c |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

From: Thomas Abraham <[email protected]>

The existing Exynos 32-bit platform support needs to be realigned in order to support newer 64-bit Exynos platforms. The driver model will be utlized for drivers on the 64-bit Exynos platforms and so some of the older platform support code would not be required for the newer 64-bit Exynos platforms.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-exynos/Kconfig             |   14 ++++++++++++++
 arch/arm/mach-exynos/Makefile            |    7 +++++--
 arch/arm/mach-exynos/include/mach/cpu.h  |    2 +-
 arch/arm/mach-exynos/include/mach/gpio.h |    2 +-
 arch/arm/mach-exynos/soc.c               |    2 ++
 6 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/Kconfig +0 -1

index b82ec18..ee22a3c 100644
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
-	select CPU_V7
 	select DM
 	select DM_SPI_FLASH
 	select DM_SERIAL

arch/arm/mach-exynos/Kconfig +12 -0

index a6a7597..acab947 100644
@@ -7,30 +7,38 @@ choice
 config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
+	select CPU_V7
 	select OF_CONTROL
 
 config TARGET_TRATS
 	bool "Exynos4210 Trats board"
+	select CPU_V7
 
 config TARGET_S5PC210_UNIVERSAL
 	bool "EXYNOS4210 Universal C210 board"
+	select CPU_V7
 
 config TARGET_ORIGEN
 	bool "Exynos4412 Origen board"
+	select CPU_V7
 	select SUPPORT_SPL
 
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
+	select CPU_V7
 
 config TARGET_ODROID
 	bool "Exynos4412 Odroid board"
+	select CPU_V7
 
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
+	select CPU_V7
 	select OF_CONTROL
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
+	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL

@@ -38,32 +46,38 @@ config TARGET_ARNDALE
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
+	select CPU_V7
 	select SUPPORT_SPL
 	select OF_CONTROL
 
 config TARGET_SNOW
 	bool "Snow board"
+	select CPU_V7
 	select SUPPORT_SPL
 	select OF_CONTROL
 
 config TARGET_SPRING
 	bool "Spring board"
+	select CPU_V7
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
+	select CPU_V7
 	select SUPPORT_SPL
 	select OF_CONTROL
 
 config TARGET_PEACH_PI

arch/arm/mach-exynos/Makefile +1 -1

 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 

@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y	+= spl_boot.o
+obj-y	+= spl_boot.o tzpc.o
 obj-y	+= lowlevel_init.o
 endif

arch/arm/mach-exynos/include/mach/cpu.h +1 -1

index 14a1692..f12e3d6 100644
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
 IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)				\
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
 	samsung_get_base_##device(void) \
 {								\
 	if (cpu_is_exynos4()) {				\

arch/arm/mach-exynos/include/mach/gpio.h +1 -1

index 7fc8e61..81363bd 100644
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
 };
 
 struct gpio_info {
-	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned long reg_addr;	/* Address of register for this part */
 	unsigned int max_gpio;	/* Maximum GPIO in this part */
 };
 

arch/arm/mach-exynos/soc.c +0 -0

index 0f116b1..5cea5ed 100644

Dear Thomas Abraham,

Quoted 107 lines · Thomas Abraham

From: Thomas Abraham <[email protected]>

The existing Exynos 32-bit platform support needs to be realigned in order to support newer 64-bit Exynos platforms. The driver model will be utlized for drivers on the 64-bit Exynos platforms and so some of the older platform support code would not be required for the newer 64-bit Exynos platforms.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-exynos/Kconfig             |   14 ++++++++++++++
 arch/arm/mach-exynos/Makefile            |    7 +++++--
 arch/arm/mach-exynos/include/mach/cpu.h  |    2 +-
 arch/arm/mach-exynos/include/mach/gpio.h |    2 +-
 arch/arm/mach-exynos/soc.c               |    2 ++
 6 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/Kconfig +0 -1

index b82ec18..ee22a3c 100644
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
      bool "Samsung EXYNOS"
-     select CPU_V7
      select DM
      select DM_SPI_FLASH
      select DM_SERIAL

arch/arm/mach-exynos/Kconfig +13 -0

index a6a7597..acab947 100644
@@ -7,30 +7,38 @@ choice
 config TARGET_SMDKV310
      select SUPPORT_SPL
      bool "Exynos4210 SMDKV310 board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_TRATS
      bool "Exynos4210 Trats board"
+     select CPU_V7
 
 config TARGET_S5PC210_UNIVERSAL
      bool "EXYNOS4210 Universal C210 board"
+     select CPU_V7
 
 config TARGET_ORIGEN
      bool "Exynos4412 Origen board"
+     select CPU_V7
      select SUPPORT_SPL
 
 config TARGET_TRATS2
      bool "Exynos4412 Trat2 board"
+     select CPU_V7
 
 config TARGET_ODROID
      bool "Exynos4412 Odroid board"
+     select CPU_V7
 
 config TARGET_ODROID_XU3
      bool "Exynos5422 Odroid board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_ARNDALE
      bool "Exynos5250 Arndale board"
+     select CPU_V7
      select CPU_V7_HAS_NONSEC
      select CPU_V7_HAS_VIRT
      select SUPPORT_SPL

@@ -38,32 +46,38 @@ config TARGET_ARNDALE
 
 config TARGET_SMDK5250
      bool "SMDK5250 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SNOW
      bool "Snow board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SPRING
      bool "Spring board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
      select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
      bool "SMDK5420 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_PEACH_PI
      bool "Peach Pi board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 

arch/arm/mach-exynos/Kconfig config TARGET_ARNDALE · line 82

Quoted 5 lines

arch/arm/mach-exynos/Kconfig +1 -0

 config TARGET_PEACH_PIT
      bool "Peach Pit board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL

I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64? What do you think?

Quoted 10 lines

arch/arm/mach-exynos/Makefile +0 -0

index 8542f89..be5912e 100644
@@ -5,7 +5,8 @@
 # SPDX-License-Identifier:   GPL-2.0+
 #
 

arch/arm/mach-exynos/Makefile line 9

Quoted 3 lines

arch/arm/mach-exynos/Makefile +2 -1

-obj-y        += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y        += soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o

soc.o, duplicated?

Quoted 44 lines

arch/arm/mach-exynos/Makefile +1 -1

 obj-$(CONFIG_EXYNOS5420)     += sec_boot.o
 

@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)        += clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)        += dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y        += spl_boot.o
+obj-y        += spl_boot.o tzpc.o
 obj-y        += lowlevel_init.o
 endif

arch/arm/mach-exynos/include/mach/cpu.h +1 -1

index 14a1692..f12e3d6 100644
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
 IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)                           \
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
      samsung_get_base_##device(void) \
 {                                                            \
      if (cpu_is_exynos4()) {                         \

arch/arm/mach-exynos/include/mach/gpio.h +1 -1

index 7fc8e61..81363bd 100644
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
 };
 
 struct gpio_info {
-     unsigned int reg_addr;  /* Address of register for this part */
+     unsigned long reg_addr; /* Address of register for this part */
      unsigned int max_gpio;  /* Maximum GPIO in this part */
 };
 

arch/arm/mach-exynos/soc.c +0 -0

index 0f116b1..5cea5ed 100644
@@ -11,7 +11,9 @@
 

arch/arm/mach-exynos/soc.c line 16

Quoted 5 lines

arch/arm/mach-exynos/soc.c +2 -0

 void reset_cpu(ulong addr)
 {
+#ifndef CONFIG_OF_CONTROL
      writel(0x1, samsung_get_base_swreset());
+#endif

Is it related change?

arch/arm/mach-exynos/soc.c line 19

Quoted 5 lines

arch/arm/mach-exynos/soc.c +0 -0

 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF

Thanks,
Minkyu Kang.

Hi Mr. Kang,

Quoted 110 lines · Minkyu Kang

Dear Thomas Abraham,

Quoted 107 lines · Thomas Abraham

From: Thomas Abraham <[email protected]>

The existing Exynos 32-bit platform support needs to be realigned in order to support newer 64-bit Exynos platforms. The driver model will be utlized for drivers on the 64-bit Exynos platforms and so some of the older platform support code would not be required for the newer 64-bit Exynos platforms.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-exynos/Kconfig             |   14 ++++++++++++++
 arch/arm/mach-exynos/Makefile            |    7 +++++--
 arch/arm/mach-exynos/include/mach/cpu.h  |    2 +-
 arch/arm/mach-exynos/include/mach/gpio.h |    2 +-
 arch/arm/mach-exynos/soc.c               |    2 ++
 6 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/Kconfig +0 -1

index b82ec18..ee22a3c 100644
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
      bool "Samsung EXYNOS"
-     select CPU_V7
      select DM
      select DM_SPI_FLASH
      select DM_SERIAL

arch/arm/mach-exynos/Kconfig +13 -0

index a6a7597..acab947 100644
@@ -7,30 +7,38 @@ choice
 config TARGET_SMDKV310
      select SUPPORT_SPL
      bool "Exynos4210 SMDKV310 board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_TRATS
      bool "Exynos4210 Trats board"
+     select CPU_V7
 
 config TARGET_S5PC210_UNIVERSAL
      bool "EXYNOS4210 Universal C210 board"
+     select CPU_V7
 
 config TARGET_ORIGEN
      bool "Exynos4412 Origen board"
+     select CPU_V7
      select SUPPORT_SPL
 
 config TARGET_TRATS2
      bool "Exynos4412 Trat2 board"
+     select CPU_V7
 
 config TARGET_ODROID
      bool "Exynos4412 Odroid board"
+     select CPU_V7
 
 config TARGET_ODROID_XU3
      bool "Exynos5422 Odroid board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_ARNDALE
      bool "Exynos5250 Arndale board"
+     select CPU_V7
      select CPU_V7_HAS_NONSEC
      select CPU_V7_HAS_VIRT
      select SUPPORT_SPL

@@ -38,32 +46,38 @@ config TARGET_ARNDALE
 
 config TARGET_SMDK5250
      bool "SMDK5250 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SNOW
      bool "Snow board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SPRING
      bool "Spring board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
      select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
      bool "SMDK5420 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_PEACH_PI
      bool "Peach Pi board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 

Quoted 8 lines

arch/arm/mach-exynos/Kconfig config TARGET_ARNDALE · line 82

Quoted 5 lines

arch/arm/mach-exynos/Kconfig +1 -0

 config TARGET_PEACH_PIT
      bool "Peach Pit board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL

I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64? What do you think?

I was infact thinking to avoid adding a new ARCH type as much as possible and reuse ARCH_EXYNOS for 64-bit as well. Eventually, the code in mach-exynos has to move into respective driver folders (atleast for ARM64 platforms) and have as little as possible in mach-exynos directory.

Hi,

Quoted 122 lines · Thomas Abraham

Hi Mr. Kang,

Quoted 110 lines · Minkyu Kang

Dear Thomas Abraham,

Quoted 107 lines · Thomas Abraham

From: Thomas Abraham <[email protected]>

The existing Exynos 32-bit platform support needs to be realigned in order to support newer 64-bit Exynos platforms. The driver model will be utlized for drivers on the 64-bit Exynos platforms and so some of the older platform support code would not be required for the newer 64-bit Exynos platforms.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-exynos/Kconfig             |   14 ++++++++++++++
 arch/arm/mach-exynos/Makefile            |    7 +++++--
 arch/arm/mach-exynos/include/mach/cpu.h  |    2 +-
 arch/arm/mach-exynos/include/mach/gpio.h |    2 +-
 arch/arm/mach-exynos/soc.c               |    2 ++
 6 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/Kconfig +0 -1

index b82ec18..ee22a3c 100644
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
      bool "Samsung EXYNOS"
-     select CPU_V7
      select DM
      select DM_SPI_FLASH
      select DM_SERIAL

arch/arm/mach-exynos/Kconfig +13 -0

index a6a7597..acab947 100644
@@ -7,30 +7,38 @@ choice
 config TARGET_SMDKV310
      select SUPPORT_SPL
      bool "Exynos4210 SMDKV310 board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_TRATS
      bool "Exynos4210 Trats board"
+     select CPU_V7
 
 config TARGET_S5PC210_UNIVERSAL
      bool "EXYNOS4210 Universal C210 board"
+     select CPU_V7
 
 config TARGET_ORIGEN
      bool "Exynos4412 Origen board"
+     select CPU_V7
      select SUPPORT_SPL
 
 config TARGET_TRATS2
      bool "Exynos4412 Trat2 board"
+     select CPU_V7
 
 config TARGET_ODROID
      bool "Exynos4412 Odroid board"
+     select CPU_V7
 
 config TARGET_ODROID_XU3
      bool "Exynos5422 Odroid board"
+     select CPU_V7
      select OF_CONTROL
 
 config TARGET_ARNDALE
      bool "Exynos5250 Arndale board"
+     select CPU_V7
      select CPU_V7_HAS_NONSEC
      select CPU_V7_HAS_VIRT
      select SUPPORT_SPL

@@ -38,32 +46,38 @@ config TARGET_ARNDALE
 
 config TARGET_SMDK5250
      bool "SMDK5250 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SNOW
      bool "Snow board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_SPRING
      bool "Spring board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
      select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
      bool "SMDK5420 board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 
 config TARGET_PEACH_PI
      bool "Peach Pi board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL
 

Quoted 8 lines

arch/arm/mach-exynos/Kconfig config TARGET_ARNDALE · line 82

Quoted 5 lines

arch/arm/mach-exynos/Kconfig +1 -0

 config TARGET_PEACH_PIT
      bool "Peach Pit board"
+     select CPU_V7
      select SUPPORT_SPL
      select OF_CONTROL

I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64? What do you think?

Quoted 5 lines

I was infact thinking to avoid adding a new ARCH type as much as possible and reuse ARCH_EXYNOS for 64-bit as well. Eventually, the code in mach-exynos has to move into respective driver folders (atleast for ARM64 platforms) and have as little as possible in mach-exynos directory.

I understood what you want.
But I think, we can reuse mach-exynos code even if we make new ARCH type. And the cpu type should have a dependency with ARCH, not boards. I don't believe that we should add a cpu type to every boards. Please consider again.

Thanks,
Minkyu Kang.

From: Thomas Abraham <[email protected]>

The existing Exynos 32-bit platform support needs to be realigned in order to support newer 64-bit Exynos platforms. The driver model will be utlized for drivers on the 64-bit Exynos platforms and so some of the older platform support code would not be required for the newer 64-bit Exynos platforms.

Cc Minkyu Kang <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-exynos/Kconfig             |   14 ++++++++++++++
 arch/arm/mach-exynos/Makefile            |    5 +++--
 arch/arm/mach-exynos/include/mach/cpu.h  |    2 +-
 arch/arm/mach-exynos/include/mach/gpio.h |    2 +-
 arch/arm/mach-exynos/soc.c               |    2 ++
 6 files changed, 21 insertions(+), 5 deletions(-)

arch/arm/Kconfig +0 -1

index b82ec18..ee22a3c 100644
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
        bool "Samsung EXYNOS"
-       select CPU_V7
        select DM
        select DM_SPI_FLASH
        select DM_SERIAL

arch/arm/mach-exynos/Kconfig +14 -0

index a6a7597..acab947 100644
@@ -7,30 +7,38 @@ choice
 config TARGET_SMDKV310
        select SUPPORT_SPL
        bool "Exynos4210 SMDKV310 board"
+       select CPU_V7
        select OF_CONTROL
 
 config TARGET_TRATS
        bool "Exynos4210 Trats board"
+       select CPU_V7
 
 config TARGET_S5PC210_UNIVERSAL
        bool "EXYNOS4210 Universal C210 board"
+       select CPU_V7
 
 config TARGET_ORIGEN
        bool "Exynos4412 Origen board"
+       select CPU_V7
        select SUPPORT_SPL
 
 config TARGET_TRATS2
        bool "Exynos4412 Trat2 board"
+       select CPU_V7
 
 config TARGET_ODROID
        bool "Exynos4412 Odroid board"
+       select CPU_V7
 
 config TARGET_ODROID_XU3
        bool "Exynos5422 Odroid board"
+       select CPU_V7
        select OF_CONTROL
 
 config TARGET_ARNDALE
        bool "Exynos5250 Arndale board"
+       select CPU_V7
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
        select SUPPORT_SPL

@@ -38,32 +46,38 @@ config TARGET_ARNDALE
 
 config TARGET_SMDK5250
        bool "SMDK5250 board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
 
 config TARGET_SNOW
        bool "Snow board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
 
 config TARGET_SPRING
        bool "Spring board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
        select SPL_DISABLE_OF_CONTROL
 
 config TARGET_SMDK5420
        bool "SMDK5420 board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
 
 config TARGET_PEACH_PI
        bool "Peach Pi board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
 
 config TARGET_PEACH_PIT
        bool "Peach Pit board"
+       select CPU_V7
        select SUPPORT_SPL
        select OF_CONTROL
 

arch/arm/mach-exynos/Makefile +3 -2

index 8542f89..f3c07b7 100644
@@ -5,7 +5,8 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y  += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y  += soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
 
 obj-$(CONFIG_EXYNOS5420)       += sec_boot.o
 

@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)  += clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)  += dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y  += spl_boot.o
+obj-y  += spl_boot.o tzpc.o
 obj-y  += lowlevel_init.o
 endif

arch/arm/mach-exynos/include/mach/cpu.h +1 -1

index 14a1692..f12e3d6 100644
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
 IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)                             \
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
        samsung_get_base_##device(void) \
 {                                                              \
        if (cpu_is_exynos4()) {                         \

arch/arm/mach-exynos/include/mach/gpio.h +1 -1

index 7fc8e61..81363bd 100644
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
 };
 
 struct gpio_info {
-       unsigned int reg_addr;  /* Address of register for this part */
+       unsigned long reg_addr; /* Address of register for this part */
        unsigned int max_gpio;  /* Maximum GPIO in this part */
 };
 

arch/arm/mach-exynos/soc.c +2 -1

index 0f116b1..737a8dd 100644
@@ -11,7 +11,9 @@
 
 void reset_cpu(ulong addr)
 {
+#ifdef CONFIG_CPU_V7
        writel(0x1, samsung_get_base_swreset());
+#endif
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
--

1.6.6.rc2

From: Thomas Abraham <[email protected]>

Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57 and four Cortex-A53 CPUs and includes various peripheral controllers.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/dts/exynos7420.dtsi        |   82 ++++++++++++++++++++++++
 arch/arm/mach-exynos/Kconfig        |   11 +++
 arch/arm/mach-exynos/Makefile       |    1 +
 arch/arm/mach-exynos/mmu-arm64.c    |   35 ++++++++++
 arch/arm/mach-exynos/soc.c          |    8 +++
 include/configs/espresso7420.h      |   35 ++++++++++
 include/configs/exynos7420-common.h |  117 +++++++++++++++++++++++++++++++++++
 7 files changed, 289 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/exynos7420.dtsi
 create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
 create mode 100644 include/configs/espresso7420.h
 create mode 100644 include/configs/exynos7420-common.h

arch/arm/dts/exynos7420.dtsi new file +82 -0

new file mode 100644
index 0000000..990f8a1
@@ -0,0 +1,82 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+       compatible = "samsung,exynos7420";
+
+       fin_pll: xxti {
+               compatible = "fixed-clock";
+               clock-output-names = "fin_pll";
+               u-boot,dm-pre-reloc;
+               #clock-cells = <0>;
+       };
+
+       clock_topc: clock-controller at 10570000 {
+               compatible = "samsung,exynos7-clock-topc";
+               reg = <0x10570000 0x10000>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>;
+               clock-names = "fin_pll";
+       };
+
+       clock_top0: clock-controller at 105d0000 {
+               compatible = "samsung,exynos7-clock-top0";
+               reg = <0x105d0000 0xb000>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+                        <&clock_topc DOUT_SCLK_BUS1_PLL>,
+                        <&clock_topc DOUT_SCLK_CC_PLL>,
+                        <&clock_topc DOUT_SCLK_MFC_PLL>;
+               clock-names = "fin_pll", "dout_sclk_bus0_pll",
+                             "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+                             "dout_sclk_mfc_pll";
+       };
+
+       clock_peric1: clock-controller at 14c80000 {
+               compatible = "samsung,exynos7-clock-peric1";
+               reg = <0x14c80000 0xd00>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+                        <&clock_top0 CLK_SCLK_UART1>,
+                        <&clock_top0 CLK_SCLK_UART2>,
+                        <&clock_top0 CLK_SCLK_UART3>;
+               clock-names = "fin_pll", "dout_aclk_peric1_66",
+                             "sclk_uart1", "sclk_uart2", "sclk_uart3";
+       };
+
+       pinctrl at 13470000 {
+               compatible = "samsung,exynos7420-pinctrl";
+               reg = <0x13470000 0x1000>;
+               u-boot,dm-pre-reloc;
+
+               serial2_bus: serial2-bus {
+                       samsung,pins = "gpd1-4", "gpd1-5";
+                       samsung,pin-function = <2>;
+                       samsung,pin-pud = <3>;
+                       samsung,pin-drv = <0>;
+               };
+       };
+
+       serial at 14C30000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x14C30000 0x100>;
+               u-boot,dm-pre-reloc;
+               clocks = <&clock_peric1 PCLK_UART2>,
+                        <&clock_peric1 SCLK_UART2>;
+               clock-names = "uart", "clk_uart_baud0";
+               pinctrl-names = "default";
+               pinctrl-0 = <&serial2_bus>;
+       };
+};

arch/arm/mach-exynos/Kconfig +11 -0

index acab947..52a5a30 100644
@@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
        select SUPPORT_SPL
        select OF_CONTROL
 
+config  TARGET_ESPRESSO7420
+       bool "ESPRESSO7420 board"
+       select ARM64
+       select SUPPORT_SPL
+       select OF_CONTROL
+       select SPL_DISABLE_OF_CONTROL
+       select PINCTRL
+       select PINCTRL_EXYNOS7420
+       select CLK_EXYNOS
+
 endchoice
 
 config SYS_SOC

@@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"
 source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
 
 endif

arch/arm/mach-exynos/Makefile +1 -0

index be5912e..a238a98 100644
@@ -7,6 +7,7 @@
 
 obj-y  += soc.o
 obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
+obj-$(CONFIG_ARM64)    += mmu-arm64.o
 
 obj-$(CONFIG_EXYNOS5420)       += sec_boot.o
 

arch/arm/mach-exynos/mmu-arm64.c new file +35 -0

new file mode 100644
index 0000000..ba6d99d
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+       {
+               .base   = 0x10000000UL,
+               .size   = 0x10000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                               PTE_BLOCK_NON_SHARE |
+                               PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+       }, {
+               .base   = 0x40000000UL,
+               .size   = 0x80000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                               PTE_BLOCK_INNER_SHARE,
+       }, {
+               /* List terminator */
+               .base   = 0,
+               .size   = 0,
+               .attrs  = 0,
+       },
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif

arch/arm/mach-exynos/soc.c +8 -0

index 5cea5ed..0706f5d 100644
@@ -23,3 +23,11 @@ void enable_caches(void)
        dcache_enable();
 }
 #endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+       armv8_switch_to_el2();
+       armv8_switch_to_el1();
+}
+#endif

include/configs/espresso7420.h new file +15 -0

new file mode 100644
index 0000000..2af33e7
@@ -0,0 +1,35 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+

include/configs/espresso7420.h new file +10 -0

+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING    " for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS   8
+#define SDRAM_BANK_SIZE                (256UL << 20UL) /* 256 MB */
+
+#endif /* __CONFIG_ESPRESSO7420_H */

include/configs/exynos7420-common.h new file +37 -0

new file mode 100644
index 0000000..9a7e193
@@ -0,0 +1,117 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG                 /* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420              /* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>              /* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              1024    /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE                        115200
+

include/configs/exynos7420-common.h new file +25 -0

+
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE               0x02100000
+#define CONFIG_IRAM_SIZE               0x58000
+#define CONFIG_IRAM_END                        (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT              0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3           (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE      SDRAM_BANK_SIZE

include/configs/exynos7420-common.h new file +35 -1

+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE        (16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+       "bootm_size=0x10000000\0" \
+       "kernel_addr_r=0x42000000\0" \
+       "fdt_addr_r=0x43000000\0" \
+       "ramdisk_addr_r=0x43300000\0" \
+       "scriptaddr=0x50000000\0" \
+       "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+       "stdin=serial\0" \
+       "stdout=serial\0" \
+       "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       EXYNOS_DEVICE_SETTINGS \
+       EXYNOS_FDTFILE_SETTING \
+       MEM_LAYOUT_ENV_SETTINGS
+
+#endif /* __CONFIG_EXYNOS7420_COMMON_H */
--

1.6.6.rc2

Hi Thomas,

Quoted 6 lines · Thomas Abraham

From: Thomas Abraham <[email protected]>

Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57 and four Cortex-A53 CPUs and includes various peripheral controllers.

Signed-off-by Thomas Abraham <[email protected]>

Quoted 14 lines

---
 arch/arm/dts/exynos7420.dtsi        |   82 ++++++++++++++++++++++++
 arch/arm/mach-exynos/Kconfig        |   11 +++
 arch/arm/mach-exynos/Makefile       |    1 +
 arch/arm/mach-exynos/mmu-arm64.c    |   35 ++++++++++
 arch/arm/mach-exynos/soc.c          |    8 +++
 include/configs/espresso7420.h      |   35 ++++++++++
 include/configs/exynos7420-common.h |  117 +++++++++++++++++++++++++++++++++++
 7 files changed, 289 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/exynos7420.dtsi
 create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
 create mode 100644 include/configs/espresso7420.h
 create mode 100644 include/configs/exynos7420-common.h

Please see below:

Reviewed-by Simon Glass <[email protected]>

Quoted 211 lines

arch/arm/dts/exynos7420.dtsi new file +82 -0

new file mode 100644
index 0000000..990f8a1
@@ -0,0 +1,82 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+       compatible = "samsung,exynos7420";
+
+       fin_pll: xxti {
+               compatible = "fixed-clock";
+               clock-output-names = "fin_pll";
+               u-boot,dm-pre-reloc;
+               #clock-cells = <0>;
+       };
+
+       clock_topc: clock-controller at 10570000 {
+               compatible = "samsung,exynos7-clock-topc";
+               reg = <0x10570000 0x10000>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>;
+               clock-names = "fin_pll";
+       };
+
+       clock_top0: clock-controller at 105d0000 {
+               compatible = "samsung,exynos7-clock-top0";
+               reg = <0x105d0000 0xb000>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+                        <&clock_topc DOUT_SCLK_BUS1_PLL>,
+                        <&clock_topc DOUT_SCLK_CC_PLL>,
+                        <&clock_topc DOUT_SCLK_MFC_PLL>;
+               clock-names = "fin_pll", "dout_sclk_bus0_pll",
+                             "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+                             "dout_sclk_mfc_pll";
+       };
+
+       clock_peric1: clock-controller at 14c80000 {
+               compatible = "samsung,exynos7-clock-peric1";
+               reg = <0x14c80000 0xd00>;
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+                        <&clock_top0 CLK_SCLK_UART1>,
+                        <&clock_top0 CLK_SCLK_UART2>,
+                        <&clock_top0 CLK_SCLK_UART3>;
+               clock-names = "fin_pll", "dout_aclk_peric1_66",
+                             "sclk_uart1", "sclk_uart2", "sclk_uart3";
+       };
+
+       pinctrl at 13470000 {
+               compatible = "samsung,exynos7420-pinctrl";
+               reg = <0x13470000 0x1000>;
+               u-boot,dm-pre-reloc;
+
+               serial2_bus: serial2-bus {
+                       samsung,pins = "gpd1-4", "gpd1-5";
+                       samsung,pin-function = <2>;
+                       samsung,pin-pud = <3>;
+                       samsung,pin-drv = <0>;
+               };
+       };
+
+       serial at 14C30000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x14C30000 0x100>;
+               u-boot,dm-pre-reloc;
+               clocks = <&clock_peric1 PCLK_UART2>,
+                        <&clock_peric1 SCLK_UART2>;
+               clock-names = "uart", "clk_uart_baud0";
+               pinctrl-names = "default";
+               pinctrl-0 = <&serial2_bus>;
+       };
+};

arch/arm/mach-exynos/Kconfig +11 -0

index acab947..52a5a30 100644
@@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
        select SUPPORT_SPL
        select OF_CONTROL
 
+config  TARGET_ESPRESSO7420
+       bool "ESPRESSO7420 board"
+       select ARM64
+       select SUPPORT_SPL
+       select OF_CONTROL
+       select SPL_DISABLE_OF_CONTROL
+       select PINCTRL
+       select PINCTRL_EXYNOS7420
+       select CLK_EXYNOS
+
 endchoice
 
 config SYS_SOC

@@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"
 source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
 
 endif

arch/arm/mach-exynos/Makefile +1 -0

index be5912e..a238a98 100644
@@ -7,6 +7,7 @@
 
 obj-y  += soc.o
 obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
+obj-$(CONFIG_ARM64)    += mmu-arm64.o
 
 obj-$(CONFIG_EXYNOS5420)       += sec_boot.o
 

arch/arm/mach-exynos/mmu-arm64.c new file +35 -0

new file mode 100644
index 0000000..ba6d99d
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+       {
+               .base   = 0x10000000UL,
+               .size   = 0x10000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                               PTE_BLOCK_NON_SHARE |
+                               PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+       }, {
+               .base   = 0x40000000UL,
+               .size   = 0x80000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                               PTE_BLOCK_INNER_SHARE,
+       }, {
+               /* List terminator */
+               .base   = 0,
+               .size   = 0,
+               .attrs  = 0,
+       },
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif

arch/arm/mach-exynos/soc.c +8 -0

index 5cea5ed..0706f5d 100644
@@ -23,3 +23,11 @@ void enable_caches(void)
        dcache_enable();
 }
 #endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+       armv8_switch_to_el2();
+       armv8_switch_to_el1();
+}
+#endif

include/configs/espresso7420.h new file +19 -0

new file mode 100644
index 0000000..2af33e7
@@ -0,0 +1,35 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE          0x40000000

include/configs/espresso7420.h line 25

Quoted 6 lines

include/configs/espresso7420.h new file +6 -0

+#define CONFIG_SYS_TEXT_BASE           0x43E00000
+#define CONFIG_SPL_STACK               CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2         /* use SERIAL 2 */

Is that needed?

Quoted 58 lines

include/configs/espresso7420.h new file +10 -0

+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING    " for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS   8
+#define SDRAM_BANK_SIZE                (256UL << 20UL) /* 256 MB */
+
+#endif /* __CONFIG_ESPRESSO7420_H */

include/configs/exynos7420-common.h new file +41 -0

new file mode 100644
index 0000000..9a7e193
@@ -0,0 +1,117 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG                 /* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420              /* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>              /* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              1024    /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE                        115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */

include/configs/exynos7420-common.h line 47

Quoted 6 lines

include/configs/exynos7420-common.h new file +6 -0

+#define COUNTER_FREQUENCY              24000000
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE                      0x11001000
+#define GICC_BASE                      0x11002000

Can these be in device tree? Or in arch/asm/include/... ?

Quoted 27 lines

include/configs/exynos7420-common.h new file +25 -0

+
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE               0x02100000
 
+#define CONFIG_IRAM_SIZE               0x58000
+#define CONFIG_IRAM_END                        (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT              0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3           (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE      SDRAM_BANK_SIZE

include/configs/exynos7420-common.h line 82

Quoted 10 lines

include/configs/exynos7420-common.h new file +10 -0

+#define PHYS_SDRAM_4           (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5           (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6           (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7           (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE      SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8           (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE      SDRAM_BANK_SIZE

I wish we could use device tree for this cruft. Any way?

Quoted 36 lines

include/configs/exynos7420-common.h new file +35 -1

+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE        (16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+       "bootm_size=0x10000000\0" \
+       "kernel_addr_r=0x42000000\0" \
+       "fdt_addr_r=0x43000000\0" \
+       "ramdisk_addr_r=0x43300000\0" \
+       "scriptaddr=0x50000000\0" \
+       "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+       "stdin=serial\0" \
+       "stdout=serial\0" \
+       "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       EXYNOS_DEVICE_SETTINGS \
+       EXYNOS_FDTFILE_SETTING \
+       MEM_LAYOUT_ENV_SETTINGS
+
+#endif /* __CONFIG_EXYNOS7420_COMMON_H */
--

Quoted 2 lines

1.6.6.rc2

Regards,
Simon