sunxi: mctl_mem_matches: Add missing memory barrier

We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way,

add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases, which was resulting in:

U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiB

U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology

CPU:   Allwinner A23 (SUN8I)
DRAM:  512 MiB

Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB.

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/mach-sunxi/dram_helpers.c | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-sunxi/dram_helpers.c +2 -0

index 50318d2..e0c823a 100644
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/io.h>
 #include <asm/arch/dram.h>
 

@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
 	/* Try to write different values to RAM at two addresses */
 	writel(0, CONFIG_SYS_SDRAM_BASE);
 	writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+	DSB;
 	/* Check if the same value is actually observed when reading back */
 	return readl(CONFIG_SYS_SDRAM_BASE) ==
 	       readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

Hello Hans,

Quoted 2 lines · On Thu, 14 Apr 2016 18:58:04 +0200 Hans de Goede <[email protected]> wrote:

We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way,

This does not make much sense to me. The SPL is running with the MMU disabled, because disabling the MMU is one of the first things done by the SPL at the very start. And when the MMU is disabled, all the data accesses are treated as Strongly-ordered and are not supposed to use the write buffer. A quote from the ARMv7 Architecture Manual:

"a write to Strongly-ordered memory can complete only when it reaches the peripheral or memory component accessed by the write"

We can even verify whether the write buffer is actually in use by simply benchmarking something like the memset function. If the write buffer is working, then the sequential write speed will be around 1 GB/s or more.

Quoted 10 lines

add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases, which was resulting in:

U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiB

U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology

Quoted 5 lines

CPU:   Allwinner A23 (SUN8I)
DRAM:  512 MiB

Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB.

Is it just a single device or board? Has anybody seen anything like this on other devices with the same SoC?

I wonder if what you are observing could be possibly explained by just a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle in a reliable way. Inserting just one or more NOP instructions instead of the barrier could possibly change some timings too.

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

Quoted 6 lines

I wonder if what you are observing could be possibly explained by just a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle in a reliable way. Inserting just one or more NOP instructions instead of the barrier could possibly change some timings too.

Quoted 2 lines

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

I do believe that this patch addresses a real problem and is not hiding some dram timing issues, I might be wrong about the write-buffer being the cause, it could simply be that the compiler is doing something bad (despite the accesses being marked as volatile)??and that the DSB stops the compiler from optimizing things too much.

Quoted 6 lines · Hans de Goede

Quoted 6 lines

I wonder if what you are observing could be possibly explained by just a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle in a reliable way. Inserting just one or more NOP instructions instead of the barrier could possibly change some timings too.

Quoted 7 lines

Quoted 2 lines

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

I do believe that this patch addresses a real problem and is not hiding some dram timing issues, I might be wrong about the write-buffer being the cause, it could simply be that the compiler is doing something bad (despite the accesses being marked as volatile) and that the DSB stops the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this (apparent write buffer interactions with MMU disabled) in the early days of Xen development, but that was probably on models and so may not have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and see if it differs in more or less than the addition of the single instruction and perhaps experiment with just a compiler barrier.

Andre, do you have any insights on this?

Hi,

Quoted 25 lines · Ian Campbell

Quoted 6 lines · Hans de Goede

Quoted 6 lines

I wonder if what you are observing could be possibly explained by just a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle in a reliable way. Inserting just one or more NOP instructions instead of the barrier could possibly change some timings too.

Quoted 7 lines

Quoted 2 lines

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

I do believe that this patch addresses a real problem and is not hiding some dram timing issues, I might be wrong about the write-buffer being the cause, it could simply be that the compiler is doing something bad (despite the accesses being marked as volatile) and that the DSB stops the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this (apparent write buffer interactions with MMU disabled) in the early days of Xen development, but that was probably on models and so may not have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and see if it differs in more or less than the addition of the single instruction and perhaps experiment with just a compiler barrier.

Andre, do you have any insights on this?

Andre here is the original mail/patch for reference:

sunxi: mctl_mem_matches: Add missing memory barrier

We are running with the caches disabled when mctl_mem_matches gets
called,
but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases,
which
was resulting in:

<snip>

arch/arm/mach-sunxi/dram_helpers.c +1 -0

@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
     /* Try to write different values to RAM at two addresses */
     writel(0, CONFIG_SYS_SDRAM_BASE);
     writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+    DSB;
     /* Check if the same value is actually observed when reading back */
     return readl(CONFIG_SYS_SDRAM_BASE) ==
            readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

What this code is trying to do is determine RAM (chip) size by seeing when writing to RAM wrapsaround.

This works with the DSB but not without (without it always returns false) this is on a Cortex A7 with the mmu (and data caches) disabled.

Ian, I can try using just a compiler barrier, but I've never done so before, how do I insert one ?

Hi Hans,

thanks for the information and the heads up!

Quoted 27 lines · Hans de Goede

Hi,

Quoted 24 lines · Ian Campbell

Quoted 6 lines · Hans de Goede

Quoted 6 lines

I wonder if what you are observing could be possibly explained by just a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle in a reliable way. Inserting just one or more NOP instructions instead of the barrier could possibly change some timings too.

Quoted 7 lines

Quoted 2 lines

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

I do believe that this patch addresses a real problem and is not hiding some dram timing issues, I might be wrong about the write-buffer being the cause, it could simply be that the compiler is doing something bad (despite the accesses being marked as volatile) and that the DSB stops the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this (apparent write buffer interactions with MMU disabled) in the early days of Xen development, but that was probably on models and so may not have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and see if it differs in more or less than the addition of the single instruction and perhaps experiment with just a compiler barrier.

Quoted 1 line

Quoted 1 line

Andre, do you have any insights on this?

Agree on the compiler barrier, frankly I don't see how this should break with caches on or off unless the actual instruction order is wrong or the compiler optimized something away.
Regardless of the write buffer the core should make sure the subsequent reads return the value written before - especially if we are talking UP here.

Quoted 27 lines

Andre here is the original mail/patch for reference:

sunxi: mctl_mem_matches: Add missing memory barrier

We are running with the caches disabled when mctl_mem_matches gets
called,
but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases,
which
was resulting in:

<snip>

arch/arm/mach-sunxi/dram_helpers.c +1 -0

@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
      /* Try to write different values to RAM at two addresses */
      writel(0, CONFIG_SYS_SDRAM_BASE);
      writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+    DSB;
      /* Check if the same value is actually observed when reading back */
      return readl(CONFIG_SYS_SDRAM_BASE) ==
             readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

Quoted 8 lines

What this code is trying to do is determine RAM (chip) size by seeing when writing to RAM wrapsaround.

This works with the DSB but not without (without it always returns false) this is on a Cortex A7 with the mmu (and data caches) disabled.

Ian, I can try using just a compiler barrier, but I've never done so before, how do I insert one ?

barrier();

I am busy at the moment, but will take a look later.

Cheers,
Andre.

Hi,

Quoted 37 lines · Andre Przywara

Hi Hans,

thanks for the information and the heads up!

Quoted 32 lines · Hans de Goede

Hi,

Quoted 29 lines · Ian Campbell

Quoted 11 lines · Hans de Goede

Quoted 11 lines

I wonder if what you are observing could be possibly explained by just
a usual data corruption problem? Which may be happening when the DRAM clock speed is set higher than this particular device is able to handle
in a reliable way. Inserting just one or more NOP instructions instead
of the barrier could possibly change some timings too.

If this patch helps, then it's fine. But I wonder if it is not merely making the problem latent instead of fixing the root cause?

Quoted 7 lines

I do believe that this patch addresses a real problem and is not hiding
some dram timing issues, I might be wrong about the write-buffer being the cause, it could simply be that the compiler is doing something bad (despite the accesses being marked as volatile) and that the DSB stops
the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this (apparent write buffer interactions with MMU disabled) in the early days of Xen development, but that was probably on models and so may not have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and see if it differs in more or less than the addition of the single instruction and perhaps experiment with just a compiler barrier.

Quoted 8 lines

Quoted 1 line

Quoted 1 line

Andre, do you have any insights on this?

Agree on the compiler barrier, frankly I don't see how this should break with caches on or off unless the actual instruction order is wrong or the compiler optimized something away.
Regardless of the write buffer the core should make sure the subsequent reads return the value written before - especially if we are talking UP here.

"the core should make sure the subsequent reads return the value written before"
that is exactly the problem, we are writing 2 different values to so DRAM_BASE and DRAM_BASE + 512MiB, then read them both back and compare them, expecting them to be the same (both reads returning the last written value) if the ramsize is 512MiB (this is used in several places
in the dram controller code to auto-config number of rows, columns, etc.).

But the core seems to just return the last written value, rather then actually going out to the RAM and reading it from there, which results in the function always returning false (i.o.w. it claims no DRAM phys address wraparound is happening
at 512MiB).

The DSB seems to fix this, but it might very well be the compiler being to clever (although all accesses are done through volatile pointers, so it really should not).

I'll try the barrier() fix when I've some time.

Regards,

Hans

Quoted 47 lines

Quoted 33 lines

Andre here is the original mail/patch for reference:

sunxi: mctl_mem_matches: Add missing memory barrier

We are running with the caches disabled when mctl_mem_matches gets
called,
but the cpu's write buffer is still there and can still get in
the way,
add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases,
which
was resulting in:

<snip>

(quoted diff) +1 -0

@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
      /* Try to write different values to RAM at two addresses */
      writel(0, CONFIG_SYS_SDRAM_BASE);
      writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+    DSB;
      /* Check if the same value is actually observed when reading

back */

      return readl(CONFIG_SYS_SDRAM_BASE) ==
             readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

What this code is trying to do is determine RAM (chip) size by seeing when
writing to RAM wrapsaround.

Quoted 6 lines

This works with the DSB but not without (without it always returns false)
this is on a Cortex A7 with the mmu (and data caches) disabled.

Ian, I can try using just a compiler barrier, but I've never done so before, how do I insert one ?

barrier();

I am busy at the moment, but will take a look later.

Cheers,
Andre.

Hi,

Quoted 85 lines · Hans de Goede

Hi,

Quoted 59 lines · Andre Przywara

Hi Hans,

thanks for the information and the heads up!

Quoted 53 lines · Hans de Goede

Hi,

Quoted 49 lines · Ian Campbell

Quoted 19 lines · Hans de Goede

Quoted 15 lines

I wonder if what you are observing could be possibly explained by
just
a usual data corruption problem? Which may be happening when the DRAM
clock speed is set higher than this particular device is able to
handle
in a reliable way. Inserting just one or more NOP instructions
instead
of the barrier could possibly change some timings too.

Quoted 4 lines

If this patch helps, then it's fine. But I wonder if it is not merely
making the problem latent instead of fixing the root cause?

Quoted 11 lines

I do believe that this patch addresses a real problem and is not
hiding
some dram timing issues, I might be wrong about the write- buffer being
the cause, it could simply be that the compiler is doing something bad
(despite the accesses being marked as volatile)??and that the DSB
stops
the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this
(apparent write buffer interactions with MMU disabled) in the early
days of Xen development, but that was probably on models and so may not
have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and
see if it differs in more or less than the addition of the single
instruction and perhaps experiment with just a compiler barrier.

Andre, do you have any insights on this?

Quoted 10 lines

Agree on the compiler barrier, frankly I don't see how this should break
with caches on or off unless the actual instruction order is wrong or
the compiler optimized something away.
Regardless of the write buffer the core should make sure the subsequent
reads return the value written before - especially if we are talking UP
here.

"the core should make sure the subsequent reads return the value written
before"
that is exactly the problem, we are writing 2 different values to so DRAM_BASE and DRAM_BASE + 512MiB, then read them both back and compare them, expecting them to be the same (both reads returning
the last written value) if the ramsize is 512MiB (this is used in several places
in the dram controller code to auto-config number of rows, columns, etc.).

Quoted 5 lines

But the core seems to just return the last written value, rather then actually going out to the RAM and reading it from there, which results in the function always returning false (i.o.w. it claims no DRAM phys address wraparound is happening ?at 512MiB).

Oh, right, I missed that part, sorry.
So this is about physical aliasing?
The DRAM controller has only n address lines connected, and changing a line >n shouldn't make a difference, right?

And the write succeeds and does trigger an asynchronous abort?

So I did a quick poll around the office and people say that "dsb" is the right thing to do here (with MMU off).
As this is backed by practical experience, I'd just say: good to go!